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x86-gcc-cpuid.h
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1 /*
2  * Helper cpuid.h file copied from gcc-4.8.0. Code in gdb should not
3  * include this directly, but pull in x86-cpuid.h and use that func.
4  */
5 /*
6  * Copyright (C) 2007-2015 Free Software Foundation, Inc.
7  *
8  * This file is free software; you can redistribute it and/or modify it
9  * under the terms of the GNU General Public License as published by the
10  * Free Software Foundation; either version 3, or (at your option) any
11  * later version.
12  *
13  * This file is distributed in the hope that it will be useful, but
14  * WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16  * General Public License for more details.
17  *
18  * Under Section 7 of GPL version 3, you are granted additional
19  * permissions described in the GCC Runtime Library Exception, version
20  * 3.1, as published by the Free Software Foundation.
21  *
22  * You should have received a copy of the GNU General Public License and
23  * a copy of the GCC Runtime Library Exception along with this program;
24  * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
25  * <http://www.gnu.org/licenses/>.
26  */
27 
28 /* %ecx */
29 #define bit_SSE3 (1 << 0)
30 #define bit_PCLMUL (1 << 1)
31 #define bit_LZCNT (1 << 5)
32 #define bit_SSSE3 (1 << 9)
33 #define bit_FMA (1 << 12)
34 #define bit_CMPXCHG16B (1 << 13)
35 #define bit_SSE4_1 (1 << 19)
36 #define bit_SSE4_2 (1 << 20)
37 #define bit_MOVBE (1 << 22)
38 #define bit_POPCNT (1 << 23)
39 #define bit_AES (1 << 25)
40 #define bit_XSAVE (1 << 26)
41 #define bit_OSXSAVE (1 << 27)
42 #define bit_AVX (1 << 28)
43 #define bit_F16C (1 << 29)
44 #define bit_RDRND (1 << 30)
45 
46 /* %edx */
47 #define bit_CMPXCHG8B (1 << 8)
48 #define bit_CMOV (1 << 15)
49 #define bit_MMX (1 << 23)
50 #define bit_FXSAVE (1 << 24)
51 #define bit_SSE (1 << 25)
52 #define bit_SSE2 (1 << 26)
53 
54 /* Extended Features */
55 /* %ecx */
56 #define bit_LAHF_LM (1 << 0)
57 #define bit_ABM (1 << 5)
58 #define bit_SSE4a (1 << 6)
59 #define bit_PRFCHW (1 << 8)
60 #define bit_XOP (1 << 11)
61 #define bit_LWP (1 << 15)
62 #define bit_FMA4 (1 << 16)
63 #define bit_TBM (1 << 21)
64 
65 /* %edx */
66 #define bit_MMXEXT (1 << 22)
67 #define bit_LM (1 << 29)
68 #define bit_3DNOWP (1 << 30)
69 #define bit_3DNOW (1 << 31)
70 
71 /* Extended Features (%eax == 7) */
72 #define bit_FSGSBASE (1 << 0)
73 #define bit_BMI (1 << 3)
74 #define bit_HLE (1 << 4)
75 #define bit_AVX2 (1 << 5)
76 #define bit_BMI2 (1 << 8)
77 #define bit_RTM (1 << 11)
78 #define bit_AVX512F (1 << 16)
79 #define bit_MPX (1 << 14)
80 #define bit_RDSEED (1 << 18)
81 #define bit_ADX (1 << 19)
82 #define bit_AVX512PF (1 << 26)
83 #define bit_AVX512ER (1 << 27)
84 #define bit_AVX512CD (1 << 28)
85 #define bit_SHA (1 << 29)
86 
87 /* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
88 #define bit_XSAVEOPT (1 << 0)
89 
90 /* Signatures for different CPU implementations as returned in uses
91  of cpuid with level 0. */
92 #define signature_AMD_ebx 0x68747541
93 #define signature_AMD_ecx 0x444d4163
94 #define signature_AMD_edx 0x69746e65
95 
96 #define signature_CENTAUR_ebx 0x746e6543
97 #define signature_CENTAUR_ecx 0x736c7561
98 #define signature_CENTAUR_edx 0x48727561
99 
100 #define signature_CYRIX_ebx 0x69727943
101 #define signature_CYRIX_ecx 0x64616574
102 #define signature_CYRIX_edx 0x736e4978
103 
104 #define signature_INTEL_ebx 0x756e6547
105 #define signature_INTEL_ecx 0x6c65746e
106 #define signature_INTEL_edx 0x49656e69
107 
108 #define signature_TM1_ebx 0x6e617254
109 #define signature_TM1_ecx 0x55504361
110 #define signature_TM1_edx 0x74656d73
111 
112 #define signature_TM2_ebx 0x756e6547
113 #define signature_TM2_ecx 0x3638784d
114 #define signature_TM2_edx 0x54656e69
115 
116 #define signature_NSC_ebx 0x646f6547
117 #define signature_NSC_ecx 0x43534e20
118 #define signature_NSC_edx 0x79622065
119 
120 #define signature_NEXGEN_ebx 0x4778654e
121 #define signature_NEXGEN_ecx 0x6e657669
122 #define signature_NEXGEN_edx 0x72446e65
123 
124 #define signature_RISE_ebx 0x65736952
125 #define signature_RISE_ecx 0x65736952
126 #define signature_RISE_edx 0x65736952
127 
128 #define signature_SIS_ebx 0x20536953
129 #define signature_SIS_ecx 0x20536953
130 #define signature_SIS_edx 0x20536953
131 
132 #define signature_UMC_ebx 0x20434d55
133 #define signature_UMC_ecx 0x20434d55
134 #define signature_UMC_edx 0x20434d55
135 
136 #define signature_VIA_ebx 0x20414956
137 #define signature_VIA_ecx 0x20414956
138 #define signature_VIA_edx 0x20414956
139 
140 #define signature_VORTEX_ebx 0x74726f56
141 #define signature_VORTEX_ecx 0x436f5320
142 #define signature_VORTEX_edx 0x36387865
143 
144 #if defined(__i386__) && defined(__PIC__)
145 /* %ebx may be the PIC register. */
146 #if __GNUC__ >= 3
147 #define __cpuid(level, a, b, c, d) \
148  __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t" \
149  "cpuid\n\t" \
150  "xchg{l}\t{%%}ebx, %k1\n\t" \
151  : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
152  : "0" (level))
153 
154 #define __cpuid_count(level, count, a, b, c, d) \
155  __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t" \
156  "cpuid\n\t" \
157  "xchg{l}\t{%%}ebx, %k1\n\t" \
158  : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
159  : "0" (level), "2" (count))
160 #else
161 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
162  nor alternatives in i386 code. */
163 #define __cpuid(level, a, b, c, d) \
164  __asm__ ("xchgl\t%%ebx, %k1\n\t" \
165  "cpuid\n\t" \
166  "xchgl\t%%ebx, %k1\n\t" \
167  : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
168  : "0" (level))
169 
170 #define __cpuid_count(level, count, a, b, c, d) \
171  __asm__ ("xchgl\t%%ebx, %k1\n\t" \
172  "cpuid\n\t" \
173  "xchgl\t%%ebx, %k1\n\t" \
174  : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
175  : "0" (level), "2" (count))
176 #endif
177 #elif defined(__x86_64__) && (defined(__code_model_medium__) || defined(__code_model_large__)) && defined(__PIC__)
178 /* %rbx may be the PIC register. */
179 #define __cpuid(level, a, b, c, d) \
180  __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \
181  "cpuid\n\t" \
182  "xchg{q}\t{%%}rbx, %q1\n\t" \
183  : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
184  : "0" (level))
185 
186 #define __cpuid_count(level, count, a, b, c, d) \
187  __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \
188  "cpuid\n\t" \
189  "xchg{q}\t{%%}rbx, %q1\n\t" \
190  : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
191  : "0" (level), "2" (count))
192 #else
193 #define __cpuid(level, a, b, c, d) \
194  __asm__ ("cpuid\n\t" \
195  : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
196  : "0" (level))
197 
198 #define __cpuid_count(level, count, a, b, c, d) \
199  __asm__ ("cpuid\n\t" \
200  : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
201  : "0" (level), "2" (count))
202 #endif
203 
204 /* Return highest supported input value for cpuid instruction. ext can
205  be either 0x0 or 0x8000000 to return highest supported value for
206  basic or extended cpuid information. Function returns 0 if cpuid
207  is not supported or whatever cpuid returns in eax register. If sig
208  pointer is non-null, then first four bytes of the signature
209  (as found in ebx register) are returned in location pointed by sig. */
210 
211 static __inline unsigned int
212 __get_cpuid_max (unsigned int __ext, unsigned int *__sig)
213 {
214  unsigned int __eax, __ebx, __ecx, __edx;
215 
216 #ifndef __x86_64__
217  /* See if we can use cpuid. On AMD64 we always can. */
218 #if __GNUC__ >= 3
219  __asm__ ("pushf{l|d}\n\t"
220  "pushf{l|d}\n\t"
221  "pop{l}\t%0\n\t"
222  "mov{l}\t{%0, %1|%1, %0}\n\t"
223  "xor{l}\t{%2, %0|%0, %2}\n\t"
224  "push{l}\t%0\n\t"
225  "popf{l|d}\n\t"
226  "pushf{l|d}\n\t"
227  "pop{l}\t%0\n\t"
228  "popf{l|d}\n\t"
229  : "=&r" (__eax), "=&r" (__ebx)
230  : "i" (0x00200000));
231 #else
232 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
233  nor alternatives in i386 code. */
234  __asm__ ("pushfl\n\t"
235  "pushfl\n\t"
236  "popl\t%0\n\t"
237  "movl\t%0, %1\n\t"
238  "xorl\t%2, %0\n\t"
239  "pushl\t%0\n\t"
240  "popfl\n\t"
241  "pushfl\n\t"
242  "popl\t%0\n\t"
243  "popfl\n\t"
244  : "=&r" (__eax), "=&r" (__ebx)
245  : "i" (0x00200000));
246 #endif
247 
248  if (!((__eax ^ __ebx) & 0x00200000))
249  return 0;
250 #endif
251 
252  /* Host supports cpuid. Return highest supported cpuid input value. */
253  __cpuid (__ext, __eax, __ebx, __ecx, __edx);
254 
255  if (__sig)
256  *__sig = __ebx;
257 
258  return __eax;
259 }
260 
261 /* Return cpuid data for requested cpuid level, as found in returned
262  eax, ebx, ecx and edx registers. The function checks if cpuid is
263  supported and returns 1 for valid cpuid information or 0 for
264  unsupported cpuid level. All pointers are required to be non-null. */
265 
266 static __inline int
267 __get_cpuid (unsigned int __level,
268  unsigned int *__eax, unsigned int *__ebx,
269  unsigned int *__ecx, unsigned int *__edx)
270 {
271  unsigned int __ext = __level & 0x80000000;
272 
273  if (__get_cpuid_max (__ext, 0) < __level)
274  return 0;
275 
276  __cpuid (__level, *__eax, *__ebx, *__ecx, *__edx);
277  return 1;
278 }
static __inline unsigned int __get_cpuid_max(unsigned int __ext, unsigned int *__sig)
static __inline int __get_cpuid(unsigned int __level, unsigned int *__eax, unsigned int *__ebx, unsigned int *__ecx, unsigned int *__edx)
#define __cpuid(level, a, b, c, d)