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/tmp/gdb-7.10/gdb/amd64-tdep.c
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1 /* Target-dependent code for AMD64.
2 
3  Copyright (C) 2001-2015 Free Software Foundation, Inc.
4 
5  Contributed by Jiri Smid, SuSE Labs.
6 
7  This file is part of GDB.
8 
9  This program is free software; you can redistribute it and/or modify
10  it under the terms of the GNU General Public License as published by
11  the Free Software Foundation; either version 3 of the License, or
12  (at your option) any later version.
13 
14  This program is distributed in the hope that it will be useful,
15  but WITHOUT ANY WARRANTY; without even the implied warranty of
16  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17  GNU General Public License for more details.
18 
19  You should have received a copy of the GNU General Public License
20  along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 
22 #include "defs.h"
23 #include "opcode/i386.h"
24 #include "dis-asm.h"
25 #include "arch-utils.h"
26 #include "block.h"
27 #include "dummy-frame.h"
28 #include "frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
31 #include "inferior.h"
32 #include "infrun.h"
33 #include "gdbcmd.h"
34 #include "gdbcore.h"
35 #include "objfiles.h"
36 #include "regcache.h"
37 #include "regset.h"
38 #include "symfile.h"
39 #include "disasm.h"
40 #include "amd64-tdep.h"
41 #include "i387-tdep.h"
42 #include "x86-xstate.h"
43 
44 #include "features/i386/amd64.c"
48 
49 #include "features/i386/x32.c"
50 #include "features/i386/x32-avx.c"
52 
53 #include "ax.h"
54 #include "ax-gdb.h"
55 
56 /* Note that the AMD64 architecture was previously known as x86-64.
57  The latter is (forever) engraved into the canonical system name as
58  returned by config.guess, and used as the name for the AMD64 port
59  of GNU/Linux. The BSD's have renamed their ports to amd64; they
60  don't like to shout. For GDB we prefer the amd64_-prefix over the
61  x86_64_-prefix since it's so much easier to type. */
62 
63 /* Register information. */
64 
65 static const char *amd64_register_names[] =
66 {
67  "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
68 
69  /* %r8 is indeed register number 8. */
70  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
71  "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
72 
73  /* %st0 is register number 24. */
74  "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
75  "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
76 
77  /* %xmm0 is register number 40. */
78  "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
79  "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
80  "mxcsr",
81 };
82 
83 static const char *amd64_ymm_names[] =
84 {
85  "ymm0", "ymm1", "ymm2", "ymm3",
86  "ymm4", "ymm5", "ymm6", "ymm7",
87  "ymm8", "ymm9", "ymm10", "ymm11",
88  "ymm12", "ymm13", "ymm14", "ymm15"
89 };
90 
91 static const char *amd64_ymm_avx512_names[] =
92 {
93  "ymm16", "ymm17", "ymm18", "ymm19",
94  "ymm20", "ymm21", "ymm22", "ymm23",
95  "ymm24", "ymm25", "ymm26", "ymm27",
96  "ymm28", "ymm29", "ymm30", "ymm31"
97 };
98 
99 static const char *amd64_ymmh_names[] =
100 {
101  "ymm0h", "ymm1h", "ymm2h", "ymm3h",
102  "ymm4h", "ymm5h", "ymm6h", "ymm7h",
103  "ymm8h", "ymm9h", "ymm10h", "ymm11h",
104  "ymm12h", "ymm13h", "ymm14h", "ymm15h"
105 };
106 
107 static const char *amd64_ymmh_avx512_names[] =
108 {
109  "ymm16h", "ymm17h", "ymm18h", "ymm19h",
110  "ymm20h", "ymm21h", "ymm22h", "ymm23h",
111  "ymm24h", "ymm25h", "ymm26h", "ymm27h",
112  "ymm28h", "ymm29h", "ymm30h", "ymm31h"
113 };
114 
115 static const char *amd64_mpx_names[] =
116 {
117  "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
118 };
119 
120 static const char *amd64_k_names[] =
121 {
122  "k0", "k1", "k2", "k3",
123  "k4", "k5", "k6", "k7"
124 };
125 
126 static const char *amd64_zmmh_names[] =
127 {
128  "zmm0h", "zmm1h", "zmm2h", "zmm3h",
129  "zmm4h", "zmm5h", "zmm6h", "zmm7h",
130  "zmm8h", "zmm9h", "zmm10h", "zmm11h",
131  "zmm12h", "zmm13h", "zmm14h", "zmm15h",
132  "zmm16h", "zmm17h", "zmm18h", "zmm19h",
133  "zmm20h", "zmm21h", "zmm22h", "zmm23h",
134  "zmm24h", "zmm25h", "zmm26h", "zmm27h",
135  "zmm28h", "zmm29h", "zmm30h", "zmm31h"
136 };
137 
138 static const char *amd64_zmm_names[] =
139 {
140  "zmm0", "zmm1", "zmm2", "zmm3",
141  "zmm4", "zmm5", "zmm6", "zmm7",
142  "zmm8", "zmm9", "zmm10", "zmm11",
143  "zmm12", "zmm13", "zmm14", "zmm15",
144  "zmm16", "zmm17", "zmm18", "zmm19",
145  "zmm20", "zmm21", "zmm22", "zmm23",
146  "zmm24", "zmm25", "zmm26", "zmm27",
147  "zmm28", "zmm29", "zmm30", "zmm31"
148 };
149 
150 static const char *amd64_xmm_avx512_names[] = {
151  "xmm16", "xmm17", "xmm18", "xmm19",
152  "xmm20", "xmm21", "xmm22", "xmm23",
153  "xmm24", "xmm25", "xmm26", "xmm27",
154  "xmm28", "xmm29", "xmm30", "xmm31"
155 };
156 
157 /* DWARF Register Number Mapping as defined in the System V psABI,
158  section 3.6. */
159 
160 static int amd64_dwarf_regmap[] =
161 {
162  /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
166 
167  /* Frame Pointer Register RBP. */
169 
170  /* Stack Pointer Register RSP. */
172 
173  /* Extended Integer Registers 8 - 15. */
174  AMD64_R8_REGNUM, /* %r8 */
175  AMD64_R9_REGNUM, /* %r9 */
176  AMD64_R10_REGNUM, /* %r10 */
177  AMD64_R11_REGNUM, /* %r11 */
178  AMD64_R12_REGNUM, /* %r12 */
179  AMD64_R13_REGNUM, /* %r13 */
180  AMD64_R14_REGNUM, /* %r14 */
181  AMD64_R15_REGNUM, /* %r15 */
182 
183  /* Return Address RA. Mapped to RIP. */
185 
186  /* SSE Registers 0 - 7. */
188  AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
189  AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
190  AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
191 
192  /* Extended SSE Registers 8 - 15. */
193  AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
194  AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
195  AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
196  AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
197 
198  /* Floating Point Registers 0-7. */
199  AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
200  AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
201  AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
202  AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
203 
204  /* MMX Registers 0 - 7.
205  We have to handle those registers specifically, as their register
206  number within GDB depends on the target (or they may even not be
207  available at all). */
208  -1, -1, -1, -1, -1, -1, -1, -1,
209 
210  /* Control and Status Flags Register. */
212 
213  /* Selector Registers. */
220  -1,
221  -1,
222 
223  /* Segment Base Address Registers. */
224  -1,
225  -1,
226  -1,
227  -1,
228 
229  /* Special Selector Registers. */
230  -1,
231  -1,
232 
233  /* Floating Point Control Registers. */
237 };
238 
239 static const int amd64_dwarf_regmap_len =
240  (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
241 
242 /* Convert DWARF register number REG to the appropriate register
243  number used by GDB. */
244 
245 static int
246 amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
247 {
248  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
249  int ymm0_regnum = tdep->ymm0_regnum;
250  int regnum = -1;
251 
252  if (reg >= 0 && reg < amd64_dwarf_regmap_len)
253  regnum = amd64_dwarf_regmap[reg];
254 
255  if (regnum == -1)
256  warning (_("Unmapped DWARF Register #%d encountered."), reg);
257  else if (ymm0_regnum >= 0
258  && i386_xmm_regnum_p (gdbarch, regnum))
259  regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep);
260 
261  return regnum;
262 }
263 
264 /* Map architectural register numbers to gdb register numbers. */
265 
266 static const int amd64_arch_regmap[16] =
267 {
268  AMD64_RAX_REGNUM, /* %rax */
269  AMD64_RCX_REGNUM, /* %rcx */
270  AMD64_RDX_REGNUM, /* %rdx */
271  AMD64_RBX_REGNUM, /* %rbx */
272  AMD64_RSP_REGNUM, /* %rsp */
273  AMD64_RBP_REGNUM, /* %rbp */
274  AMD64_RSI_REGNUM, /* %rsi */
275  AMD64_RDI_REGNUM, /* %rdi */
276  AMD64_R8_REGNUM, /* %r8 */
277  AMD64_R9_REGNUM, /* %r9 */
278  AMD64_R10_REGNUM, /* %r10 */
279  AMD64_R11_REGNUM, /* %r11 */
280  AMD64_R12_REGNUM, /* %r12 */
281  AMD64_R13_REGNUM, /* %r13 */
282  AMD64_R14_REGNUM, /* %r14 */
283  AMD64_R15_REGNUM /* %r15 */
284 };
285 
286 static const int amd64_arch_regmap_len =
287  (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0]));
288 
289 /* Convert architectural register number REG to the appropriate register
290  number used by GDB. */
291 
292 static int
294 {
295  gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len);
296 
297  return amd64_arch_regmap[reg];
298 }
299 
300 /* Register names for byte pseudo-registers. */
301 
302 static const char *amd64_byte_names[] =
303 {
304  "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
305  "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
306  "ah", "bh", "ch", "dh"
307 };
308 
309 /* Number of lower byte registers. */
310 #define AMD64_NUM_LOWER_BYTE_REGS 16
311 
312 /* Register names for word pseudo-registers. */
313 
314 static const char *amd64_word_names[] =
315 {
316  "ax", "bx", "cx", "dx", "si", "di", "bp", "",
317  "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
318 };
319 
320 /* Register names for dword pseudo-registers. */
321 
322 static const char *amd64_dword_names[] =
323 {
324  "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
325  "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
326  "eip"
327 };
328 
329 /* Return the name of register REGNUM. */
330 
331 static const char *
332 amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
333 {
334  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
335  if (i386_byte_regnum_p (gdbarch, regnum))
336  return amd64_byte_names[regnum - tdep->al_regnum];
337  else if (i386_zmm_regnum_p (gdbarch, regnum))
338  return amd64_zmm_names[regnum - tdep->zmm0_regnum];
339  else if (i386_ymm_regnum_p (gdbarch, regnum))
340  return amd64_ymm_names[regnum - tdep->ymm0_regnum];
341  else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
342  return amd64_ymm_avx512_names[regnum - tdep->ymm16_regnum];
343  else if (i386_word_regnum_p (gdbarch, regnum))
344  return amd64_word_names[regnum - tdep->ax_regnum];
345  else if (i386_dword_regnum_p (gdbarch, regnum))
346  return amd64_dword_names[regnum - tdep->eax_regnum];
347  else
348  return i386_pseudo_register_name (gdbarch, regnum);
349 }
350 
351 static struct value *
352 amd64_pseudo_register_read_value (struct gdbarch *gdbarch,
353  struct regcache *regcache,
354  int regnum)
355 {
356  gdb_byte raw_buf[MAX_REGISTER_SIZE];
357  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
358  enum register_status status;
359  struct value *result_value;
360  gdb_byte *buf;
361 
362  result_value = allocate_value (register_type (gdbarch, regnum));
363  VALUE_LVAL (result_value) = lval_register;
364  VALUE_REGNUM (result_value) = regnum;
365  buf = value_contents_raw (result_value);
366 
367  if (i386_byte_regnum_p (gdbarch, regnum))
368  {
369  int gpnum = regnum - tdep->al_regnum;
370 
371  /* Extract (always little endian). */
372  if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
373  {
374  /* Special handling for AH, BH, CH, DH. */
375  status = regcache_raw_read (regcache,
377  raw_buf);
378  if (status == REG_VALID)
379  memcpy (buf, raw_buf + 1, 1);
380  else
381  mark_value_bytes_unavailable (result_value, 0,
382  TYPE_LENGTH (value_type (result_value)));
383  }
384  else
385  {
386  status = regcache_raw_read (regcache, gpnum, raw_buf);
387  if (status == REG_VALID)
388  memcpy (buf, raw_buf, 1);
389  else
390  mark_value_bytes_unavailable (result_value, 0,
391  TYPE_LENGTH (value_type (result_value)));
392  }
393  }
394  else if (i386_dword_regnum_p (gdbarch, regnum))
395  {
396  int gpnum = regnum - tdep->eax_regnum;
397  /* Extract (always little endian). */
398  status = regcache_raw_read (regcache, gpnum, raw_buf);
399  if (status == REG_VALID)
400  memcpy (buf, raw_buf, 4);
401  else
402  mark_value_bytes_unavailable (result_value, 0,
403  TYPE_LENGTH (value_type (result_value)));
404  }
405  else
406  i386_pseudo_register_read_into_value (gdbarch, regcache, regnum,
407  result_value);
408 
409  return result_value;
410 }
411 
412 static void
413 amd64_pseudo_register_write (struct gdbarch *gdbarch,
414  struct regcache *regcache,
415  int regnum, const gdb_byte *buf)
416 {
417  gdb_byte raw_buf[MAX_REGISTER_SIZE];
418  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
419 
420  if (i386_byte_regnum_p (gdbarch, regnum))
421  {
422  int gpnum = regnum - tdep->al_regnum;
423 
424  if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
425  {
426  /* Read ... AH, BH, CH, DH. */
427  regcache_raw_read (regcache,
428  gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
429  /* ... Modify ... (always little endian). */
430  memcpy (raw_buf + 1, buf, 1);
431  /* ... Write. */
432  regcache_raw_write (regcache,
433  gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
434  }
435  else
436  {
437  /* Read ... */
438  regcache_raw_read (regcache, gpnum, raw_buf);
439  /* ... Modify ... (always little endian). */
440  memcpy (raw_buf, buf, 1);
441  /* ... Write. */
442  regcache_raw_write (regcache, gpnum, raw_buf);
443  }
444  }
445  else if (i386_dword_regnum_p (gdbarch, regnum))
446  {
447  int gpnum = regnum - tdep->eax_regnum;
448 
449  /* Read ... */
450  regcache_raw_read (regcache, gpnum, raw_buf);
451  /* ... Modify ... (always little endian). */
452  memcpy (raw_buf, buf, 4);
453  /* ... Write. */
454  regcache_raw_write (regcache, gpnum, raw_buf);
455  }
456  else
457  i386_pseudo_register_write (gdbarch, regcache, regnum, buf);
458 }
459 
460 
461 
462 /* Register classes as defined in the psABI. */
463 
465 {
474 };
475 
476 /* Return the union class of CLASS1 and CLASS2. See the psABI for
477  details. */
478 
479 static enum amd64_reg_class
481 {
482  /* Rule (a): If both classes are equal, this is the resulting class. */
483  if (class1 == class2)
484  return class1;
485 
486  /* Rule (b): If one of the classes is NO_CLASS, the resulting class
487  is the other class. */
488  if (class1 == AMD64_NO_CLASS)
489  return class2;
490  if (class2 == AMD64_NO_CLASS)
491  return class1;
492 
493  /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
494  if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
495  return AMD64_MEMORY;
496 
497  /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
498  if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
499  return AMD64_INTEGER;
500 
501  /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
502  MEMORY is used as class. */
503  if (class1 == AMD64_X87 || class1 == AMD64_X87UP
504  || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
505  || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
506  return AMD64_MEMORY;
507 
508  /* Rule (f): Otherwise class SSE is used. */
509  return AMD64_SSE;
510 }
511 
512 static void amd64_classify (struct type *type, enum amd64_reg_class theclass[2]);
513 
514 /* Return non-zero if TYPE is a non-POD structure or union type. */
515 
516 static int
518 {
519  /* ??? A class with a base class certainly isn't POD, but does this
520  catch all non-POD structure types? */
521  if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0)
522  return 1;
523 
524  return 0;
525 }
526 
527 /* Classify TYPE according to the rules for aggregate (structures and
528  arrays) and union types, and store the result in CLASS. */
529 
530 static void
532 {
533  /* 1. If the size of an object is larger than two eightbytes, or in
534  C++, is a non-POD structure or union type, or contains
535  unaligned fields, it has class memory. */
536  if (TYPE_LENGTH (type) > 16 || amd64_non_pod_p (type))
537  {
538  theclass[0] = theclass[1] = AMD64_MEMORY;
539  return;
540  }
541 
542  /* 2. Both eightbytes get initialized to class NO_CLASS. */
543  theclass[0] = theclass[1] = AMD64_NO_CLASS;
544 
545  /* 3. Each field of an object is classified recursively so that
546  always two fields are considered. The resulting class is
547  calculated according to the classes of the fields in the
548  eightbyte: */
549 
550  if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
551  {
552  struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
553 
554  /* All fields in an array have the same type. */
555  amd64_classify (subtype, theclass);
556  if (TYPE_LENGTH (type) > 8 && theclass[1] == AMD64_NO_CLASS)
557  theclass[1] = theclass[0];
558  }
559  else
560  {
561  int i;
562 
563  /* Structure or union. */
565  || TYPE_CODE (type) == TYPE_CODE_UNION);
566 
567  for (i = 0; i < TYPE_NFIELDS (type); i++)
568  {
569  struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
570  int pos = TYPE_FIELD_BITPOS (type, i) / 64;
571  enum amd64_reg_class subclass[2];
572  int bitsize = TYPE_FIELD_BITSIZE (type, i);
573  int endpos;
574 
575  if (bitsize == 0)
576  bitsize = TYPE_LENGTH (subtype) * 8;
577  endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64;
578 
579  /* Ignore static fields. */
580  if (field_is_static (&TYPE_FIELD (type, i)))
581  continue;
582 
583  gdb_assert (pos == 0 || pos == 1);
584 
585  amd64_classify (subtype, subclass);
586  theclass[pos] = amd64_merge_classes (theclass[pos], subclass[0]);
587  if (bitsize <= 64 && pos == 0 && endpos == 1)
588  /* This is a bit of an odd case: We have a field that would
589  normally fit in one of the two eightbytes, except that
590  it is placed in a way that this field straddles them.
591  This has been seen with a structure containing an array.
592 
593  The ABI is a bit unclear in this case, but we assume that
594  this field's class (stored in subclass[0]) must also be merged
595  into class[1]. In other words, our field has a piece stored
596  in the second eight-byte, and thus its class applies to
597  the second eight-byte as well.
598 
599  In the case where the field length exceeds 8 bytes,
600  it should not be necessary to merge the field class
601  into class[1]. As LEN > 8, subclass[1] is necessarily
602  different from AMD64_NO_CLASS. If subclass[1] is equal
603  to subclass[0], then the normal class[1]/subclass[1]
604  merging will take care of everything. For subclass[1]
605  to be different from subclass[0], I can only see the case
606  where we have a SSE/SSEUP or X87/X87UP pair, which both
607  use up all 16 bytes of the aggregate, and are already
608  handled just fine (because each portion sits on its own
609  8-byte). */
610  theclass[1] = amd64_merge_classes (theclass[1], subclass[0]);
611  if (pos == 0)
612  theclass[1] = amd64_merge_classes (theclass[1], subclass[1]);
613  }
614  }
615 
616  /* 4. Then a post merger cleanup is done: */
617 
618  /* Rule (a): If one of the classes is MEMORY, the whole argument is
619  passed in memory. */
620  if (theclass[0] == AMD64_MEMORY || theclass[1] == AMD64_MEMORY)
621  theclass[0] = theclass[1] = AMD64_MEMORY;
622 
623  /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
624  SSE. */
625  if (theclass[0] == AMD64_SSEUP)
626  theclass[0] = AMD64_SSE;
627  if (theclass[1] == AMD64_SSEUP && theclass[0] != AMD64_SSE)
628  theclass[1] = AMD64_SSE;
629 }
630 
631 /* Classify TYPE, and store the result in CLASS. */
632 
633 static void
634 amd64_classify (struct type *type, enum amd64_reg_class theclass[2])
635 {
636  enum type_code code = TYPE_CODE (type);
637  int len = TYPE_LENGTH (type);
638 
639  theclass[0] = theclass[1] = AMD64_NO_CLASS;
640 
641  /* Arguments of types (signed and unsigned) _Bool, char, short, int,
642  long, long long, and pointers are in the INTEGER class. Similarly,
643  range types, used by languages such as Ada, are also in the INTEGER
644  class. */
645  if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
646  || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
647  || code == TYPE_CODE_CHAR
648  || code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
649  && (len == 1 || len == 2 || len == 4 || len == 8))
650  theclass[0] = AMD64_INTEGER;
651 
652  /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
653  are in class SSE. */
654  else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT)
655  && (len == 4 || len == 8))
656  /* FIXME: __m64 . */
657  theclass[0] = AMD64_SSE;
658 
659  /* Arguments of types __float128, _Decimal128 and __m128 are split into
660  two halves. The least significant ones belong to class SSE, the most
661  significant one to class SSEUP. */
662  else if (code == TYPE_CODE_DECFLOAT && len == 16)
663  /* FIXME: __float128, __m128. */
664  theclass[0] = AMD64_SSE, theclass[1] = AMD64_SSEUP;
665 
666  /* The 64-bit mantissa of arguments of type long double belongs to
667  class X87, the 16-bit exponent plus 6 bytes of padding belongs to
668  class X87UP. */
669  else if (code == TYPE_CODE_FLT && len == 16)
670  /* Class X87 and X87UP. */
671  theclass[0] = AMD64_X87, theclass[1] = AMD64_X87UP;
672 
673  /* Arguments of complex T where T is one of the types float or
674  double get treated as if they are implemented as:
675 
676  struct complexT {
677  T real;
678  T imag;
679  };
680 
681  */
682  else if (code == TYPE_CODE_COMPLEX && len == 8)
683  theclass[0] = AMD64_SSE;
684  else if (code == TYPE_CODE_COMPLEX && len == 16)
685  theclass[0] = theclass[1] = AMD64_SSE;
686 
687  /* A variable of type complex long double is classified as type
688  COMPLEX_X87. */
689  else if (code == TYPE_CODE_COMPLEX && len == 32)
690  theclass[0] = AMD64_COMPLEX_X87;
691 
692  /* Aggregates. */
693  else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
694  || code == TYPE_CODE_UNION)
695  amd64_classify_aggregate (type, theclass);
696 }
697 
698 static enum return_value_convention
699 amd64_return_value (struct gdbarch *gdbarch, struct value *function,
700  struct type *type, struct regcache *regcache,
701  gdb_byte *readbuf, const gdb_byte *writebuf)
702 {
703  enum amd64_reg_class theclass[2];
704  int len = TYPE_LENGTH (type);
705  static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
706  static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
707  int integer_reg = 0;
708  int sse_reg = 0;
709  int i;
710 
711  gdb_assert (!(readbuf && writebuf));
712 
713  /* 1. Classify the return type with the classification algorithm. */
714  amd64_classify (type, theclass);
715 
716  /* 2. If the type has class MEMORY, then the caller provides space
717  for the return value and passes the address of this storage in
718  %rdi as if it were the first argument to the function. In effect,
719  this address becomes a hidden first argument.
720 
721  On return %rax will contain the address that has been passed in
722  by the caller in %rdi. */
723  if (theclass[0] == AMD64_MEMORY)
724  {
725  /* As indicated by the comment above, the ABI guarantees that we
726  can always find the return value just after the function has
727  returned. */
728 
729  if (readbuf)
730  {
731  ULONGEST addr;
732 
733  regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
734  read_memory (addr, readbuf, TYPE_LENGTH (type));
735  }
736 
738  }
739 
740  /* 8. If the class is COMPLEX_X87, the real part of the value is
741  returned in %st0 and the imaginary part in %st1. */
742  if (theclass[0] == AMD64_COMPLEX_X87)
743  {
744  if (readbuf)
745  {
746  regcache_raw_read (regcache, AMD64_ST0_REGNUM, readbuf);
747  regcache_raw_read (regcache, AMD64_ST1_REGNUM, readbuf + 16);
748  }
749 
750  if (writebuf)
751  {
752  i387_return_value (gdbarch, regcache);
753  regcache_raw_write (regcache, AMD64_ST0_REGNUM, writebuf);
754  regcache_raw_write (regcache, AMD64_ST1_REGNUM, writebuf + 16);
755 
756  /* Fix up the tag word such that both %st(0) and %st(1) are
757  marked as valid. */
759  }
760 
762  }
763 
764  gdb_assert (theclass[1] != AMD64_MEMORY);
765  gdb_assert (len <= 16);
766 
767  for (i = 0; len > 0; i++, len -= 8)
768  {
769  int regnum = -1;
770  int offset = 0;
771 
772  switch (theclass[i])
773  {
774  case AMD64_INTEGER:
775  /* 3. If the class is INTEGER, the next available register
776  of the sequence %rax, %rdx is used. */
777  regnum = integer_regnum[integer_reg++];
778  break;
779 
780  case AMD64_SSE:
781  /* 4. If the class is SSE, the next available SSE register
782  of the sequence %xmm0, %xmm1 is used. */
783  regnum = sse_regnum[sse_reg++];
784  break;
785 
786  case AMD64_SSEUP:
787  /* 5. If the class is SSEUP, the eightbyte is passed in the
788  upper half of the last used SSE register. */
789  gdb_assert (sse_reg > 0);
790  regnum = sse_regnum[sse_reg - 1];
791  offset = 8;
792  break;
793 
794  case AMD64_X87:
795  /* 6. If the class is X87, the value is returned on the X87
796  stack in %st0 as 80-bit x87 number. */
797  regnum = AMD64_ST0_REGNUM;
798  if (writebuf)
799  i387_return_value (gdbarch, regcache);
800  break;
801 
802  case AMD64_X87UP:
803  /* 7. If the class is X87UP, the value is returned together
804  with the previous X87 value in %st0. */
805  gdb_assert (i > 0 && theclass[0] == AMD64_X87);
806  regnum = AMD64_ST0_REGNUM;
807  offset = 8;
808  len = 2;
809  break;
810 
811  case AMD64_NO_CLASS:
812  continue;
813 
814  default:
815  gdb_assert (!"Unexpected register class.");
816  }
817 
818  gdb_assert (regnum != -1);
819 
820  if (readbuf)
821  regcache_raw_read_part (regcache, regnum, offset, min (len, 8),
822  readbuf + i * 8);
823  if (writebuf)
824  regcache_raw_write_part (regcache, regnum, offset, min (len, 8),
825  writebuf + i * 8);
826  }
827 
829 }
830 
831 
832 static CORE_ADDR
834  struct value **args, CORE_ADDR sp, int struct_return)
835 {
836  static int integer_regnum[] =
837  {
838  AMD64_RDI_REGNUM, /* %rdi */
839  AMD64_RSI_REGNUM, /* %rsi */
840  AMD64_RDX_REGNUM, /* %rdx */
841  AMD64_RCX_REGNUM, /* %rcx */
842  AMD64_R8_REGNUM, /* %r8 */
843  AMD64_R9_REGNUM /* %r9 */
844  };
845  static int sse_regnum[] =
846  {
847  /* %xmm0 ... %xmm7 */
849  AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
850  AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
851  AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
852  };
853  struct value **stack_args = alloca (nargs * sizeof (struct value *));
854  int num_stack_args = 0;
855  int num_elements = 0;
856  int element = 0;
857  int integer_reg = 0;
858  int sse_reg = 0;
859  int i;
860 
861  /* Reserve a register for the "hidden" argument. */
862  if (struct_return)
863  integer_reg++;
864 
865  for (i = 0; i < nargs; i++)
866  {
867  struct type *type = value_type (args[i]);
868  int len = TYPE_LENGTH (type);
869  enum amd64_reg_class theclass[2];
870  int needed_integer_regs = 0;
871  int needed_sse_regs = 0;
872  int j;
873 
874  /* Classify argument. */
875  amd64_classify (type, theclass);
876 
877  /* Calculate the number of integer and SSE registers needed for
878  this argument. */
879  for (j = 0; j < 2; j++)
880  {
881  if (theclass[j] == AMD64_INTEGER)
882  needed_integer_regs++;
883  else if (theclass[j] == AMD64_SSE)
884  needed_sse_regs++;
885  }
886 
887  /* Check whether enough registers are available, and if the
888  argument should be passed in registers at all. */
889  if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum)
890  || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
891  || (needed_integer_regs == 0 && needed_sse_regs == 0))
892  {
893  /* The argument will be passed on the stack. */
894  num_elements += ((len + 7) / 8);
895  stack_args[num_stack_args++] = args[i];
896  }
897  else
898  {
899  /* The argument will be passed in registers. */
900  const gdb_byte *valbuf = value_contents (args[i]);
901  gdb_byte buf[8];
902 
903  gdb_assert (len <= 16);
904 
905  for (j = 0; len > 0; j++, len -= 8)
906  {
907  int regnum = -1;
908  int offset = 0;
909 
910  switch (theclass[j])
911  {
912  case AMD64_INTEGER:
913  regnum = integer_regnum[integer_reg++];
914  break;
915 
916  case AMD64_SSE:
917  regnum = sse_regnum[sse_reg++];
918  break;
919 
920  case AMD64_SSEUP:
921  gdb_assert (sse_reg > 0);
922  regnum = sse_regnum[sse_reg - 1];
923  offset = 8;
924  break;
925 
926  default:
927  gdb_assert (!"Unexpected register class.");
928  }
929 
930  gdb_assert (regnum != -1);
931  memset (buf, 0, sizeof buf);
932  memcpy (buf, valbuf + j * 8, min (len, 8));
933  regcache_raw_write_part (regcache, regnum, offset, 8, buf);
934  }
935  }
936  }
937 
938  /* Allocate space for the arguments on the stack. */
939  sp -= num_elements * 8;
940 
941  /* The psABI says that "The end of the input argument area shall be
942  aligned on a 16 byte boundary." */
943  sp &= ~0xf;
944 
945  /* Write out the arguments to the stack. */
946  for (i = 0; i < num_stack_args; i++)
947  {
948  struct type *type = value_type (stack_args[i]);
949  const gdb_byte *valbuf = value_contents (stack_args[i]);
950  int len = TYPE_LENGTH (type);
951 
952  write_memory (sp + element * 8, valbuf, len);
953  element += ((len + 7) / 8);
954  }
955 
956  /* The psABI says that "For calls that may call functions that use
957  varargs or stdargs (prototype-less calls or calls to functions
958  containing ellipsis (...) in the declaration) %al is used as
959  hidden argument to specify the number of SSE registers used. */
960  regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
961  return sp;
962 }
963 
964 static CORE_ADDR
965 amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
966  struct regcache *regcache, CORE_ADDR bp_addr,
967  int nargs, struct value **args, CORE_ADDR sp,
968  int struct_return, CORE_ADDR struct_addr)
969 {
970  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
971  gdb_byte buf[8];
972 
973  /* Pass arguments. */
974  sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
975 
976  /* Pass "hidden" argument". */
977  if (struct_return)
978  {
979  store_unsigned_integer (buf, 8, byte_order, struct_addr);
980  regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf);
981  }
982 
983  /* Store return address. */
984  sp -= 8;
985  store_unsigned_integer (buf, 8, byte_order, bp_addr);
986  write_memory (sp, buf, 8);
987 
988  /* Finally, update the stack pointer... */
989  store_unsigned_integer (buf, 8, byte_order, sp);
990  regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf);
991 
992  /* ...and fake a frame pointer. */
993  regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf);
994 
995  return sp + 16;
996 }
997 
998 /* Displaced instruction handling. */
999 
1000 /* A partially decoded instruction.
1001  This contains enough details for displaced stepping purposes. */
1002 
1004 {
1005  /* The number of opcode bytes. */
1007  /* The offset of the rex prefix or -1 if not present. */
1009  /* The offset to the first opcode byte. */
1011  /* The offset to the modrm byte or -1 if not present. */
1013 
1014  /* The raw instruction. */
1016 };
1017 
1019 {
1020  /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
1024 
1025  /* Details of the instruction. */
1027 
1028  /* Amount of space allocated to insn_buf. */
1029  int max_len;
1030 
1031  /* The possibly modified insn.
1032  This is a variable-length field. */
1034 };
1035 
1036 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1037  ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1038  at which point delete these in favor of libopcodes' versions). */
1039 
1040 static const unsigned char onebyte_has_modrm[256] = {
1041  /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1042  /* ------------------------------- */
1043  /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1044  /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1045  /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1046  /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1047  /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1048  /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1049  /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1050  /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1051  /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1052  /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1053  /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1054  /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1055  /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1056  /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1057  /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1058  /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1059  /* ------------------------------- */
1060  /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1061 };
1062 
1063 static const unsigned char twobyte_has_modrm[256] = {
1064  /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1065  /* ------------------------------- */
1066  /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1067  /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1068  /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1069  /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1070  /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1071  /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1072  /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1073  /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1074  /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1075  /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1076  /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1077  /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1078  /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1079  /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1080  /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1081  /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1082  /* ------------------------------- */
1083  /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1084 };
1085 
1086 static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp);
1087 
1088 static int
1090 {
1091  return REX_PREFIX_P (pfx);
1092 }
1093 
1094 /* Skip the legacy instruction prefixes in INSN.
1095  We assume INSN is properly sentineled so we don't have to worry
1096  about falling off the end of the buffer. */
1097 
1098 static gdb_byte *
1100 {
1101  while (1)
1102  {
1103  switch (*insn)
1104  {
1105  case DATA_PREFIX_OPCODE:
1106  case ADDR_PREFIX_OPCODE:
1107  case CS_PREFIX_OPCODE:
1108  case DS_PREFIX_OPCODE:
1109  case ES_PREFIX_OPCODE:
1110  case FS_PREFIX_OPCODE:
1111  case GS_PREFIX_OPCODE:
1112  case SS_PREFIX_OPCODE:
1113  case LOCK_PREFIX_OPCODE:
1114  case REPE_PREFIX_OPCODE:
1115  case REPNE_PREFIX_OPCODE:
1116  ++insn;
1117  continue;
1118  default:
1119  break;
1120  }
1121  break;
1122  }
1123 
1124  return insn;
1125 }
1126 
1127 /* Return an integer register (other than RSP) that is unused as an input
1128  operand in INSN.
1129  In order to not require adding a rex prefix if the insn doesn't already
1130  have one, the result is restricted to RAX ... RDI, sans RSP.
1131  The register numbering of the result follows architecture ordering,
1132  e.g. RDI = 7. */
1133 
1134 static int
1136 {
1137  /* 1 bit for each reg */
1138  int used_regs_mask = 0;
1139 
1140  /* There can be at most 3 int regs used as inputs in an insn, and we have
1141  7 to choose from (RAX ... RDI, sans RSP).
1142  This allows us to take a conservative approach and keep things simple.
1143  E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1144  that implicitly specify RAX. */
1145 
1146  /* Avoid RAX. */
1147  used_regs_mask |= 1 << EAX_REG_NUM;
1148  /* Similarily avoid RDX, implicit operand in divides. */
1149  used_regs_mask |= 1 << EDX_REG_NUM;
1150  /* Avoid RSP. */
1151  used_regs_mask |= 1 << ESP_REG_NUM;
1152 
1153  /* If the opcode is one byte long and there's no ModRM byte,
1154  assume the opcode specifies a register. */
1155  if (details->opcode_len == 1 && details->modrm_offset == -1)
1156  used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7);
1157 
1158  /* Mark used regs in the modrm/sib bytes. */
1159  if (details->modrm_offset != -1)
1160  {
1161  int modrm = details->raw_insn[details->modrm_offset];
1162  int mod = MODRM_MOD_FIELD (modrm);
1163  int reg = MODRM_REG_FIELD (modrm);
1164  int rm = MODRM_RM_FIELD (modrm);
1165  int have_sib = mod != 3 && rm == 4;
1166 
1167  /* Assume the reg field of the modrm byte specifies a register. */
1168  used_regs_mask |= 1 << reg;
1169 
1170  if (have_sib)
1171  {
1172  int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]);
1173  int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]);
1174  used_regs_mask |= 1 << base;
1175  used_regs_mask |= 1 << idx;
1176  }
1177  else
1178  {
1179  used_regs_mask |= 1 << rm;
1180  }
1181  }
1182 
1183  gdb_assert (used_regs_mask < 256);
1184  gdb_assert (used_regs_mask != 255);
1185 
1186  /* Finally, find a free reg. */
1187  {
1188  int i;
1189 
1190  for (i = 0; i < 8; ++i)
1191  {
1192  if (! (used_regs_mask & (1 << i)))
1193  return i;
1194  }
1195 
1196  /* We shouldn't get here. */
1197  internal_error (__FILE__, __LINE__, _("unable to find free reg"));
1198  }
1199 }
1200 
1201 /* Extract the details of INSN that we need. */
1202 
1203 static void
1205 {
1206  gdb_byte *start = insn;
1207  int need_modrm;
1208 
1209  details->raw_insn = insn;
1210 
1211  details->opcode_len = -1;
1212  details->rex_offset = -1;
1213  details->opcode_offset = -1;
1214  details->modrm_offset = -1;
1215 
1216  /* Skip legacy instruction prefixes. */
1217  insn = amd64_skip_prefixes (insn);
1218 
1219  /* Skip REX instruction prefix. */
1220  if (rex_prefix_p (*insn))
1221  {
1222  details->rex_offset = insn - start;
1223  ++insn;
1224  }
1225 
1226  details->opcode_offset = insn - start;
1227 
1228  if (*insn == TWO_BYTE_OPCODE_ESCAPE)
1229  {
1230  /* Two or three-byte opcode. */
1231  ++insn;
1232  need_modrm = twobyte_has_modrm[*insn];
1233 
1234  /* Check for three-byte opcode. */
1235  switch (*insn)
1236  {
1237  case 0x24:
1238  case 0x25:
1239  case 0x38:
1240  case 0x3a:
1241  case 0x7a:
1242  case 0x7b:
1243  ++insn;
1244  details->opcode_len = 3;
1245  break;
1246  default:
1247  details->opcode_len = 2;
1248  break;
1249  }
1250  }
1251  else
1252  {
1253  /* One-byte opcode. */
1254  need_modrm = onebyte_has_modrm[*insn];
1255  details->opcode_len = 1;
1256  }
1257 
1258  if (need_modrm)
1259  {
1260  ++insn;
1261  details->modrm_offset = insn - start;
1262  }
1263 }
1264 
1265 /* Update %rip-relative addressing in INSN.
1266 
1267  %rip-relative addressing only uses a 32-bit displacement.
1268  32 bits is not enough to be guaranteed to cover the distance between where
1269  the real instruction is and where its copy is.
1270  Convert the insn to use base+disp addressing.
1271  We set base = pc + insn_length so we can leave disp unchanged. */
1272 
1273 static void
1274 fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc,
1275  CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1276 {
1277  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1278  const struct amd64_insn *insn_details = &dsc->insn_details;
1279  int modrm_offset = insn_details->modrm_offset;
1280  gdb_byte *insn = insn_details->raw_insn + modrm_offset;
1281  CORE_ADDR rip_base;
1282  int32_t disp;
1283  int insn_length;
1284  int arch_tmp_regno, tmp_regno;
1285  ULONGEST orig_value;
1286 
1287  /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1288  ++insn;
1289 
1290  /* Compute the rip-relative address. */
1291  disp = extract_signed_integer (insn, sizeof (int32_t), byte_order);
1292  insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf,
1293  dsc->max_len, from);
1294  rip_base = from + insn_length;
1295 
1296  /* We need a register to hold the address.
1297  Pick one not used in the insn.
1298  NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1299  arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details);
1300  tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno);
1301 
1302  /* REX.B should be unset as we were using rip-relative addressing,
1303  but ensure it's unset anyway, tmp_regno is not r8-r15. */
1304  if (insn_details->rex_offset != -1)
1305  dsc->insn_buf[insn_details->rex_offset] &= ~REX_B;
1306 
1307  regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value);
1308  dsc->tmp_regno = tmp_regno;
1309  dsc->tmp_save = orig_value;
1310  dsc->tmp_used = 1;
1311 
1312  /* Convert the ModRM field to be base+disp. */
1313  dsc->insn_buf[modrm_offset] &= ~0xc7;
1314  dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno;
1315 
1316  regcache_cooked_write_unsigned (regs, tmp_regno, rip_base);
1317 
1318  if (debug_displaced)
1319  fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n"
1320  "displaced: using temp reg %d, old value %s, new value %s\n",
1321  dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save),
1322  paddress (gdbarch, rip_base));
1323 }
1324 
1325 static void
1326 fixup_displaced_copy (struct gdbarch *gdbarch,
1327  struct displaced_step_closure *dsc,
1328  CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1329 {
1330  const struct amd64_insn *details = &dsc->insn_details;
1331 
1332  if (details->modrm_offset != -1)
1333  {
1334  gdb_byte modrm = details->raw_insn[details->modrm_offset];
1335 
1336  if ((modrm & 0xc7) == 0x05)
1337  {
1338  /* The insn uses rip-relative addressing.
1339  Deal with it. */
1340  fixup_riprel (gdbarch, dsc, from, to, regs);
1341  }
1342  }
1343 }
1344 
1345 struct displaced_step_closure *
1346 amd64_displaced_step_copy_insn (struct gdbarch *gdbarch,
1348  struct regcache *regs)
1349 {
1350  int len = gdbarch_max_insn_length (gdbarch);
1351  /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1352  continually watch for running off the end of the buffer. */
1353  int fixup_sentinel_space = len;
1354  struct displaced_step_closure *dsc =
1355  xmalloc (sizeof (*dsc) + len + fixup_sentinel_space);
1356  gdb_byte *buf = &dsc->insn_buf[0];
1357  struct amd64_insn *details = &dsc->insn_details;
1358 
1359  dsc->tmp_used = 0;
1360  dsc->max_len = len + fixup_sentinel_space;
1361 
1362  read_memory (from, buf, len);
1363 
1364  /* Set up the sentinel space so we don't have to worry about running
1365  off the end of the buffer. An excessive number of leading prefixes
1366  could otherwise cause this. */
1367  memset (buf + len, 0, fixup_sentinel_space);
1368 
1369  amd64_get_insn_details (buf, details);
1370 
1371  /* GDB may get control back after the insn after the syscall.
1372  Presumably this is a kernel bug.
1373  If this is a syscall, make sure there's a nop afterwards. */
1374  {
1375  int syscall_length;
1376 
1377  if (amd64_syscall_p (details, &syscall_length))
1378  buf[details->opcode_offset + syscall_length] = NOP_OPCODE;
1379  }
1380 
1381  /* Modify the insn to cope with the address where it will be executed from.
1382  In particular, handle any rip-relative addressing. */
1383  fixup_displaced_copy (gdbarch, dsc, from, to, regs);
1384 
1385  write_memory (to, buf, len);
1386 
1387  if (debug_displaced)
1388  {
1389  fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
1390  paddress (gdbarch, from), paddress (gdbarch, to));
1392  }
1393 
1394  return dsc;
1395 }
1396 
1397 static int
1398 amd64_absolute_jmp_p (const struct amd64_insn *details)
1399 {
1400  const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1401 
1402  if (insn[0] == 0xff)
1403  {
1404  /* jump near, absolute indirect (/4) */
1405  if ((insn[1] & 0x38) == 0x20)
1406  return 1;
1407 
1408  /* jump far, absolute indirect (/5) */
1409  if ((insn[1] & 0x38) == 0x28)
1410  return 1;
1411  }
1412 
1413  return 0;
1414 }
1415 
1416 /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1417 
1418 static int
1419 amd64_jmp_p (const struct amd64_insn *details)
1420 {
1421  const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1422 
1423  /* jump short, relative. */
1424  if (insn[0] == 0xeb)
1425  return 1;
1426 
1427  /* jump near, relative. */
1428  if (insn[0] == 0xe9)
1429  return 1;
1430 
1431  return amd64_absolute_jmp_p (details);
1432 }
1433 
1434 static int
1435 amd64_absolute_call_p (const struct amd64_insn *details)
1436 {
1437  const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1438 
1439  if (insn[0] == 0xff)
1440  {
1441  /* Call near, absolute indirect (/2) */
1442  if ((insn[1] & 0x38) == 0x10)
1443  return 1;
1444 
1445  /* Call far, absolute indirect (/3) */
1446  if ((insn[1] & 0x38) == 0x18)
1447  return 1;
1448  }
1449 
1450  return 0;
1451 }
1452 
1453 static int
1454 amd64_ret_p (const struct amd64_insn *details)
1455 {
1456  /* NOTE: gcc can emit "repz ; ret". */
1457  const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1458 
1459  switch (insn[0])
1460  {
1461  case 0xc2: /* ret near, pop N bytes */
1462  case 0xc3: /* ret near */
1463  case 0xca: /* ret far, pop N bytes */
1464  case 0xcb: /* ret far */
1465  case 0xcf: /* iret */
1466  return 1;
1467 
1468  default:
1469  return 0;
1470  }
1471 }
1472 
1473 static int
1474 amd64_call_p (const struct amd64_insn *details)
1475 {
1476  const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1477 
1478  if (amd64_absolute_call_p (details))
1479  return 1;
1480 
1481  /* call near, relative */
1482  if (insn[0] == 0xe8)
1483  return 1;
1484 
1485  return 0;
1486 }
1487 
1488 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1489  length in bytes. Otherwise, return zero. */
1490 
1491 static int
1492 amd64_syscall_p (const struct amd64_insn *details, int *lengthp)
1493 {
1494  const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1495 
1496  if (insn[0] == 0x0f && insn[1] == 0x05)
1497  {
1498  *lengthp = 2;
1499  return 1;
1500  }
1501 
1502  return 0;
1503 }
1504 
1505 /* Classify the instruction at ADDR using PRED.
1506  Throw an error if the memory can't be read. */
1507 
1508 static int
1509 amd64_classify_insn_at (struct gdbarch *gdbarch, CORE_ADDR addr,
1510  int (*pred) (const struct amd64_insn *))
1511 {
1512  struct amd64_insn details;
1513  gdb_byte *buf;
1514  int len, classification;
1515 
1516  len = gdbarch_max_insn_length (gdbarch);
1517  buf = alloca (len);
1518 
1519  read_code (addr, buf, len);
1520  amd64_get_insn_details (buf, &details);
1521 
1522  classification = pred (&details);
1523 
1524  return classification;
1525 }
1526 
1527 /* The gdbarch insn_is_call method. */
1528 
1529 static int
1530 amd64_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
1531 {
1532  return amd64_classify_insn_at (gdbarch, addr, amd64_call_p);
1533 }
1534 
1535 /* The gdbarch insn_is_ret method. */
1536 
1537 static int
1538 amd64_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
1539 {
1540  return amd64_classify_insn_at (gdbarch, addr, amd64_ret_p);
1541 }
1542 
1543 /* The gdbarch insn_is_jump method. */
1544 
1545 static int
1546 amd64_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
1547 {
1548  return amd64_classify_insn_at (gdbarch, addr, amd64_jmp_p);
1549 }
1550 
1551 /* Fix up the state of registers and memory after having single-stepped
1552  a displaced instruction. */
1553 
1554 void
1555 amd64_displaced_step_fixup (struct gdbarch *gdbarch,
1556  struct displaced_step_closure *dsc,
1558  struct regcache *regs)
1559 {
1560  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1561  /* The offset we applied to the instruction's address. */
1562  ULONGEST insn_offset = to - from;
1563  gdb_byte *insn = dsc->insn_buf;
1564  const struct amd64_insn *insn_details = &dsc->insn_details;
1565 
1566  if (debug_displaced)
1568  "displaced: fixup (%s, %s), "
1569  "insn = 0x%02x 0x%02x ...\n",
1570  paddress (gdbarch, from), paddress (gdbarch, to),
1571  insn[0], insn[1]);
1572 
1573  /* If we used a tmp reg, restore it. */
1574 
1575  if (dsc->tmp_used)
1576  {
1577  if (debug_displaced)
1578  fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n",
1579  dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save));
1581  }
1582 
1583  /* The list of issues to contend with here is taken from
1584  resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1585  Yay for Free Software! */
1586 
1587  /* Relocate the %rip back to the program's instruction stream,
1588  if necessary. */
1589 
1590  /* Except in the case of absolute or indirect jump or call
1591  instructions, or a return instruction, the new rip is relative to
1592  the displaced instruction; make it relative to the original insn.
1593  Well, signal handler returns don't need relocation either, but we use the
1594  value of %rip to recognize those; see below. */
1595  if (! amd64_absolute_jmp_p (insn_details)
1596  && ! amd64_absolute_call_p (insn_details)
1597  && ! amd64_ret_p (insn_details))
1598  {
1599  ULONGEST orig_rip;
1600  int insn_len;
1601 
1603 
1604  /* A signal trampoline system call changes the %rip, resuming
1605  execution of the main program after the signal handler has
1606  returned. That makes them like 'return' instructions; we
1607  shouldn't relocate %rip.
1608 
1609  But most system calls don't, and we do need to relocate %rip.
1610 
1611  Our heuristic for distinguishing these cases: if stepping
1612  over the system call instruction left control directly after
1613  the instruction, the we relocate --- control almost certainly
1614  doesn't belong in the displaced copy. Otherwise, we assume
1615  the instruction has put control where it belongs, and leave
1616  it unrelocated. Goodness help us if there are PC-relative
1617  system calls. */
1618  if (amd64_syscall_p (insn_details, &insn_len)
1619  && orig_rip != to + insn_len
1620  /* GDB can get control back after the insn after the syscall.
1621  Presumably this is a kernel bug.
1622  Fixup ensures its a nop, we add one to the length for it. */
1623  && orig_rip != to + insn_len + 1)
1624  {
1625  if (debug_displaced)
1627  "displaced: syscall changed %%rip; "
1628  "not relocating\n");
1629  }
1630  else
1631  {
1632  ULONGEST rip = orig_rip - insn_offset;
1633 
1634  /* If we just stepped over a breakpoint insn, we don't backup
1635  the pc on purpose; this is to match behaviour without
1636  stepping. */
1637 
1639 
1640  if (debug_displaced)
1642  "displaced: "
1643  "relocated %%rip from %s to %s\n",
1644  paddress (gdbarch, orig_rip),
1645  paddress (gdbarch, rip));
1646  }
1647  }
1648 
1649  /* If the instruction was PUSHFL, then the TF bit will be set in the
1650  pushed value, and should be cleared. We'll leave this for later,
1651  since GDB already messes up the TF flag when stepping over a
1652  pushfl. */
1653 
1654  /* If the instruction was a call, the return address now atop the
1655  stack is the address following the copied instruction. We need
1656  to make it the address following the original instruction. */
1657  if (amd64_call_p (insn_details))
1658  {
1659  ULONGEST rsp;
1660  ULONGEST retaddr;
1661  const ULONGEST retaddr_len = 8;
1662 
1664  retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order);
1665  retaddr = (retaddr - insn_offset) & 0xffffffffffffffffULL;
1666  write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr);
1667 
1668  if (debug_displaced)
1670  "displaced: relocated return addr at %s "
1671  "to %s\n",
1672  paddress (gdbarch, rsp),
1673  paddress (gdbarch, retaddr));
1674  }
1675 }
1676 
1677 /* If the instruction INSN uses RIP-relative addressing, return the
1678  offset into the raw INSN where the displacement to be adjusted is
1679  found. Returns 0 if the instruction doesn't use RIP-relative
1680  addressing. */
1681 
1682 static int
1684 {
1685  if (insn->modrm_offset != -1)
1686  {
1687  gdb_byte modrm = insn->raw_insn[insn->modrm_offset];
1688 
1689  if ((modrm & 0xc7) == 0x05)
1690  {
1691  /* The displacement is found right after the ModRM byte. */
1692  return insn->modrm_offset + 1;
1693  }
1694  }
1695 
1696  return 0;
1697 }
1698 
1699 static void
1701 {
1702  target_write_memory (*to, buf, len);
1703  *to += len;
1704 }
1705 
1706 static void
1707 amd64_relocate_instruction (struct gdbarch *gdbarch,
1708  CORE_ADDR *to, CORE_ADDR oldloc)
1709 {
1710  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1711  int len = gdbarch_max_insn_length (gdbarch);
1712  /* Extra space for sentinels. */
1713  int fixup_sentinel_space = len;
1714  gdb_byte *buf = xmalloc (len + fixup_sentinel_space);
1715  struct amd64_insn insn_details;
1716  int offset = 0;
1717  LONGEST rel32, newrel;
1718  gdb_byte *insn;
1719  int insn_length;
1720 
1721  read_memory (oldloc, buf, len);
1722 
1723  /* Set up the sentinel space so we don't have to worry about running
1724  off the end of the buffer. An excessive number of leading prefixes
1725  could otherwise cause this. */
1726  memset (buf + len, 0, fixup_sentinel_space);
1727 
1728  insn = buf;
1729  amd64_get_insn_details (insn, &insn_details);
1730 
1731  insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc);
1732 
1733  /* Skip legacy instruction prefixes. */
1734  insn = amd64_skip_prefixes (insn);
1735 
1736  /* Adjust calls with 32-bit relative addresses as push/jump, with
1737  the address pushed being the location where the original call in
1738  the user program would return to. */
1739  if (insn[0] == 0xe8)
1740  {
1741  gdb_byte push_buf[16];
1742  unsigned int ret_addr;
1743 
1744  /* Where "ret" in the original code will return to. */
1745  ret_addr = oldloc + insn_length;
1746  push_buf[0] = 0x68; /* pushq $... */
1747  store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
1748  /* Push the push. */
1749  append_insns (to, 5, push_buf);
1750 
1751  /* Convert the relative call to a relative jump. */
1752  insn[0] = 0xe9;
1753 
1754  /* Adjust the destination offset. */
1755  rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1756  newrel = (oldloc - *to) + rel32;
1757  store_signed_integer (insn + 1, 4, byte_order, newrel);
1758 
1759  if (debug_displaced)
1761  "Adjusted insn rel32=%s at %s to"
1762  " rel32=%s at %s\n",
1763  hex_string (rel32), paddress (gdbarch, oldloc),
1764  hex_string (newrel), paddress (gdbarch, *to));
1765 
1766  /* Write the adjusted jump into its displaced location. */
1767  append_insns (to, 5, insn);
1768  return;
1769  }
1770 
1771  offset = rip_relative_offset (&insn_details);
1772  if (!offset)
1773  {
1774  /* Adjust jumps with 32-bit relative addresses. Calls are
1775  already handled above. */
1776  if (insn[0] == 0xe9)
1777  offset = 1;
1778  /* Adjust conditional jumps. */
1779  else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1780  offset = 2;
1781  }
1782 
1783  if (offset)
1784  {
1785  rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1786  newrel = (oldloc - *to) + rel32;
1787  store_signed_integer (insn + offset, 4, byte_order, newrel);
1788  if (debug_displaced)
1790  "Adjusted insn rel32=%s at %s to"
1791  " rel32=%s at %s\n",
1792  hex_string (rel32), paddress (gdbarch, oldloc),
1793  hex_string (newrel), paddress (gdbarch, *to));
1794  }
1795 
1796  /* Write the adjusted instruction into its displaced location. */
1797  append_insns (to, insn_length, buf);
1798 }
1799 
1800 
1801 /* The maximum number of saved registers. This should include %rip. */
1802 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1803 
1805 {
1806  /* Base address. */
1808  int base_p;
1811 
1812  /* Saved registers. */
1816 
1817  /* Do we have a frame? */
1819 };
1820 
1821 /* Initialize a frame cache. */
1822 
1823 static void
1825 {
1826  int i;
1827 
1828  /* Base address. */
1829  cache->base = 0;
1830  cache->base_p = 0;
1831  cache->sp_offset = -8;
1832  cache->pc = 0;
1833 
1834  /* Saved registers. We initialize these to -1 since zero is a valid
1835  offset (that's where %rbp is supposed to be stored).
1836  The values start out as being offsets, and are later converted to
1837  addresses (at which point -1 is interpreted as an address, still meaning
1838  "invalid"). */
1839  for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
1840  cache->saved_regs[i] = -1;
1841  cache->saved_sp = 0;
1842  cache->saved_sp_reg = -1;
1843 
1844  /* Frameless until proven otherwise. */
1845  cache->frameless_p = 1;
1846 }
1847 
1848 /* Allocate and initialize a frame cache. */
1849 
1850 static struct amd64_frame_cache *
1852 {
1853  struct amd64_frame_cache *cache;
1854 
1855  cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
1856  amd64_init_frame_cache (cache);
1857  return cache;
1858 }
1859 
1860 /* GCC 4.4 and later, can put code in the prologue to realign the
1861  stack pointer. Check whether PC points to such code, and update
1862  CACHE accordingly. Return the first instruction after the code
1863  sequence or CURRENT_PC, whichever is smaller. If we don't
1864  recognize the code, return PC. */
1865 
1866 static CORE_ADDR
1868  struct amd64_frame_cache *cache)
1869 {
1870  /* There are 2 code sequences to re-align stack before the frame
1871  gets set up:
1872 
1873  1. Use a caller-saved saved register:
1874 
1875  leaq 8(%rsp), %reg
1876  andq $-XXX, %rsp
1877  pushq -8(%reg)
1878 
1879  2. Use a callee-saved saved register:
1880 
1881  pushq %reg
1882  leaq 16(%rsp), %reg
1883  andq $-XXX, %rsp
1884  pushq -8(%reg)
1885 
1886  "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1887 
1888  0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1889  0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1890  */
1891 
1892  gdb_byte buf[18];
1893  int reg, r;
1894  int offset, offset_and;
1895 
1896  if (target_read_code (pc, buf, sizeof buf))
1897  return pc;
1898 
1899  /* Check caller-saved saved register. The first instruction has
1900  to be "leaq 8(%rsp), %reg". */
1901  if ((buf[0] & 0xfb) == 0x48
1902  && buf[1] == 0x8d
1903  && buf[3] == 0x24
1904  && buf[4] == 0x8)
1905  {
1906  /* MOD must be binary 10 and R/M must be binary 100. */
1907  if ((buf[2] & 0xc7) != 0x44)
1908  return pc;
1909 
1910  /* REG has register number. */
1911  reg = (buf[2] >> 3) & 7;
1912 
1913  /* Check the REX.R bit. */
1914  if (buf[0] == 0x4c)
1915  reg += 8;
1916 
1917  offset = 5;
1918  }
1919  else
1920  {
1921  /* Check callee-saved saved register. The first instruction
1922  has to be "pushq %reg". */
1923  reg = 0;
1924  if ((buf[0] & 0xf8) == 0x50)
1925  offset = 0;
1926  else if ((buf[0] & 0xf6) == 0x40
1927  && (buf[1] & 0xf8) == 0x50)
1928  {
1929  /* Check the REX.B bit. */
1930  if ((buf[0] & 1) != 0)
1931  reg = 8;
1932 
1933  offset = 1;
1934  }
1935  else
1936  return pc;
1937 
1938  /* Get register. */
1939  reg += buf[offset] & 0x7;
1940 
1941  offset++;
1942 
1943  /* The next instruction has to be "leaq 16(%rsp), %reg". */
1944  if ((buf[offset] & 0xfb) != 0x48
1945  || buf[offset + 1] != 0x8d
1946  || buf[offset + 3] != 0x24
1947  || buf[offset + 4] != 0x10)
1948  return pc;
1949 
1950  /* MOD must be binary 10 and R/M must be binary 100. */
1951  if ((buf[offset + 2] & 0xc7) != 0x44)
1952  return pc;
1953 
1954  /* REG has register number. */
1955  r = (buf[offset + 2] >> 3) & 7;
1956 
1957  /* Check the REX.R bit. */
1958  if (buf[offset] == 0x4c)
1959  r += 8;
1960 
1961  /* Registers in pushq and leaq have to be the same. */
1962  if (reg != r)
1963  return pc;
1964 
1965  offset += 5;
1966  }
1967 
1968  /* Rigister can't be %rsp nor %rbp. */
1969  if (reg == 4 || reg == 5)
1970  return pc;
1971 
1972  /* The next instruction has to be "andq $-XXX, %rsp". */
1973  if (buf[offset] != 0x48
1974  || buf[offset + 2] != 0xe4
1975  || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
1976  return pc;
1977 
1978  offset_and = offset;
1979  offset += buf[offset + 1] == 0x81 ? 7 : 4;
1980 
1981  /* The next instruction has to be "pushq -8(%reg)". */
1982  r = 0;
1983  if (buf[offset] == 0xff)
1984  offset++;
1985  else if ((buf[offset] & 0xf6) == 0x40
1986  && buf[offset + 1] == 0xff)
1987  {
1988  /* Check the REX.B bit. */
1989  if ((buf[offset] & 0x1) != 0)
1990  r = 8;
1991  offset += 2;
1992  }
1993  else
1994  return pc;
1995 
1996  /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
1997  01. */
1998  if (buf[offset + 1] != 0xf8
1999  || (buf[offset] & 0xf8) != 0x70)
2000  return pc;
2001 
2002  /* R/M has register. */
2003  r += buf[offset] & 7;
2004 
2005  /* Registers in leaq and pushq have to be the same. */
2006  if (reg != r)
2007  return pc;
2008 
2009  if (current_pc > pc + offset_and)
2010  cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
2011 
2012  return min (pc + offset + 2, current_pc);
2013 }
2014 
2015 /* Similar to amd64_analyze_stack_align for x32. */
2016 
2017 static CORE_ADDR
2019  struct amd64_frame_cache *cache)
2020 {
2021  /* There are 2 code sequences to re-align stack before the frame
2022  gets set up:
2023 
2024  1. Use a caller-saved saved register:
2025 
2026  leaq 8(%rsp), %reg
2027  andq $-XXX, %rsp
2028  pushq -8(%reg)
2029 
2030  or
2031 
2032  [addr32] leal 8(%rsp), %reg
2033  andl $-XXX, %esp
2034  [addr32] pushq -8(%reg)
2035 
2036  2. Use a callee-saved saved register:
2037 
2038  pushq %reg
2039  leaq 16(%rsp), %reg
2040  andq $-XXX, %rsp
2041  pushq -8(%reg)
2042 
2043  or
2044 
2045  pushq %reg
2046  [addr32] leal 16(%rsp), %reg
2047  andl $-XXX, %esp
2048  [addr32] pushq -8(%reg)
2049 
2050  "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2051 
2052  0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2053  0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2054 
2055  "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2056 
2057  0x83 0xe4 0xf0 andl $-16, %esp
2058  0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2059  */
2060 
2061  gdb_byte buf[19];
2062  int reg, r;
2063  int offset, offset_and;
2064 
2065  if (target_read_memory (pc, buf, sizeof buf))
2066  return pc;
2067 
2068  /* Skip optional addr32 prefix. */
2069  offset = buf[0] == 0x67 ? 1 : 0;
2070 
2071  /* Check caller-saved saved register. The first instruction has
2072  to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2073  if (((buf[offset] & 0xfb) == 0x48 || (buf[offset] & 0xfb) == 0x40)
2074  && buf[offset + 1] == 0x8d
2075  && buf[offset + 3] == 0x24
2076  && buf[offset + 4] == 0x8)
2077  {
2078  /* MOD must be binary 10 and R/M must be binary 100. */
2079  if ((buf[offset + 2] & 0xc7) != 0x44)
2080  return pc;
2081 
2082  /* REG has register number. */
2083  reg = (buf[offset + 2] >> 3) & 7;
2084 
2085  /* Check the REX.R bit. */
2086  if ((buf[offset] & 0x4) != 0)
2087  reg += 8;
2088 
2089  offset += 5;
2090  }
2091  else
2092  {
2093  /* Check callee-saved saved register. The first instruction
2094  has to be "pushq %reg". */
2095  reg = 0;
2096  if ((buf[offset] & 0xf6) == 0x40
2097  && (buf[offset + 1] & 0xf8) == 0x50)
2098  {
2099  /* Check the REX.B bit. */
2100  if ((buf[offset] & 1) != 0)
2101  reg = 8;
2102 
2103  offset += 1;
2104  }
2105  else if ((buf[offset] & 0xf8) != 0x50)
2106  return pc;
2107 
2108  /* Get register. */
2109  reg += buf[offset] & 0x7;
2110 
2111  offset++;
2112 
2113  /* Skip optional addr32 prefix. */
2114  if (buf[offset] == 0x67)
2115  offset++;
2116 
2117  /* The next instruction has to be "leaq 16(%rsp), %reg" or
2118  "leal 16(%rsp), %reg". */
2119  if (((buf[offset] & 0xfb) != 0x48 && (buf[offset] & 0xfb) != 0x40)
2120  || buf[offset + 1] != 0x8d
2121  || buf[offset + 3] != 0x24
2122  || buf[offset + 4] != 0x10)
2123  return pc;
2124 
2125  /* MOD must be binary 10 and R/M must be binary 100. */
2126  if ((buf[offset + 2] & 0xc7) != 0x44)
2127  return pc;
2128 
2129  /* REG has register number. */
2130  r = (buf[offset + 2] >> 3) & 7;
2131 
2132  /* Check the REX.R bit. */
2133  if ((buf[offset] & 0x4) != 0)
2134  r += 8;
2135 
2136  /* Registers in pushq and leaq have to be the same. */
2137  if (reg != r)
2138  return pc;
2139 
2140  offset += 5;
2141  }
2142 
2143  /* Rigister can't be %rsp nor %rbp. */
2144  if (reg == 4 || reg == 5)
2145  return pc;
2146 
2147  /* The next instruction may be "andq $-XXX, %rsp" or
2148  "andl $-XXX, %esp". */
2149  if (buf[offset] != 0x48)
2150  offset--;
2151 
2152  if (buf[offset + 2] != 0xe4
2153  || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
2154  return pc;
2155 
2156  offset_and = offset;
2157  offset += buf[offset + 1] == 0x81 ? 7 : 4;
2158 
2159  /* Skip optional addr32 prefix. */
2160  if (buf[offset] == 0x67)
2161  offset++;
2162 
2163  /* The next instruction has to be "pushq -8(%reg)". */
2164  r = 0;
2165  if (buf[offset] == 0xff)
2166  offset++;
2167  else if ((buf[offset] & 0xf6) == 0x40
2168  && buf[offset + 1] == 0xff)
2169  {
2170  /* Check the REX.B bit. */
2171  if ((buf[offset] & 0x1) != 0)
2172  r = 8;
2173  offset += 2;
2174  }
2175  else
2176  return pc;
2177 
2178  /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2179  01. */
2180  if (buf[offset + 1] != 0xf8
2181  || (buf[offset] & 0xf8) != 0x70)
2182  return pc;
2183 
2184  /* R/M has register. */
2185  r += buf[offset] & 7;
2186 
2187  /* Registers in leaq and pushq have to be the same. */
2188  if (reg != r)
2189  return pc;
2190 
2191  if (current_pc > pc + offset_and)
2192  cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
2193 
2194  return min (pc + offset + 2, current_pc);
2195 }
2196 
2197 /* Do a limited analysis of the prologue at PC and update CACHE
2198  accordingly. Bail out early if CURRENT_PC is reached. Return the
2199  address where the analysis stopped.
2200 
2201  We will handle only functions beginning with:
2202 
2203  pushq %rbp 0x55
2204  movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2205 
2206  or (for the X32 ABI):
2207 
2208  pushq %rbp 0x55
2209  movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2210 
2211  Any function that doesn't start with one of these sequences will be
2212  assumed to have no prologue and thus no valid frame pointer in
2213  %rbp. */
2214 
2215 static CORE_ADDR
2216 amd64_analyze_prologue (struct gdbarch *gdbarch,
2217  CORE_ADDR pc, CORE_ADDR current_pc,
2218  struct amd64_frame_cache *cache)
2219 {
2220  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2221  /* There are two variations of movq %rsp, %rbp. */
2222  static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 };
2223  static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec };
2224  /* Ditto for movl %esp, %ebp. */
2225  static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 };
2226  static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec };
2227 
2228  gdb_byte buf[3];
2229  gdb_byte op;
2230 
2231  if (current_pc <= pc)
2232  return current_pc;
2233 
2234  if (gdbarch_ptr_bit (gdbarch) == 32)
2235  pc = amd64_x32_analyze_stack_align (pc, current_pc, cache);
2236  else
2237  pc = amd64_analyze_stack_align (pc, current_pc, cache);
2238 
2239  op = read_code_unsigned_integer (pc, 1, byte_order);
2240 
2241  if (op == 0x55) /* pushq %rbp */
2242  {
2243  /* Take into account that we've executed the `pushq %rbp' that
2244  starts this instruction sequence. */
2245  cache->saved_regs[AMD64_RBP_REGNUM] = 0;
2246  cache->sp_offset += 8;
2247 
2248  /* If that's all, return now. */
2249  if (current_pc <= pc + 1)
2250  return current_pc;
2251 
2252  read_code (pc + 1, buf, 3);
2253 
2254  /* Check for `movq %rsp, %rbp'. */
2255  if (memcmp (buf, mov_rsp_rbp_1, 3) == 0
2256  || memcmp (buf, mov_rsp_rbp_2, 3) == 0)
2257  {
2258  /* OK, we actually have a frame. */
2259  cache->frameless_p = 0;
2260  return pc + 4;
2261  }
2262 
2263  /* For X32, also check for `movq %esp, %ebp'. */
2264  if (gdbarch_ptr_bit (gdbarch) == 32)
2265  {
2266  if (memcmp (buf, mov_esp_ebp_1, 2) == 0
2267  || memcmp (buf, mov_esp_ebp_2, 2) == 0)
2268  {
2269  /* OK, we actually have a frame. */
2270  cache->frameless_p = 0;
2271  return pc + 3;
2272  }
2273  }
2274 
2275  return pc + 1;
2276  }
2277 
2278  return pc;
2279 }
2280 
2281 /* Work around false termination of prologue - GCC PR debug/48827.
2282 
2283  START_PC is the first instruction of a function, PC is its minimal already
2284  determined advanced address. Function returns PC if it has nothing to do.
2285 
2286  84 c0 test %al,%al
2287  74 23 je after
2288  <-- here is 0 lines advance - the false prologue end marker.
2289  0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2290  0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2291  0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2292  0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2293  0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2294  0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2295  0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2296  0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2297  after: */
2298 
2299 static CORE_ADDR
2301 {
2302  struct symtab_and_line start_pc_sal, next_sal;
2303  gdb_byte buf[4 + 8 * 7];
2304  int offset, xmmreg;
2305 
2306  if (pc == start_pc)
2307  return pc;
2308 
2309  start_pc_sal = find_pc_sect_line (start_pc, NULL, 0);
2310  if (start_pc_sal.symtab == NULL
2312  (SYMTAB_COMPUNIT (start_pc_sal.symtab))) < 6
2313  || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end)
2314  return pc;
2315 
2316  next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0);
2317  if (next_sal.line != start_pc_sal.line)
2318  return pc;
2319 
2320  /* START_PC can be from overlayed memory, ignored here. */
2321  if (target_read_code (next_sal.pc - 4, buf, sizeof (buf)) != 0)
2322  return pc;
2323 
2324  /* test %al,%al */
2325  if (buf[0] != 0x84 || buf[1] != 0xc0)
2326  return pc;
2327  /* je AFTER */
2328  if (buf[2] != 0x74)
2329  return pc;
2330 
2331  offset = 4;
2332  for (xmmreg = 0; xmmreg < 8; xmmreg++)
2333  {
2334  /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2335  if (buf[offset] != 0x0f || buf[offset + 1] != 0x29
2336  || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5))
2337  return pc;
2338 
2339  /* 0b01?????? */
2340  if ((buf[offset + 2] & 0xc0) == 0x40)
2341  {
2342  /* 8-bit displacement. */
2343  offset += 4;
2344  }
2345  /* 0b10?????? */
2346  else if ((buf[offset + 2] & 0xc0) == 0x80)
2347  {
2348  /* 32-bit displacement. */
2349  offset += 7;
2350  }
2351  else
2352  return pc;
2353  }
2354 
2355  /* je AFTER */
2356  if (offset - 4 != buf[3])
2357  return pc;
2358 
2359  return next_sal.end;
2360 }
2361 
2362 /* Return PC of first real instruction. */
2363 
2364 static CORE_ADDR
2365 amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2366 {
2367  struct amd64_frame_cache cache;
2368  CORE_ADDR pc;
2369  CORE_ADDR func_addr;
2370 
2371  if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
2372  {
2373  CORE_ADDR post_prologue_pc
2374  = skip_prologue_using_sal (gdbarch, func_addr);
2375  struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
2376 
2377  /* Clang always emits a line note before the prologue and another
2378  one after. We trust clang to emit usable line notes. */
2379  if (post_prologue_pc
2380  && (cust != NULL
2381  && COMPUNIT_PRODUCER (cust) != NULL
2382  && startswith (COMPUNIT_PRODUCER (cust), "clang ")))
2383  return max (start_pc, post_prologue_pc);
2384  }
2385 
2386  amd64_init_frame_cache (&cache);
2387  pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL,
2388  &cache);
2389  if (cache.frameless_p)
2390  return start_pc;
2391 
2392  return amd64_skip_xmm_prologue (pc, start_pc);
2393 }
2394 
2395 
2396 /* Normal frames. */
2397 
2398 static void
2399 amd64_frame_cache_1 (struct frame_info *this_frame,
2400  struct amd64_frame_cache *cache)
2401 {
2402  struct gdbarch *gdbarch = get_frame_arch (this_frame);
2403  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2404  gdb_byte buf[8];
2405  int i;
2406 
2407  cache->pc = get_frame_func (this_frame);
2408  if (cache->pc != 0)
2409  amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
2410  cache);
2411 
2412  if (cache->frameless_p)
2413  {
2414  /* We didn't find a valid frame. If we're at the start of a
2415  function, or somewhere half-way its prologue, the function's
2416  frame probably hasn't been fully setup yet. Try to
2417  reconstruct the base address for the stack frame by looking
2418  at the stack pointer. For truly "frameless" functions this
2419  might work too. */
2420 
2421  if (cache->saved_sp_reg != -1)
2422  {
2423  /* Stack pointer has been saved. */
2424  get_frame_register (this_frame, cache->saved_sp_reg, buf);
2425  cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order);
2426 
2427  /* We're halfway aligning the stack. */
2428  cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8;
2429  cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8;
2430 
2431  /* This will be added back below. */
2432  cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base;
2433  }
2434  else
2435  {
2436  get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2437  cache->base = extract_unsigned_integer (buf, 8, byte_order)
2438  + cache->sp_offset;
2439  }
2440  }
2441  else
2442  {
2443  get_frame_register (this_frame, AMD64_RBP_REGNUM, buf);
2444  cache->base = extract_unsigned_integer (buf, 8, byte_order);
2445  }
2446 
2447  /* Now that we have the base address for the stack frame we can
2448  calculate the value of %rsp in the calling frame. */
2449  cache->saved_sp = cache->base + 16;
2450 
2451  /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2452  frame we find it at the same offset from the reconstructed base
2453  address. If we're halfway aligning the stack, %rip is handled
2454  differently (see above). */
2455  if (!cache->frameless_p || cache->saved_sp_reg == -1)
2456  cache->saved_regs[AMD64_RIP_REGNUM] = 8;
2457 
2458  /* Adjust all the saved registers such that they contain addresses
2459  instead of offsets. */
2460  for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
2461  if (cache->saved_regs[i] != -1)
2462  cache->saved_regs[i] += cache->base;
2463 
2464  cache->base_p = 1;
2465 }
2466 
2467 static struct amd64_frame_cache *
2468 amd64_frame_cache (struct frame_info *this_frame, void **this_cache)
2469 {
2470  struct amd64_frame_cache *cache;
2471 
2472  if (*this_cache)
2473  return *this_cache;
2474 
2475  cache = amd64_alloc_frame_cache ();
2476  *this_cache = cache;
2477 
2478  TRY
2479  {
2480  amd64_frame_cache_1 (this_frame, cache);
2481  }
2482  CATCH (ex, RETURN_MASK_ERROR)
2483  {
2484  if (ex.error != NOT_AVAILABLE_ERROR)
2485  throw_exception (ex);
2486  }
2487  END_CATCH
2488 
2489  return cache;
2490 }
2491 
2492 static enum unwind_stop_reason
2494  void **this_cache)
2495 {
2496  struct amd64_frame_cache *cache =
2497  amd64_frame_cache (this_frame, this_cache);
2498 
2499  if (!cache->base_p)
2500  return UNWIND_UNAVAILABLE;
2501 
2502  /* This marks the outermost frame. */
2503  if (cache->base == 0)
2504  return UNWIND_OUTERMOST;
2505 
2506  return UNWIND_NO_REASON;
2507 }
2508 
2509 static void
2510 amd64_frame_this_id (struct frame_info *this_frame, void **this_cache,
2511  struct frame_id *this_id)
2512 {
2513  struct amd64_frame_cache *cache =
2514  amd64_frame_cache (this_frame, this_cache);
2515 
2516  if (!cache->base_p)
2517  (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2518  else if (cache->base == 0)
2519  {
2520  /* This marks the outermost frame. */
2521  return;
2522  }
2523  else
2524  (*this_id) = frame_id_build (cache->base + 16, cache->pc);
2525 }
2526 
2527 static struct value *
2528 amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2529  int regnum)
2530 {
2531  struct gdbarch *gdbarch = get_frame_arch (this_frame);
2532  struct amd64_frame_cache *cache =
2533  amd64_frame_cache (this_frame, this_cache);
2534 
2535  gdb_assert (regnum >= 0);
2536 
2537  if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
2538  return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
2539 
2540  if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2541  return frame_unwind_got_memory (this_frame, regnum,
2542  cache->saved_regs[regnum]);
2543 
2544  return frame_unwind_got_register (this_frame, regnum, regnum);
2545 }
2546 
2547 static const struct frame_unwind amd64_frame_unwind =
2548 {
2549  NORMAL_FRAME,
2553  NULL,
2555 };
2556 
2557 /* Generate a bytecode expression to get the value of the saved PC. */
2558 
2559 static void
2560 amd64_gen_return_address (struct gdbarch *gdbarch,
2561  struct agent_expr *ax, struct axs_value *value,
2562  CORE_ADDR scope)
2563 {
2564  /* The following sequence assumes the traditional use of the base
2565  register. */
2566  ax_reg (ax, AMD64_RBP_REGNUM);
2567  ax_const_l (ax, 8);
2568  ax_simple (ax, aop_add);
2569  value->type = register_type (gdbarch, AMD64_RIP_REGNUM);
2570  value->kind = axs_lvalue_memory;
2571 }
2572 
2573 
2574 /* Signal trampolines. */
2575 
2576 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2577  64-bit variants. This would require using identical frame caches
2578  on both platforms. */
2579 
2580 static struct amd64_frame_cache *
2581 amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2582 {
2583  struct gdbarch *gdbarch = get_frame_arch (this_frame);
2584  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2585  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2586  struct amd64_frame_cache *cache;
2587  CORE_ADDR addr;
2588  gdb_byte buf[8];
2589  int i;
2590 
2591  if (*this_cache)
2592  return *this_cache;
2593 
2594  cache = amd64_alloc_frame_cache ();
2595 
2596  TRY
2597  {
2598  get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2599  cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8;
2600 
2601  addr = tdep->sigcontext_addr (this_frame);
2602  gdb_assert (tdep->sc_reg_offset);
2604  for (i = 0; i < tdep->sc_num_regs; i++)
2605  if (tdep->sc_reg_offset[i] != -1)
2606  cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2607 
2608  cache->base_p = 1;
2609  }
2610  CATCH (ex, RETURN_MASK_ERROR)
2611  {
2612  if (ex.error != NOT_AVAILABLE_ERROR)
2613  throw_exception (ex);
2614  }
2615  END_CATCH
2616 
2617  *this_cache = cache;
2618  return cache;
2619 }
2620 
2621 static enum unwind_stop_reason
2623  void **this_cache)
2624 {
2625  struct amd64_frame_cache *cache =
2626  amd64_sigtramp_frame_cache (this_frame, this_cache);
2627 
2628  if (!cache->base_p)
2629  return UNWIND_UNAVAILABLE;
2630 
2631  return UNWIND_NO_REASON;
2632 }
2633 
2634 static void
2636  void **this_cache, struct frame_id *this_id)
2637 {
2638  struct amd64_frame_cache *cache =
2639  amd64_sigtramp_frame_cache (this_frame, this_cache);
2640 
2641  if (!cache->base_p)
2642  (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2643  else if (cache->base == 0)
2644  {
2645  /* This marks the outermost frame. */
2646  return;
2647  }
2648  else
2649  (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame));
2650 }
2651 
2652 static struct value *
2654  void **this_cache, int regnum)
2655 {
2656  /* Make sure we've initialized the cache. */
2657  amd64_sigtramp_frame_cache (this_frame, this_cache);
2658 
2659  return amd64_frame_prev_register (this_frame, this_cache, regnum);
2660 }
2661 
2662 static int
2664  struct frame_info *this_frame,
2665  void **this_cache)
2666 {
2667  struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2668 
2669  /* We shouldn't even bother if we don't have a sigcontext_addr
2670  handler. */
2671  if (tdep->sigcontext_addr == NULL)
2672  return 0;
2673 
2674  if (tdep->sigtramp_p != NULL)
2675  {
2676  if (tdep->sigtramp_p (this_frame))
2677  return 1;
2678  }
2679 
2680  if (tdep->sigtramp_start != 0)
2681  {
2682  CORE_ADDR pc = get_frame_pc (this_frame);
2683 
2684  gdb_assert (tdep->sigtramp_end != 0);
2685  if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2686  return 1;
2687  }
2688 
2689  return 0;
2690 }
2691 
2692 static const struct frame_unwind amd64_sigtramp_frame_unwind =
2693 {
2698  NULL,
2700 };
2701 
2702 
2703 static CORE_ADDR
2704 amd64_frame_base_address (struct frame_info *this_frame, void **this_cache)
2705 {
2706  struct amd64_frame_cache *cache =
2707  amd64_frame_cache (this_frame, this_cache);
2708 
2709  return cache->base;
2710 }
2711 
2712 static const struct frame_base amd64_frame_base =
2713 {
2717  amd64_frame_base_address
2718 };
2719 
2720 /* Normal frames, but in a function epilogue. */
2721 
2722 /* Implement the stack_frame_destroyed_p gdbarch method.
2723 
2724  The epilogue is defined here as the 'ret' instruction, which will
2725  follow any instruction such as 'leave' or 'pop %ebp' that destroys
2726  the function's stack frame. */
2727 
2728 static int
2729 amd64_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2730 {
2731  gdb_byte insn;
2732  struct compunit_symtab *cust;
2733 
2734  cust = find_pc_compunit_symtab (pc);
2735  if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
2736  return 0;
2737 
2738  if (target_read_memory (pc, &insn, 1))
2739  return 0; /* Can't read memory at pc. */
2740 
2741  if (insn != 0xc3) /* 'ret' instruction. */
2742  return 0;
2743 
2744  return 1;
2745 }
2746 
2747 static int
2749  struct frame_info *this_frame,
2750  void **this_prologue_cache)
2751 {
2752  if (frame_relative_level (this_frame) == 0)
2753  return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame),
2754  get_frame_pc (this_frame));
2755  else
2756  return 0;
2757 }
2758 
2759 static struct amd64_frame_cache *
2760 amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2761 {
2762  struct gdbarch *gdbarch = get_frame_arch (this_frame);
2763  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2764  struct amd64_frame_cache *cache;
2765  gdb_byte buf[8];
2766 
2767  if (*this_cache)
2768  return *this_cache;
2769 
2770  cache = amd64_alloc_frame_cache ();
2771  *this_cache = cache;
2772 
2773  TRY
2774  {
2775  /* Cache base will be %esp plus cache->sp_offset (-8). */
2776  get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2777  cache->base = extract_unsigned_integer (buf, 8,
2778  byte_order) + cache->sp_offset;
2779 
2780  /* Cache pc will be the frame func. */
2781  cache->pc = get_frame_pc (this_frame);
2782 
2783  /* The saved %esp will be at cache->base plus 16. */
2784  cache->saved_sp = cache->base + 16;
2785 
2786  /* The saved %eip will be at cache->base plus 8. */
2787  cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8;
2788 
2789  cache->base_p = 1;
2790  }
2791  CATCH (ex, RETURN_MASK_ERROR)
2792  {
2793  if (ex.error != NOT_AVAILABLE_ERROR)
2794  throw_exception (ex);
2795  }
2796  END_CATCH
2797 
2798  return cache;
2799 }
2800 
2801 static enum unwind_stop_reason
2803  void **this_cache)
2804 {
2805  struct amd64_frame_cache *cache
2806  = amd64_epilogue_frame_cache (this_frame, this_cache);
2807 
2808  if (!cache->base_p)
2809  return UNWIND_UNAVAILABLE;
2810 
2811  return UNWIND_NO_REASON;
2812 }
2813 
2814 static void
2816  void **this_cache,
2817  struct frame_id *this_id)
2818 {
2819  struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame,
2820  this_cache);
2821 
2822  if (!cache->base_p)
2823  (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2824  else
2825  (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2826 }
2827 
2828 static const struct frame_unwind amd64_epilogue_frame_unwind =
2829 {
2830  NORMAL_FRAME,
2834  NULL,
2836 };
2837 
2838 static struct frame_id
2839 amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2840 {
2841  CORE_ADDR fp;
2842 
2843  fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM);
2844 
2845  return frame_id_build (fp + 16, get_frame_pc (this_frame));
2846 }
2847 
2848 /* 16 byte align the SP per frame requirements. */
2849 
2850 static CORE_ADDR
2851 amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2852 {
2853  return sp & -(CORE_ADDR)16;
2854 }
2855 
2856 
2857 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2858  in the floating-point register set REGSET to register cache
2859  REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2860 
2861 static void
2863  int regnum, const void *fpregs, size_t len)
2864 {
2865  struct gdbarch *gdbarch = get_regcache_arch (regcache);
2866  const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2867 
2868  gdb_assert (len >= tdep->sizeof_fpregset);
2869  amd64_supply_fxsave (regcache, regnum, fpregs);
2870 }
2871 
2872 /* Collect register REGNUM from the register cache REGCACHE and store
2873  it in the buffer specified by FPREGS and LEN as described by the
2874  floating-point register set REGSET. If REGNUM is -1, do this for
2875  all registers in REGSET. */
2876 
2877 static void
2879  const struct regcache *regcache,
2880  int regnum, void *fpregs, size_t len)
2881 {
2882  struct gdbarch *gdbarch = get_regcache_arch (regcache);
2883  const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2884 
2885  gdb_assert (len >= tdep->sizeof_fpregset);
2886  amd64_collect_fxsave (regcache, regnum, fpregs);
2887 }
2888 
2889 const struct regset amd64_fpregset =
2890  {
2892  };
2893 
2894 
2895 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
2896  %rdi. We expect its value to be a pointer to the jmp_buf structure
2897  from which we extract the address that we will land at. This
2898  address is copied into PC. This routine returns non-zero on
2899  success. */
2900 
2901 static int
2903 {
2904  gdb_byte buf[8];
2905  CORE_ADDR jb_addr;
2906  struct gdbarch *gdbarch = get_frame_arch (frame);
2907  int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2908  int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr);
2909 
2910  /* If JB_PC_OFFSET is -1, we have no way to find out where the
2911  longjmp will land. */
2912  if (jb_pc_offset == -1)
2913  return 0;
2914 
2915  get_frame_register (frame, AMD64_RDI_REGNUM, buf);
2916  jb_addr= extract_typed_address
2917  (buf, builtin_type (gdbarch)->builtin_data_ptr);
2918  if (target_read_memory (jb_addr + jb_pc_offset, buf, len))
2919  return 0;
2920 
2921  *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
2922 
2923  return 1;
2924 }
2925 
2926 static const int amd64_record_regmap[] =
2927 {
2934 };
2935 
2936 void
2937 amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
2938 {
2939  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2940  const struct target_desc *tdesc = info.target_desc;
2941  static const char *const stap_integer_prefixes[] = { "$", NULL };
2942  static const char *const stap_register_prefixes[] = { "%", NULL };
2943  static const char *const stap_register_indirection_prefixes[] = { "(",
2944  NULL };
2945  static const char *const stap_register_indirection_suffixes[] = { ")",
2946  NULL };
2947 
2948  /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
2949  floating-point registers. */
2951  tdep->fpregset = &amd64_fpregset;
2952 
2953  if (! tdesc_has_registers (tdesc))
2954  tdesc = tdesc_amd64;
2955  tdep->tdesc = tdesc;
2956 
2959 
2960  if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512") != NULL)
2961  {
2966 
2967  tdep->num_zmm_regs = 32;
2968  tdep->num_xmm_avx512_regs = 16;
2969  tdep->num_ymm_avx512_regs = 16;
2970 
2972  tdep->k0_regnum = AMD64_K0_REGNUM;
2975  }
2976 
2977  if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL)
2978  {
2980  tdep->num_ymm_regs = 16;
2982  }
2983 
2984  if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL)
2985  {
2989  }
2990 
2991  tdep->num_byte_regs = 20;
2992  tdep->num_word_regs = 16;
2993  tdep->num_dword_regs = 16;
2994  /* Avoid wiring in the MMX registers for now. */
2995  tdep->num_mmx_regs = 0;
2996 
3001 
3003 
3004  /* AMD64 has an FPU and 16 SSE registers. */
3005  tdep->st0_regnum = AMD64_ST0_REGNUM;
3006  tdep->num_xmm_regs = 16;
3007 
3008  /* This is what all the fuss is about. */
3009  set_gdbarch_long_bit (gdbarch, 64);
3010  set_gdbarch_long_long_bit (gdbarch, 64);
3011  set_gdbarch_ptr_bit (gdbarch, 64);
3012 
3013  /* In contrast to the i386, on AMD64 a `long double' actually takes
3014  up 128 bits, even though it's still based on the i387 extended
3015  floating-point format which has only 80 significant bits. */
3016  set_gdbarch_long_double_bit (gdbarch, 128);
3017 
3019 
3020  /* Register numbers of various important registers. */
3021  set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
3022  set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
3023  set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
3024  set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
3025 
3026  /* The "default" register numbering scheme for AMD64 is referred to
3027  as the "DWARF Register Number Mapping" in the System V psABI.
3028  The preferred debugging format for all known AMD64 targets is
3029  actually DWARF2, and GCC doesn't seem to support DWARF (that is
3030  DWARF-1), but we provide the same mapping just in case. This
3031  mapping is also used for stabs, which GCC does support. */
3034 
3035  /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
3036  be in use on any of the supported AMD64 targets. */
3037 
3038  /* Call dummy code. */
3041  set_gdbarch_frame_red_zone_size (gdbarch, 128);
3042 
3046 
3048 
3050 
3052 
3054 
3055  /* Hook the function epilogue frame unwinder. This unwinder is
3056  appended to the list first, so that it supercedes the other
3057  unwinders in function epilogues. */
3058  frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind);
3059 
3060  /* Hook the prologue-based frame unwinders. */
3061  frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind);
3062  frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind);
3063  frame_base_set_default (gdbarch, &amd64_frame_base);
3064 
3066 
3068 
3070 
3071  /* SystemTap variables and functions. */
3072  set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
3073  set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
3075  stap_register_indirection_prefixes);
3077  stap_register_indirection_suffixes);
3085 }
3086 
3087 
3088 static struct type *
3089 amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3090 {
3091  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3092 
3093  switch (regnum - tdep->eax_regnum)
3094  {
3095  case AMD64_RBP_REGNUM: /* %ebp */
3096  case AMD64_RSP_REGNUM: /* %esp */
3097  return builtin_type (gdbarch)->builtin_data_ptr;
3098  case AMD64_RIP_REGNUM: /* %eip */
3099  return builtin_type (gdbarch)->builtin_func_ptr;
3100  }
3101 
3102  return i386_pseudo_register_type (gdbarch, regnum);
3103 }
3104 
3105 void
3106 amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3107 {
3108  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3109  const struct target_desc *tdesc = info.target_desc;
3110 
3111  amd64_init_abi (info, gdbarch);
3112 
3113  if (! tdesc_has_registers (tdesc))
3114  tdesc = tdesc_x32;
3115  tdep->tdesc = tdesc;
3116 
3117  tdep->num_dword_regs = 17;
3119 
3120  set_gdbarch_long_bit (gdbarch, 32);
3121  set_gdbarch_ptr_bit (gdbarch, 32);
3122 }
3123 
3124 /* Return the target description for a specified XSAVE feature mask. */
3125 
3126 const struct target_desc *
3128 {
3129  switch (xcr0 & X86_XSTATE_ALL_MASK)
3130  {
3133  return tdesc_amd64_avx512;
3134  case X86_XSTATE_MPX_MASK:
3135  return tdesc_amd64_mpx;
3136  case X86_XSTATE_AVX_MASK:
3137  return tdesc_amd64_avx;
3138  default:
3139  return tdesc_amd64;
3140  }
3141 }
3142 
3143 /* Provide a prototype to silence -Wmissing-prototypes. */
3144 void _initialize_amd64_tdep (void);
3145 
3146 void
3148 {
3153 
3157 }
3158 
3159 
3160 /* The 64-bit FXSAVE format differs from the 32-bit format in the
3161  sense that the instruction pointer and data pointer are simply
3162  64-bit offsets into the code segment and the data segment instead
3163  of a selector offset pair. The functions below store the upper 32
3164  bits of these pointers (instead of just the 16-bits of the segment
3165  selector). */
3166 
3167 /* Fill register REGNUM in REGCACHE with the appropriate
3168  floating-point or SSE register value from *FXSAVE. If REGNUM is
3169  -1, do this for all registers. This function masks off any of the
3170  reserved bits in *FXSAVE. */
3171 
3172 void
3174  const void *fxsave)
3175 {
3176  struct gdbarch *gdbarch = get_regcache_arch (regcache);
3177  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3178 
3179  i387_supply_fxsave (regcache, regnum, fxsave);
3180 
3181  if (fxsave
3182  && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3183  {
3184  const gdb_byte *regs = fxsave;
3185 
3186  if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3187  regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
3188  if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3189  regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
3190  }
3191 }
3192 
3193 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3194 
3195 void
3197  const void *xsave)
3198 {
3199  struct gdbarch *gdbarch = get_regcache_arch (regcache);
3200  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3201 
3202  i387_supply_xsave (regcache, regnum, xsave);
3203 
3204  if (xsave
3205  && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3206  {
3207  const gdb_byte *regs = xsave;
3208 
3209  if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3210  regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep),
3211  regs + 12);
3212  if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3213  regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep),
3214  regs + 20);
3215  }
3216 }
3217 
3218 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3219  *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3220  all registers. This function doesn't touch any of the reserved
3221  bits in *FXSAVE. */
3222 
3223 void
3225  void *fxsave)
3226 {
3227  struct gdbarch *gdbarch = get_regcache_arch (regcache);
3228  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3229  gdb_byte *regs = fxsave;
3230 
3231  i387_collect_fxsave (regcache, regnum, fxsave);
3232 
3233  if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3234  {
3235  if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3236  regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
3237  if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3238  regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
3239  }
3240 }
3241 
3242 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
3243 
3244 void
3246  void *xsave, int gcore)
3247 {
3248  struct gdbarch *gdbarch = get_regcache_arch (regcache);
3249  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3250  gdb_byte *regs = xsave;
3251 
3252  i387_collect_xsave (regcache, regnum, xsave, gcore);
3253 
3254  if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
3255  {
3256  if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3257  regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep),
3258  regs + 12);
3259  if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3260  regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep),
3261  regs + 20);
3262  }
3263 }
int i386_zmm_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:226
void set_gdbarch_num_regs(struct gdbarch *gdbarch, int num_regs)
Definition: gdbarch.c:1909
void set_gdbarch_frame_align(struct gdbarch *gdbarch, gdbarch_frame_align_ftype frame_align)
Definition: gdbarch.c:2935
#define X86_XSTATE_AVX_MASK
Definition: x86-xstate.h:41
void set_gdbarch_value_to_register(struct gdbarch *gdbarch, gdbarch_value_to_register_ftype value_to_register)
Definition: gdbarch.c:2457
struct target_desc * tdesc_amd64_avx
Definition: amd64-avx.c:8
ULONGEST extract_unsigned_integer(const gdb_byte *, int, enum bfd_endian)
Definition: findvar.c:84
static enum unwind_stop_reason amd64_sigtramp_frame_unwind_stop_reason(struct frame_info *this_frame, void **this_cache)
Definition: amd64-tdep.c:2622
type_code
Definition: gdbtypes.h:85
#define SYMTAB_COMPUNIT(symtab)
Definition: symtab.h:965
static CORE_ADDR amd64_skip_prologue(struct gdbarch *gdbarch, CORE_ADDR start_pc)
Definition: amd64-tdep.c:2365
int jb_pc_offset
Definition: i386-tdep.h:199
void set_gdbarch_ps_regnum(struct gdbarch *gdbarch, int ps_regnum)
Definition: gdbarch.c:2025
struct frame_id frame_id_build(CORE_ADDR stack_addr, CORE_ADDR code_addr)
Definition: frame.c:554
CORE_ADDR extract_typed_address(const gdb_byte *buf, struct type *type)
Definition: findvar.c:169
void set_gdbarch_get_longjmp_target(struct gdbarch *gdbarch, gdbarch_get_longjmp_target_ftype get_longjmp_target)
Definition: gdbarch.c:2390
int zmm0_regnum
Definition: i386-tdep.h:97
static int amd64_syscall_p(const struct amd64_insn *insn, int *lengthp)
Definition: amd64-tdep.c:1492
amd64_reg_class
Definition: amd64-tdep.c:464
int xmm16_regnum
Definition: i386-tdep.h:128
struct type * builtin_func_ptr
Definition: gdbtypes.h:1544
void set_tdesc_pseudo_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype *pseudo_name)
int num_core_regs
Definition: i386-tdep.h:119
struct target_desc * tdesc_amd64_mpx
Definition: amd64-mpx.c:8
CORE_ADDR get_frame_pc(struct frame_info *frame)
Definition: frame.c:2217
static void fixup_riprel(struct gdbarch *gdbarch, struct displaced_step_closure *dsc, CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
Definition: amd64-tdep.c:1274
void set_gdbarch_fp0_regnum(struct gdbarch *gdbarch, int fp0_regnum)
Definition: gdbarch.c:2042
static int amd64_arch_reg_to_regnum(int reg)
Definition: amd64-tdep.c:293
static CORE_ADDR amd64_push_arguments(struct regcache *regcache, int nargs, struct value **args, CORE_ADDR sp, int struct_return)
Definition: amd64-tdep.c:833
static void append_insns(CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
Definition: amd64-tdep.c:1700
static CORE_ADDR amd64_skip_xmm_prologue(CORE_ADDR pc, CORE_ADDR start_pc)
Definition: amd64-tdep.c:2300
bfd_vma CORE_ADDR
Definition: common-types.h:41
const char ** mpx_register_names
Definition: i386-tdep.h:174
void displaced_step_dump_bytes(struct ui_file *file, const gdb_byte *buf, size_t len)
Definition: infrun.c:1615
int target_write_memory(CORE_ADDR memaddr, const gdb_byte *myaddr, ssize_t len)
Definition: target.c:1474
#define TYPE_N_BASECLASSES(thistype)
Definition: gdbtypes.h:1327
struct type * i386_pseudo_register_type(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:3186
static enum return_value_convention amd64_return_value(struct gdbarch *gdbarch, struct value *function, struct type *type, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf)
Definition: amd64-tdep.c:699
int producer_is_gcc_ge_4(const char *producer)
Definition: utils.c:3147
int sc_num_regs
Definition: i386-tdep.h:216
static int amd64_call_p(const struct amd64_insn *details)
Definition: amd64-tdep.c:1474
void set_gdbarch_stap_parse_special_token(struct gdbarch *gdbarch, gdbarch_stap_parse_special_token_ftype stap_parse_special_token)
Definition: gdbarch.c:4243
int i386_dword_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:198
const char ** ymm16h_register_names
Definition: i386-tdep.h:159
struct displaced_step_closure * amd64_displaced_step_copy_insn(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
Definition: amd64-tdep.c:1346
static int amd64_insn_is_ret(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: amd64-tdep.c:1538
void store_signed_integer(gdb_byte *, int, enum bfd_endian, LONGEST)
Definition: findvar.c:184
#define X86_XSTATE_MPX_MASK
Definition: x86-xstate.h:42
struct gdbarch * get_regcache_arch(const struct regcache *regcache)
Definition: regcache.c:297
struct value * frame_unwind_got_memory(struct frame_info *frame, int regnum, CORE_ADDR addr)
Definition: frame-unwind.c:228
void write_memory_unsigned_integer(CORE_ADDR addr, int len, enum bfd_endian byte_order, ULONGEST value)
Definition: corefile.c:412
static const char * amd64_register_names[]
Definition: amd64-tdep.c:65
void set_tdesc_pseudo_register_type(struct gdbarch *gdbarch, gdbarch_register_type_ftype *pseudo_type)
CORE_ADDR sigtramp_start
Definition: i386-tdep.h:205
int ymm16_regnum
Definition: i386-tdep.h:134
void _initialize_amd64_tdep(void)
Definition: amd64-tdep.c:3147
void set_gdbarch_relocate_instruction(struct gdbarch *gdbarch, gdbarch_relocate_instruction_ftype relocate_instruction)
Definition: gdbarch.c:3768
void warning(const char *fmt,...)
Definition: errors.c:26
CORE_ADDR end
Definition: symtab.h:1377
void set_gdbarch_gen_return_address(struct gdbarch *gdbarch, gdbarch_gen_return_address_ftype gen_return_address)
Definition: gdbarch.c:4491
void i387_supply_fxsave(struct regcache *regcache, int regnum, const void *fxsave)
Definition: i387-tdep.c:595
void set_gdbarch_stab_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_stab_reg_to_regnum_ftype stab_reg_to_regnum)
Definition: gdbarch.c:2059
static void amd64_get_insn_details(gdb_byte *insn, struct amd64_insn *details)
Definition: amd64-tdep.c:1204
int num_mmx_regs
Definition: i386-tdep.h:72
int gdbarch_ptr_bit(struct gdbarch *gdbarch)
Definition: gdbarch.c:1690
static int amd64_insn_is_jump(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: amd64-tdep.c:1546
void set_gdbarch_stap_register_prefixes(struct gdbarch *gdbarch, const char *const *stap_register_prefixes)
Definition: gdbarch.c:4110
static enum unwind_stop_reason amd64_frame_unwind_stop_reason(struct frame_info *this_frame, void **this_cache)
Definition: amd64-tdep.c:2493
static struct amd64_frame_cache * amd64_sigtramp_frame_cache(struct frame_info *this_frame, void **this_cache)
Definition: amd64-tdep.c:2581
const struct builtin_type * builtin_type(struct gdbarch *gdbarch)
Definition: gdbtypes.c:4766
void amd64_displaced_step_fixup(struct gdbarch *gdbarch, struct displaced_step_closure *dsc, CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
Definition: amd64-tdep.c:1555
struct frame_id frame_id_build_unavailable_stack(CORE_ADDR code_addr)
Definition: frame.c:527
void set_gdbarch_frame_red_zone_size(struct gdbarch *gdbarch, int frame_red_zone_size)
Definition: gdbarch.c:2968
void internal_error(const char *file, int line, const char *fmt,...)
Definition: errors.c:50
int num_word_regs
Definition: i386-tdep.h:106
CORE_ADDR sigtramp_end
Definition: i386-tdep.h:206
struct m32c_reg * pc
Definition: m32c-tdep.c:111
#define AMD64_NUM_SAVED_REGS
Definition: amd64-tdep.c:1802
return_value_convention
Definition: defs.h:206
static CORE_ADDR amd64_analyze_stack_align(CORE_ADDR pc, CORE_ADDR current_pc, struct amd64_frame_cache *cache)
Definition: amd64-tdep.c:1867
static int amd64_ret_p(const struct amd64_insn *details)
Definition: amd64-tdep.c:1454
int i386_stap_parse_special_token(struct gdbarch *gdbarch, struct stap_parse_info *p)
Definition: i386-tdep.c:4271
static enum unwind_stop_reason amd64_epilogue_frame_unwind_stop_reason(struct frame_info *this_frame, void **this_cache)
Definition: amd64-tdep.c:2802
static const char * amd64_zmm_names[]
Definition: amd64-tdep.c:138
static struct type * amd64_x32_pseudo_register_type(struct gdbarch *gdbarch, int regnum)
Definition: amd64-tdep.c:3089
CORE_ADDR(* sigcontext_addr)(struct frame_info *)
Definition: alpha-tdep.h:82
static void initialize_tdesc_amd64(void)
Definition: amd64.c:10
static int amd64_get_longjmp_target(struct frame_info *frame, CORE_ADDR *pc)
Definition: amd64-tdep.c:2902
struct target_desc * tdesc_x32
Definition: x32.c:8
struct target_desc * tdesc_amd64
Definition: amd64.c:8
Definition: ax.h:95
unwind_stop_reason
Definition: frame.h:486
void mark_value_bytes_unavailable(struct value *value, int offset, int length)
Definition: value.c:593
CORE_ADDR skip_prologue_using_sal(struct gdbarch *gdbarch, CORE_ADDR func_addr)
Definition: symtab.c:3882
static const char * amd64_ymmh_avx512_names[]
Definition: amd64-tdep.c:107
void ax_reg(struct agent_expr *x, int reg)
Definition: ax-general.c:290
int num_zmm_regs
Definition: i386-tdep.h:93
int ymm0h_regnum
Definition: i386-tdep.h:149
static void amd64_classify_aggregate(struct type *type, enum amd64_reg_class theclass[2])
Definition: amd64-tdep.c:531
#define _(String)
Definition: gdb_locale.h:40
size_t sizeof_fpregset
Definition: i386-tdep.h:64
static int rip_relative_offset(struct amd64_insn *insn)
Definition: amd64-tdep.c:1683
void set_gdbarch_dwarf2_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_dwarf2_reg_to_regnum_ftype dwarf2_reg_to_regnum)
Definition: gdbarch.c:2110
#define TYPE_FIELD(thistype, n)
Definition: gdbtypes.h:1367
static void amd64_supply_fpregset(const struct regset *regset, struct regcache *regcache, int regnum, const void *fpregs, size_t len)
Definition: amd64-tdep.c:2862
struct gdbarch_tdep * gdbarch_tdep(struct gdbarch *gdbarch)
Definition: gdbarch.c:1402
static struct value * amd64_sigtramp_frame_prev_register(struct frame_info *this_frame, void **this_cache, int regnum)
Definition: amd64-tdep.c:2653
#define END_CATCH
#define TYPE_FIELD_TYPE(thistype, n)
Definition: gdbtypes.h:1368
struct type * type
Definition: ax-gdb.h:82
void frame_unwind_prepend_unwinder(struct gdbarch *gdbarch, const struct frame_unwind *unwinder)
Definition: frame-unwind.c:64
int num_ymm_regs
Definition: i386-tdep.h:79
#define VALUE_LVAL(val)
Definition: value.h:411
char ** register_names
Definition: frv-tdep.c:90
struct value * allocate_value(struct type *type)
Definition: value.c:962
void frame_unwind_append_unwinder(struct gdbarch *gdbarch, const struct frame_unwind *unwinder)
Definition: frame-unwind.c:78
int rex_offset
Definition: amd64-tdep.c:1008
static const char * amd64_ymm_avx512_names[]
Definition: amd64-tdep.c:91
int ymm0_regnum
Definition: i386-tdep.h:83
int num_xmm_avx512_regs
Definition: i386-tdep.h:125
#define FRAME_OBSTACK_ZALLOC(TYPE)
Definition: frame.h:660
void store_unsigned_integer(gdb_byte *, int, enum bfd_endian, ULONGEST)
Definition: findvar.c:212
const char * paddress(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: utils.c:2743
void set_gdbarch_stap_register_indirection_suffixes(struct gdbarch *gdbarch, const char *const *stap_register_indirection_suffixes)
Definition: gdbarch.c:4161
struct value * frame_unwind_got_constant(struct frame_info *frame, int regnum, ULONGEST val)
Definition: frame-unwind.c:241
int i386_xmm_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:323
void i387_value_to_register(struct frame_info *frame, int regnum, struct type *type, const gdb_byte *from)
Definition: i387-tdep.c:390
ULONGEST read_code_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition: corefile.c:341
static enum amd64_reg_class amd64_merge_classes(enum amd64_reg_class class1, enum amd64_reg_class class2)
Definition: amd64-tdep.c:480
struct compunit_symtab * find_pc_compunit_symtab(CORE_ADDR pc)
Definition: symtab.c:3051
int target_read_code(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition: target.c:1456
Definition: regset.h:34
int i386_byte_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:176
static struct amd64_frame_cache * amd64_alloc_frame_cache(void)
Definition: amd64-tdep.c:1851
int i386_ymm_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:267
static CORE_ADDR amd64_analyze_prologue(struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR current_pc, struct amd64_frame_cache *cache)
Definition: amd64-tdep.c:2216
void amd64_collect_fxsave(const struct regcache *regcache, int regnum, void *fxsave)
Definition: amd64-tdep.c:3224
#define TRY
void set_gdbarch_stap_integer_prefixes(struct gdbarch *gdbarch, const char *const *stap_integer_prefixes)
Definition: gdbarch.c:4076
static const int amd64_dwarf_regmap_len
Definition: amd64-tdep.c:239
void i387_return_value(struct gdbarch *gdbarch, struct regcache *regcache)
Definition: i387-tdep.c:1756
static struct frame_id amd64_dummy_id(struct gdbarch *gdbarch, struct frame_info *this_frame)
Definition: amd64-tdep.c:2839
void amd64_x32_init_abi(struct gdbarch_info info, struct gdbarch *gdbarch)
Definition: amd64-tdep.c:3106
void frame_base_set_default(struct gdbarch *gdbarch, const struct frame_base *default_base)
Definition: frame-base.c:94
int * from
Definition: varobj.h:282
static int amd64_dwarf_regmap[]
Definition: amd64-tdep.c:160
static void initialize_tdesc_x32(void)
Definition: x32.c:10
static const char * amd64_mpx_names[]
Definition: amd64-tdep.c:115
void set_gdbarch_pseudo_register_write(struct gdbarch *gdbarch, gdbarch_pseudo_register_write_ftype pseudo_register_write)
Definition: gdbarch.c:1891
static const char * amd64_xmm_avx512_names[]
Definition: amd64-tdep.c:150
static const char * amd64_ymmh_names[]
Definition: amd64-tdep.c:99
void set_gdbarch_pseudo_register_read_value(struct gdbarch *gdbarch, gdbarch_pseudo_register_read_value_ftype pseudo_register_read_value)
Definition: gdbarch.c:1867
struct type * check_typedef(struct type *type)
Definition: gdbtypes.c:2217
ULONGEST gdbarch_max_insn_length(struct gdbarch *gdbarch)
Definition: gdbarch.c:3632
const gdb_byte * value_contents(struct value *value)
Definition: value.c:1329
#define CATCH(EXCEPTION, MASK)
enum register_status regcache_raw_read_part(struct regcache *regcache, int regnum, int offset, int len, gdb_byte *buf)
Definition: regcache.c:995
void i387_collect_fxsave(const struct regcache *regcache, int regnum, void *fxsave)
Definition: i387-tdep.c:678
void amd64_supply_fxsave(struct regcache *regcache, int regnum, const void *fxsave)
Definition: amd64-tdep.c:3173
static int amd64_non_pod_p(struct type *type)
Definition: amd64-tdep.c:517
static const char * amd64_ymm_names[]
Definition: amd64-tdep.c:83
int field_is_static(struct field *f)
Definition: gdbtypes.c:3797
int gdbarch_sp_regnum(struct gdbarch *gdbarch)
Definition: gdbarch.c:1981
void set_gdbarch_insn_is_ret(struct gdbarch *gdbarch, gdbarch_insn_is_ret_ftype insn_is_ret)
Definition: gdbarch.c:4607
static void amd64_collect_fpregset(const struct regset *regset, const struct regcache *regcache, int regnum, void *fpregs, size_t len)
Definition: amd64-tdep.c:2878
register_status
Definition: regcache.h:50
enum register_status regcache_cooked_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition: regcache.c:837
const char ** ymmh_register_names
Definition: i386-tdep.h:152
void set_gdbarch_sp_regnum(struct gdbarch *gdbarch, int sp_regnum)
Definition: gdbarch.c:1991
int debug_displaced
Definition: infrun.c:132
struct type * register_type(struct gdbarch *gdbarch, int regnum)
Definition: regcache.c:157
void set_gdbarch_dummy_id(struct gdbarch *gdbarch, gdbarch_dummy_id_ftype dummy_id)
Definition: gdbarch.c:2175
static int amd64_jmp_p(const struct amd64_insn *details)
Definition: amd64-tdep.c:1419
void fprintf_unfiltered(struct ui_file *stream, const char *format,...)
Definition: utils.c:2361
#define I387_XMM0_REGNUM(tdep)
Definition: i387-tdep.h:62
mach_port_t mach_port_t name mach_port_t mach_port_t name error_t int status
Definition: gnu-nat.c:1816
struct_return
Definition: arm-tdep.h:148
static void amd64_classify(struct type *type, enum amd64_reg_class theclass[2])
Definition: amd64-tdep.c:634
static void initialize_tdesc_amd64_avx(void)
Definition: amd64-avx.c:10
void amd64_supply_xsave(struct regcache *regcache, int regnum, const void *xsave)
Definition: amd64-tdep.c:3196
static int rex_prefix_p(gdb_byte pfx)
Definition: amd64-tdep.c:1089
enum bfd_endian gdbarch_byte_order(struct gdbarch *gdbarch)
Definition: gdbarch.c:1420
#define AMD64_NUM_GREGS
Definition: amd64-tdep.h:83
#define I387_FISEG_REGNUM(tdep)
Definition: i387-tdep.h:57
static void initialize_tdesc_x32_avx(void)
Definition: x32-avx.c:10
int num_ymm_avx512_regs
Definition: i386-tdep.h:131
static void amd64_frame_this_id(struct frame_info *this_frame, void **this_cache, struct frame_id *this_id)
Definition: amd64-tdep.c:2510
void set_gdbarch_stap_register_indirection_prefixes(struct gdbarch *gdbarch, const char *const *stap_register_indirection_prefixes)
Definition: gdbarch.c:4144
Definition: gdbtypes.h:749
int find_pc_partial_function(CORE_ADDR pc, const char **name, CORE_ADDR *address, CORE_ADDR *endaddr)
Definition: blockframe.c:321
#define VALUE_REGNUM(val)
Definition: value.h:440
void set_gdbarch_register_to_value(struct gdbarch *gdbarch, gdbarch_register_to_value_ftype register_to_value)
Definition: gdbarch.c:2440
void read_code(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition: corefile.c:283
int default_frame_sniffer(const struct frame_unwind *self, struct frame_info *this_frame, void **this_prologue_cache)
Definition: frame-unwind.c:170
#define COMPUNIT_PRODUCER(cust)
Definition: symtab.h:1097
#define gdb_assert(expr)
Definition: gdb_assert.h:33
#define AMD64_NUM_LOWER_BYTE_REGS
Definition: amd64-tdep.c:310
#define X86_XSTATE_MPX_AVX512_MASK
Definition: x86-xstate.h:44
#define min(a, b)
Definition: defs.h:106
void ax_simple(struct agent_expr *x, enum agent_op op)
Definition: ax-general.c:140
static int startswith(const char *string, const char *pattern)
Definition: common-utils.h:75
static struct value * amd64_frame_prev_register(struct frame_info *this_frame, void **this_cache, int regnum)
Definition: amd64-tdep.c:2528
enum register_status regcache_raw_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition: regcache.c:690
const char ** zmmh_register_names
Definition: i386-tdep.h:184
static CORE_ADDR amd64_push_dummy_call(struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr)
Definition: amd64-tdep.c:965
int opcode_len
Definition: amd64-tdep.c:1006
static void amd64_gen_return_address(struct gdbarch *gdbarch, struct agent_expr *ax, struct axs_value *value, CORE_ADDR scope)
Definition: amd64-tdep.c:2560
int num_byte_regs
Definition: i386-tdep.h:100
static void amd64_init_frame_cache(struct amd64_frame_cache *cache)
Definition: amd64-tdep.c:1824
static void initialize_tdesc_amd64_avx512(void)
Definition: amd64-avx512.c:10
int regnum
Definition: aarch64-tdep.c:69
static int amd64_absolute_jmp_p(const struct amd64_insn *details)
Definition: amd64-tdep.c:1398
void read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition: corefile.c:244
void set_gdbarch_insn_is_jump(struct gdbarch *gdbarch, gdbarch_insn_is_jump_ftype insn_is_jump)
Definition: gdbarch.c:4624
int i386_word_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:187
#define I387_FOSEG_REGNUM(tdep)
Definition: i387-tdep.h:59
static CORE_ADDR amd64_frame_align(struct gdbarch *gdbarch, CORE_ADDR sp)
Definition: amd64-tdep.c:2851
ULONGEST get_frame_register_unsigned(struct frame_info *frame, int regnum)
Definition: frame.c:1194
void * xmalloc(YYSIZE_T)
struct symtab * symtab
Definition: symtab.h:1369
int i387_convert_register_p(struct gdbarch *gdbarch, int regnum, struct type *type)
Definition: i387-tdep.c:338
struct ui_file * gdb_stdlog
Definition: main.c:73
#define TYPE_FIELD_BITSIZE(thistype, n)
Definition: gdbtypes.h:1377
static int amd64_sigtramp_frame_sniffer(const struct frame_unwind *self, struct frame_info *this_frame, void **this_cache)
Definition: amd64-tdep.c:2663
static CORE_ADDR amd64_x32_analyze_stack_align(CORE_ADDR pc, CORE_ADDR current_pc, struct amd64_frame_cache *cache)
Definition: amd64-tdep.c:2018
const char ** xmm_avx512_register_names
Definition: i386-tdep.h:187
void set_gdbarch_long_long_bit(struct gdbarch *gdbarch, int long_long_bit)
Definition: gdbarch.c:1534
#define TYPE_FIELD_BITPOS(thistype, n)
Definition: gdbtypes.h:1371
Definition: regdef.h:22
const struct target_desc * target_desc
Definition: gdbarch.h:1566
void i387_collect_xsave(const struct regcache *regcache, int regnum, void *xsave, int gcore)
Definition: i387-tdep.c:1267
Definition: value.c:172
const struct regset amd64_fpregset
Definition: amd64-tdep.c:2889
#define I387_SIZEOF_FXSAVE
Definition: i387-tdep.h:112
CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS]
Definition: amd64-tdep.c:1813
void regcache_raw_write_part(struct regcache *regcache, int regnum, int offset, int len, const gdb_byte *buf)
Definition: regcache.c:1006
const char * i386_pseudo_register_name(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:439
gdb_byte * raw_insn
Definition: amd64-tdep.c:1015
static int amd64_dwarf_reg_to_regnum(struct gdbarch *gdbarch, int reg)
Definition: amd64-tdep.c:246
void throw_exception(struct gdb_exception exception)
int st0_regnum
Definition: i386-tdep.h:69
static int amd64_get_unused_input_int_reg(const struct amd64_insn *details)
Definition: amd64-tdep.c:1135
bfd_byte gdb_byte
Definition: common-types.h:38
static int amd64_epilogue_frame_sniffer(const struct frame_unwind *self, struct frame_info *this_frame, void **this_prologue_cache)
Definition: amd64-tdep.c:2748
static const char * amd64_pseudo_register_name(struct gdbarch *gdbarch, int regnum)
Definition: amd64-tdep.c:332
int ymm16h_regnum
Definition: i386-tdep.h:156
int(* sigtramp_p)(struct frame_info *)
Definition: i386-tdep.h:209
static void amd64_frame_cache_1(struct frame_info *this_frame, struct amd64_frame_cache *cache)
Definition: amd64-tdep.c:2399
static void fixup_displaced_copy(struct gdbarch *gdbarch, struct displaced_step_closure *dsc, CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
Definition: amd64-tdep.c:1326
#define X86_XSTATE_AVX512_MASK
Definition: x86-xstate.h:43
#define TYPE_TARGET_TYPE(thistype)
Definition: gdbtypes.h:1229
#define max(a, b)
Definition: defs.h:109
void set_gdbarch_convert_register_p(struct gdbarch *gdbarch, gdbarch_convert_register_p_ftype convert_register_p)
Definition: gdbarch.c:2423
int frame_relative_level(struct frame_info *fi)
Definition: frame.c:2454
int opcode_offset
Definition: amd64-tdep.c:1010
#define TYPE_CODE(thistype)
Definition: gdbtypes.h:1240
enum register_status regcache_raw_read(struct regcache *regcache, int regnum, gdb_byte *buf)
Definition: regcache.c:637
const int * record_regmap
Definition: i386-tdep.h:233
struct value * frame_unwind_got_register(struct frame_info *frame, int regnum, int new_regnum)
Definition: frame-unwind.c:218
void regcache_cooked_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
Definition: regcache.c:871
void amd64_init_abi(struct gdbarch_info info, struct gdbarch *gdbarch)
Definition: amd64-tdep.c:2937
int target_read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition: target.c:1393
int num_xmm_regs
Definition: i386-tdep.h:122
struct type * builtin_data_ptr
Definition: gdbtypes.h:1533
static void initialize_tdesc_x32_avx512(void)
Definition: x32-avx512.c:10
int i386_stap_is_single_operand(struct gdbarch *gdbarch, const char *s)
Definition: i386-tdep.c:3951
void set_gdbarch_stap_is_single_operand(struct gdbarch *gdbarch, gdbarch_stap_is_single_operand_ftype stap_is_single_operand)
Definition: gdbarch.c:4219
static const char * amd64_k_names[]
Definition: amd64-tdep.c:120
static void amd64_sigtramp_frame_this_id(struct frame_info *this_frame, void **this_cache, struct frame_id *this_id)
Definition: amd64-tdep.c:2635
int offset
Definition: agent.c:65
void regcache_raw_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
Definition: regcache.c:723
int code
Definition: ser-unix.c:684
void get_frame_register(struct frame_info *frame, int regnum, gdb_byte *buf)
Definition: frame.c:1085
#define TYPE_NFIELDS(thistype)
Definition: gdbtypes.h:1241
static struct amd64_frame_cache * amd64_frame_cache(struct frame_info *this_frame, void **this_cache)
Definition: amd64-tdep.c:2468
int eax_regnum
Definition: i386-tdep.h:116
static const int amd64_record_regmap[]
Definition: amd64-tdep.c:2926
CORE_ADDR pc
Definition: symtab.h:1376
struct m32c_reg regs[M32C_MAX_NUM_REGS]
Definition: m32c-tdep.c:105
static void initialize_tdesc_amd64_mpx(void)
Definition: amd64-mpx.c:10
const struct target_desc * tdesc
Definition: i386-tdep.h:193
int i386_ymm_avx512_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:293
void ax_const_l(struct agent_expr *x, LONGEST l)
Definition: ax-general.c:245
const struct regset * fpregset
Definition: i386-tdep.h:242
void regcache_raw_supply(struct regcache *regcache, int regnum, const void *buf)
Definition: regcache.c:1041
int * sc_reg_offset
Definition: i386-tdep.h:215
unsigned long long ULONGEST
Definition: common-types.h:53
static int amd64_insn_is_call(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: amd64-tdep.c:1530
int i387_register_to_value(struct frame_info *frame, int regnum, struct type *type, gdb_byte *to, int *optimizedp, int *unavailablep)
Definition: i387-tdep.c:358
struct symtab_and_line find_pc_sect_line(CORE_ADDR pc, struct obj_section *section, int notcurrent)
Definition: symtab.c:3075
const struct tdesc_feature * tdesc_find_feature(const struct target_desc *target_desc, const char *name)
int modrm_offset
Definition: amd64-tdep.c:1012
static void amd64_relocate_instruction(struct gdbarch *gdbarch, CORE_ADDR *to, CORE_ADDR oldloc)
Definition: amd64-tdep.c:1707
void set_gdbarch_long_double_bit(struct gdbarch *gdbarch, int long_double_bit)
Definition: gdbarch.c:1667
struct type * value_type(const struct value *value)
Definition: value.c:1021
void set_gdbarch_long_bit(struct gdbarch *gdbarch, int long_bit)
Definition: gdbarch.c:1517
void set_gdbarch_return_value(struct gdbarch *gdbarch, gdbarch_return_value_ftype return_value)
Definition: gdbarch.c:2556
const struct bfd_arch_info * gdbarch_bfd_arch_info(struct gdbarch *gdbarch)
Definition: gdbarch.c:1411
void regcache_raw_collect(const struct regcache *regcache, int regnum, void *buf)
Definition: regcache.c:1071
#define AMD64_NUM_REGS
Definition: amd64-tdep.h:85
void amd64_collect_xsave(const struct regcache *regcache, int regnum, void *xsave, int gcore)
Definition: amd64-tdep.c:3245
static void amd64_pseudo_register_write(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buf)
Definition: amd64-tdep.c:413
CORE_ADDR saved_sp
Definition: amd64-tdep.c:1814
static int amd64_absolute_call_p(const struct amd64_insn *details)
Definition: amd64-tdep.c:1435
gdb_byte * value_contents_raw(struct value *value)
Definition: value.c:1084
#define TYPE_LENGTH(thistype)
Definition: gdbtypes.h:1237
int int * to
Definition: varobj.h:282
void set_gdbarch_ptr_bit(struct gdbarch *gdbarch, int ptr_bit)
Definition: gdbarch.c:1700
void set_gdbarch_push_dummy_call(struct gdbarch *gdbarch, gdbarch_push_dummy_call_ftype push_dummy_call)
Definition: gdbarch.c:2216
#define COMPUNIT_EPILOGUE_UNWIND_VALID(cust)
Definition: symtab.h:1102
static const int amd64_arch_regmap[16]
Definition: amd64-tdep.c:266
ULONGEST read_memory_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition: corefile.c:321
static CORE_ADDR amd64_frame_base_address(struct frame_info *this_frame, void **this_cache)
Definition: amd64-tdep.c:2704
void set_gdbarch_insn_is_call(struct gdbarch *gdbarch, gdbarch_insn_is_call_ftype insn_is_call)
Definition: gdbarch.c:4590
LONGEST extract_signed_integer(const gdb_byte *, int, enum bfd_endian)
Definition: findvar.c:49
void write_memory(CORE_ADDR memaddr, const bfd_byte *myaddr, ssize_t len)
Definition: corefile.c:389
void set_gdbarch_skip_prologue(struct gdbarch *gdbarch, gdbarch_skip_prologue_ftype skip_prologue)
Definition: gdbarch.c:2590
const char ** k_register_names
Definition: i386-tdep.h:181
int k0_regnum
Definition: i386-tdep.h:90
void i386_pseudo_register_read_into_value(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, struct value *result_value)
Definition: i386-tdep.c:3238
static int amd64_stack_frame_destroyed_p(struct gdbarch *gdbarch, CORE_ADDR pc)
Definition: amd64-tdep.c:2729
void i387_supply_xsave(struct regcache *regcache, int regnum, const void *xsave)
Definition: i387-tdep.c:894
#define I387_NUM_REGS
Definition: i387-tdep.h:30
enum axs_lvalue_kind kind
Definition: ax-gdb.h:77
const struct target_desc * amd64_target_description(uint64_t xcr0)
Definition: amd64-tdep.c:3127
enum bfd_endian byte_order
Definition: gdbarch.c:128
void set_gdbarch_pc_regnum(struct gdbarch *gdbarch, int pc_regnum)
Definition: gdbarch.c:2008
static int amd64_classify_insn_at(struct gdbarch *gdbarch, CORE_ADDR addr, int(*pred)(const struct amd64_insn *))
Definition: amd64-tdep.c:1509
static struct value * amd64_pseudo_register_read_value(struct gdbarch *gdbarch, struct regcache *regcache, int regnum)
Definition: amd64-tdep.c:352
int tdesc_has_registers(const struct target_desc *target_desc)
CORE_ADDR get_frame_func(struct frame_info *this_frame)
Definition: frame.c:920
struct target_desc * tdesc_amd64_avx512
Definition: amd64-avx512.c:8
int bnd0r_regnum
Definition: i386-tdep.h:163
CORE_ADDR sp_offset
Definition: amd64-tdep.c:1809
static gdb_byte * amd64_skip_prefixes(gdb_byte *insn)
Definition: amd64-tdep.c:1099
struct gdbarch * get_frame_arch(struct frame_info *this_frame)
Definition: frame.c:2535
long long LONGEST
Definition: common-types.h:52
int gdb_buffered_insn_length(struct gdbarch *gdbarch, const gdb_byte *insn, int max_len, CORE_ADDR addr)
Definition: disasm.c:525
void i386_pseudo_register_write(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buf)
Definition: i386-tdep.c:3448
void regcache_cooked_write(struct regcache *regcache, int regnum, const gdb_byte *buf)
Definition: regcache.c:930
int zmm0h_regnum
Definition: i386-tdep.h:178
int num_dword_regs
Definition: i386-tdep.h:112
static struct amd64_frame_cache * amd64_epilogue_frame_cache(struct frame_info *this_frame, void **this_cache)
Definition: amd64-tdep.c:2760
void regcache_raw_write(struct regcache *regcache, int regnum, const gdb_byte *buf)
Definition: regcache.c:885
const ULONGEST const LONGEST len
Definition: target.h:309
struct amd64_insn insn_details
Definition: amd64-tdep.c:1026
static const char * amd64_zmmh_names[]
Definition: amd64-tdep.c:126
#define X86_XSTATE_ALL_MASK
Definition: x86-xstate.h:46
static void amd64_epilogue_frame_this_id(struct frame_info *this_frame, void **this_cache, struct frame_id *this_id)
Definition: amd64-tdep.c:2815
static const struct frame_unwind amd64_frame_unwind
Definition: amd64-tdep.c:2547
int bndcfgu_regnum
Definition: i386-tdep.h:171