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/tmp/gdb-7.10/gdb/xtensa-tdep.c
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1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
2 
3  Copyright (C) 2003-2015 Free Software Foundation, Inc.
4 
5  This file is part of GDB.
6 
7  This program is free software; you can redistribute it and/or modify
8  it under the terms of the GNU General Public License as published by
9  the Free Software Foundation; either version 3 of the License, or
10  (at your option) any later version.
11 
12  This program is distributed in the hope that it will be useful,
13  but WITHOUT ANY WARRANTY; without even the implied warranty of
14  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  GNU General Public License for more details.
16 
17  You should have received a copy of the GNU General Public License
18  along with this program. If not, see <http://www.gnu.org/licenses/>. */
19 
20 #include "defs.h"
21 #include "frame.h"
22 #include "solib-svr4.h"
23 #include "symtab.h"
24 #include "symfile.h"
25 #include "objfiles.h"
26 #include "gdbtypes.h"
27 #include "gdbcore.h"
28 #include "value.h"
29 #include "dis-asm.h"
30 #include "inferior.h"
31 #include "floatformat.h"
32 #include "regcache.h"
33 #include "reggroups.h"
34 #include "regset.h"
35 
36 #include "dummy-frame.h"
37 #include "dwarf2.h"
38 #include "dwarf2-frame.h"
39 #include "dwarf2loc.h"
40 #include "frame-base.h"
41 #include "frame-unwind.h"
42 
43 #include "arch-utils.h"
44 #include "gdbarch.h"
45 #include "remote.h"
46 #include "serial.h"
47 
48 #include "command.h"
49 #include "gdbcmd.h"
50 
51 #include "xtensa-isa.h"
52 #include "xtensa-tdep.h"
53 #include "xtensa-config.h"
54 
55 
56 static unsigned int xtensa_debug_level = 0;
57 
58 #define DEBUGWARN(args...) \
59  if (xtensa_debug_level > 0) \
60  fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
61 
62 #define DEBUGINFO(args...) \
63  if (xtensa_debug_level > 1) \
64  fprintf_unfiltered (gdb_stdlog, "(info ) " args)
65 
66 #define DEBUGTRACE(args...) \
67  if (xtensa_debug_level > 2) \
68  fprintf_unfiltered (gdb_stdlog, "(trace) " args)
69 
70 #define DEBUGVERB(args...) \
71  if (xtensa_debug_level > 3) \
72  fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
73 
74 
75 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
76 #define SP_ALIGNMENT 16
77 
78 
79 /* On Windowed ABI, we use a6 through a11 for passing arguments
80  to a function called by GDB because CALL4 is used. */
81 #define ARGS_NUM_REGS 6
82 #define REGISTER_SIZE 4
83 
84 
85 /* Extract the call size from the return address or PS register. */
86 #define PS_CALLINC_SHIFT 16
87 #define PS_CALLINC_MASK 0x00030000
88 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
89 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
90 
91 /* On TX, hardware can be configured without Exception Option.
92  There is no PS register in this case. Inside XT-GDB, let us treat
93  it as a virtual read-only register always holding the same value. */
94 #define TX_PS 0x20
95 
96 /* ABI-independent macros. */
97 #define ARG_NOF(gdbarch) \
98  (gdbarch_tdep (gdbarch)->call_abi \
99  == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
100 #define ARG_1ST(gdbarch) \
101  (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
102  ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
103  : (gdbarch_tdep (gdbarch)->a0_base + 6))
104 
105 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
106  indicates that the instruction is an ENTRY instruction. */
107 
108 #define XTENSA_IS_ENTRY(gdbarch, op1) \
109  ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
110  ? ((op1) == 0x6c) : ((op1) == 0x36))
111 
112 #define XTENSA_ENTRY_LENGTH 3
113 
114 /* windowing_enabled() returns true, if windowing is enabled.
115  WOE must be set to 1; EXCM to 0.
116  Note: We assume that EXCM is always 0 for XEA1. */
117 
118 #define PS_WOE (1<<18)
119 #define PS_EXC (1<<4)
120 
121 static int
122 windowing_enabled (struct gdbarch *gdbarch, unsigned int ps)
123 {
124  /* If we know CALL0 ABI is set explicitly, say it is Call0. */
125  if (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only)
126  return 0;
127 
128  return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0);
129 }
130 
131 /* Convert a live A-register number to the corresponding AR-register
132  number. */
133 static int
134 arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb)
135 {
136  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
137  int arreg;
138 
139  arreg = a_regnum - tdep->a0_base;
140  arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT;
141  arreg &= tdep->num_aregs - 1;
142 
143  return arreg + tdep->ar_base;
144 }
145 
146 /* Convert a live AR-register number to the corresponding A-register order
147  number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
148 static int
149 areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb)
150 {
151  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
152  int areg;
153 
154  areg = ar_regnum - tdep->ar_base;
155  if (areg < 0 || areg >= tdep->num_aregs)
156  return -1;
157  areg = (areg - wb * 4) & (tdep->num_aregs - 1);
158  return (areg > 15) ? -1 : areg;
159 }
160 
161 /* Read Xtensa register directly from the hardware. */
162 static unsigned long
164 {
165  ULONGEST value;
166 
168  return (unsigned long) value;
169 }
170 
171 /* Write Xtensa register directly to the hardware. */
172 static void
174 {
176 }
177 
178 /* Return the window size of the previous call to the function from which we
179  have just returned.
180 
181  This function is used to extract the return value after a called function
182  has returned to the caller. On Xtensa, the register that holds the return
183  value (from the perspective of the caller) depends on what call
184  instruction was used. For now, we are assuming that the call instruction
185  precedes the current address, so we simply analyze the call instruction.
186  If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
187  method to call the inferior function. */
188 
189 static int
190 extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc)
191 {
192  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
193  int winsize = 4;
194  int insn;
195  gdb_byte buf[4];
196 
197  DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc);
198 
199  /* Read the previous instruction (should be a call[x]{4|8|12}. */
200  read_memory (pc-3, buf, 3);
201  insn = extract_unsigned_integer (buf, 3, byte_order);
202 
203  /* Decode call instruction:
204  Little Endian
205  call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
206  callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
207  Big Endian
208  call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
209  callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
210 
211  if (byte_order == BFD_ENDIAN_LITTLE)
212  {
213  if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
214  winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */
215  }
216  else
217  {
218  if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
219  winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */
220  }
221  return winsize;
222 }
223 
224 
225 /* REGISTER INFORMATION */
226 
227 /* Find register by name. */
228 static int
229 xtensa_find_register_by_name (struct gdbarch *gdbarch, char *name)
230 {
231  int i;
232 
233  for (i = 0; i < gdbarch_num_regs (gdbarch)
234  + gdbarch_num_pseudo_regs (gdbarch);
235  i++)
236 
237  if (strcasecmp (gdbarch_tdep (gdbarch)->regmap[i].name, name) == 0)
238  return i;
239 
240  return -1;
241 }
242 
243 /* Returns the name of a register. */
244 static const char *
245 xtensa_register_name (struct gdbarch *gdbarch, int regnum)
246 {
247  /* Return the name stored in the register map. */
248  if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
249  + gdbarch_num_pseudo_regs (gdbarch))
250  return gdbarch_tdep (gdbarch)->regmap[regnum].name;
251 
252  internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum);
253  return 0;
254 }
255 
256 /* Return the type of a register. Create a new type, if necessary. */
257 
258 static struct type *
259 xtensa_register_type (struct gdbarch *gdbarch, int regnum)
260 {
261  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
262 
263  /* Return signed integer for ARx and Ax registers. */
264  if ((regnum >= tdep->ar_base
265  && regnum < tdep->ar_base + tdep->num_aregs)
266  || (regnum >= tdep->a0_base
267  && regnum < tdep->a0_base + 16))
268  return builtin_type (gdbarch)->builtin_int;
269 
270  if (regnum == gdbarch_pc_regnum (gdbarch)
271  || regnum == tdep->a0_base + 1)
272  return builtin_type (gdbarch)->builtin_data_ptr;
273 
274  /* Return the stored type for all other registers. */
275  else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
276  + gdbarch_num_pseudo_regs (gdbarch))
277  {
278  xtensa_register_t* reg = &tdep->regmap[regnum];
279 
280  /* Set ctype for this register (only the first time). */
281 
282  if (reg->ctype == 0)
283  {
284  struct ctype_cache *tp;
285  int size = reg->byte_size;
286 
287  /* We always use the memory representation,
288  even if the register width is smaller. */
289  switch (size)
290  {
291  case 1:
292  reg->ctype = builtin_type (gdbarch)->builtin_uint8;
293  break;
294 
295  case 2:
296  reg->ctype = builtin_type (gdbarch)->builtin_uint16;
297  break;
298 
299  case 4:
300  reg->ctype = builtin_type (gdbarch)->builtin_uint32;
301  break;
302 
303  case 8:
304  reg->ctype = builtin_type (gdbarch)->builtin_uint64;
305  break;
306 
307  case 16:
308  reg->ctype = builtin_type (gdbarch)->builtin_uint128;
309  break;
310 
311  default:
312  for (tp = tdep->type_entries; tp != NULL; tp = tp->next)
313  if (tp->size == size)
314  break;
315 
316  if (tp == NULL)
317  {
318  char *name = xstrprintf ("int%d", size * 8);
319  tp = xmalloc (sizeof (struct ctype_cache));
320  tp->next = tdep->type_entries;
321  tdep->type_entries = tp;
322  tp->size = size;
323  tp->virtual_type
324  = arch_integer_type (gdbarch, size * 8, 1, name);
325  xfree (name);
326  }
327 
328  reg->ctype = tp->virtual_type;
329  }
330  }
331  return reg->ctype;
332  }
333 
334  internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum);
335  return 0;
336 }
337 
338 
339 /* Return the 'local' register number for stubs, dwarf2, etc.
340  The debugging information enumerates registers starting from 0 for A0
341  to n for An. So, we only have to add the base number for A0. */
342 
343 static int
344 xtensa_reg_to_regnum (struct gdbarch *gdbarch, int regnum)
345 {
346  int i;
347 
348  if (regnum >= 0 && regnum < 16)
349  return gdbarch_tdep (gdbarch)->a0_base + regnum;
350 
351  for (i = 0;
352  i < gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
353  i++)
354  if (regnum == gdbarch_tdep (gdbarch)->regmap[i].target_number)
355  return i;
356 
357  internal_error (__FILE__, __LINE__,
358  _("invalid dwarf/stabs register number %d"), regnum);
359  return 0;
360 }
361 
362 
363 /* Write the bits of a masked register to the various registers.
364  Only the masked areas of these registers are modified; the other
365  fields are untouched. The size of masked registers is always less
366  than or equal to 32 bits. */
367 
368 static void
371 {
372  unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
373  const xtensa_mask_t *mask = reg->mask;
374 
375  int shift = 0; /* Shift for next mask (mod 32). */
376  int start, size; /* Start bit and size of current mask. */
377 
378  unsigned int *ptr = value;
379  unsigned int regval, m, mem = 0;
380 
381  int bytesize = reg->byte_size;
382  int bitsize = bytesize * 8;
383  int i, r;
384 
385  DEBUGTRACE ("xtensa_register_write_masked ()\n");
386 
387  /* Copy the masked register to host byte-order. */
388  if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
389  for (i = 0; i < bytesize; i++)
390  {
391  mem >>= 8;
392  mem |= (buffer[bytesize - i - 1] << 24);
393  if ((i & 3) == 3)
394  *ptr++ = mem;
395  }
396  else
397  for (i = 0; i < bytesize; i++)
398  {
399  mem >>= 8;
400  mem |= (buffer[i] << 24);
401  if ((i & 3) == 3)
402  *ptr++ = mem;
403  }
404 
405  /* We might have to shift the final value:
406  bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
407  bytesize & 3 == x -> shift (4-x) * 8. */
408 
409  *ptr = mem >> (((0 - bytesize) & 3) * 8);
410  ptr = value;
411  mem = *ptr;
412 
413  /* Write the bits to the masked areas of the other registers. */
414  for (i = 0; i < mask->count; i++)
415  {
416  start = mask->mask[i].bit_start;
417  size = mask->mask[i].bit_size;
418  regval = mem >> shift;
419 
420  if ((shift += size) > bitsize)
421  error (_("size of all masks is larger than the register"));
422 
423  if (shift >= 32)
424  {
425  mem = *(++ptr);
426  shift -= 32;
427  bitsize -= 32;
428 
429  if (shift > 0)
430  regval |= mem << (size - shift);
431  }
432 
433  /* Make sure we have a valid register. */
434  r = mask->mask[i].reg_num;
435  if (r >= 0 && size > 0)
436  {
437  /* Don't overwrite the unmasked areas. */
438  ULONGEST old_val;
439  regcache_cooked_read_unsigned (regcache, r, &old_val);
440  m = 0xffffffff >> (32 - size) << start;
441  regval <<= start;
442  regval = (regval & m) | (old_val & ~m);
443  regcache_cooked_write_unsigned (regcache, r, regval);
444  }
445  }
446 }
447 
448 
449 /* Read a tie state or mapped registers. Read the masked areas
450  of the registers and assemble them into a single value. */
451 
452 static enum register_status
455 {
456  unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
457  const xtensa_mask_t *mask = reg->mask;
458 
459  int shift = 0;
460  int start, size;
461 
462  unsigned int *ptr = value;
463  unsigned int regval, mem = 0;
464 
465  int bytesize = reg->byte_size;
466  int bitsize = bytesize * 8;
467  int i;
468 
469  DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
470  reg->name == 0 ? "" : reg->name);
471 
472  /* Assemble the register from the masked areas of other registers. */
473  for (i = 0; i < mask->count; i++)
474  {
475  int r = mask->mask[i].reg_num;
476  if (r >= 0)
477  {
478  enum register_status status;
479  ULONGEST val;
480 
481  status = regcache_cooked_read_unsigned (regcache, r, &val);
482  if (status != REG_VALID)
483  return status;
484  regval = (unsigned int) val;
485  }
486  else
487  regval = 0;
488 
489  start = mask->mask[i].bit_start;
490  size = mask->mask[i].bit_size;
491 
492  regval >>= start;
493 
494  if (size < 32)
495  regval &= (0xffffffff >> (32 - size));
496 
497  mem |= regval << shift;
498 
499  if ((shift += size) > bitsize)
500  error (_("size of all masks is larger than the register"));
501 
502  if (shift >= 32)
503  {
504  *ptr++ = mem;
505  bitsize -= 32;
506  shift -= 32;
507 
508  if (shift == 0)
509  mem = 0;
510  else
511  mem = regval >> (size - shift);
512  }
513  }
514 
515  if (shift > 0)
516  *ptr = mem;
517 
518  /* Copy value to target byte order. */
519  ptr = value;
520  mem = *ptr;
521 
522  if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
523  for (i = 0; i < bytesize; i++)
524  {
525  if ((i & 3) == 0)
526  mem = *ptr++;
527  buffer[bytesize - i - 1] = mem & 0xff;
528  mem >>= 8;
529  }
530  else
531  for (i = 0; i < bytesize; i++)
532  {
533  if ((i & 3) == 0)
534  mem = *ptr++;
535  buffer[i] = mem & 0xff;
536  mem >>= 8;
537  }
538 
539  return REG_VALID;
540 }
541 
542 
543 /* Read pseudo registers. */
544 
545 static enum register_status
546 xtensa_pseudo_register_read (struct gdbarch *gdbarch,
547  struct regcache *regcache,
548  int regnum,
549  gdb_byte *buffer)
550 {
551  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
552 
553  DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
554  regnum, xtensa_register_name (gdbarch, regnum));
555 
556  /* Read aliases a0..a15, if this is a Windowed ABI. */
557  if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
558  && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
559  && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
560  {
561  gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
562  enum register_status status;
563 
564  status = regcache_raw_read (regcache,
565  gdbarch_tdep (gdbarch)->wb_regnum,
566  buf);
567  if (status != REG_VALID)
568  return status;
569  regnum = arreg_number (gdbarch, regnum,
570  extract_unsigned_integer (buf, 4, byte_order));
571  }
572 
573  /* We can always read non-pseudo registers. */
574  if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
575  return regcache_raw_read (regcache, regnum, buffer);
576 
577  /* We have to find out how to deal with priveleged registers.
578  Let's treat them as pseudo-registers, but we cannot read/write them. */
579 
580  else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
581  {
582  buffer[0] = (gdb_byte)0;
583  buffer[1] = (gdb_byte)0;
584  buffer[2] = (gdb_byte)0;
585  buffer[3] = (gdb_byte)0;
586  return REG_VALID;
587  }
588  /* Pseudo registers. */
589  else if (regnum >= 0
590  && regnum < gdbarch_num_regs (gdbarch)
591  + gdbarch_num_pseudo_regs (gdbarch))
592  {
595  int flags = gdbarch_tdep (gdbarch)->target_flags;
596 
597  /* We cannot read Unknown or Unmapped registers. */
598  if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
599  {
600  if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
601  {
602  warning (_("cannot read register %s"),
603  xtensa_register_name (gdbarch, regnum));
604  return REG_VALID;
605  }
606  }
607 
608  /* Some targets cannot read TIE register files. */
609  else if (type == xtRegisterTypeTieRegfile)
610  {
611  /* Use 'fetch' to get register? */
612  if (flags & xtTargetFlagsUseFetchStore)
613  {
614  warning (_("cannot read register"));
615  return REG_VALID;
616  }
617 
618  /* On some targets (esp. simulators), we can always read the reg. */
619  else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
620  {
621  warning (_("cannot read register"));
622  return REG_VALID;
623  }
624  }
625 
626  /* We can always read mapped registers. */
627  else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
628  return xtensa_register_read_masked (regcache, reg, buffer);
629 
630  /* Assume that we can read the register. */
631  return regcache_raw_read (regcache, regnum, buffer);
632  }
633  else
634  internal_error (__FILE__, __LINE__,
635  _("invalid register number %d"), regnum);
636 }
637 
638 
639 /* Write pseudo registers. */
640 
641 static void
642 xtensa_pseudo_register_write (struct gdbarch *gdbarch,
643  struct regcache *regcache,
644  int regnum,
645  const gdb_byte *buffer)
646 {
647  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
648 
649  DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
650  regnum, xtensa_register_name (gdbarch, regnum));
651 
652  /* Renumber register, if aliase a0..a15 on Windowed ABI. */
653  if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
654  && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
655  && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
656  {
657  gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
658 
659  regcache_raw_read (regcache,
660  gdbarch_tdep (gdbarch)->wb_regnum, buf);
661  regnum = arreg_number (gdbarch, regnum,
662  extract_unsigned_integer (buf, 4, byte_order));
663  }
664 
665  /* We can always write 'core' registers.
666  Note: We might have converted Ax->ARy. */
667  if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
668  regcache_raw_write (regcache, regnum, buffer);
669 
670  /* We have to find out how to deal with priveleged registers.
671  Let's treat them as pseudo-registers, but we cannot read/write them. */
672 
673  else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
674  {
675  return;
676  }
677  /* Pseudo registers. */
678  else if (regnum >= 0
679  && regnum < gdbarch_num_regs (gdbarch)
680  + gdbarch_num_pseudo_regs (gdbarch))
681  {
684  int flags = gdbarch_tdep (gdbarch)->target_flags;
685 
686  /* On most targets, we cannot write registers
687  of type "Unknown" or "Unmapped". */
688  if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
689  {
690  if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
691  {
692  warning (_("cannot write register %s"),
693  xtensa_register_name (gdbarch, regnum));
694  return;
695  }
696  }
697 
698  /* Some targets cannot read TIE register files. */
699  else if (type == xtRegisterTypeTieRegfile)
700  {
701  /* Use 'store' to get register? */
702  if (flags & xtTargetFlagsUseFetchStore)
703  {
704  warning (_("cannot write register"));
705  return;
706  }
707 
708  /* On some targets (esp. simulators), we can always write
709  the register. */
710  else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
711  {
712  warning (_("cannot write register"));
713  return;
714  }
715  }
716 
717  /* We can always write mapped registers. */
718  else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
719  {
720  xtensa_register_write_masked (regcache, reg, buffer);
721  return;
722  }
723 
724  /* Assume that we can write the register. */
725  regcache_raw_write (regcache, regnum, buffer);
726  }
727  else
728  internal_error (__FILE__, __LINE__,
729  _("invalid register number %d"), regnum);
730 }
731 
735 static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR];
736 
737 static void
739 {
740  int i;
741  char cpname[] = "cp0";
742 
743  xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP);
744  xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP);
745  xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP);
746 
747  for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
748  {
749  cpname[2] = '0' + i;
750  xtensa_cp[i] = reggroup_new (cpname, USER_REGGROUP);
751  }
752 }
753 
754 static void
755 xtensa_add_reggroups (struct gdbarch *gdbarch)
756 {
757  int i;
758 
759  /* Predefined groups. */
760  reggroup_add (gdbarch, all_reggroup);
761  reggroup_add (gdbarch, save_reggroup);
762  reggroup_add (gdbarch, restore_reggroup);
763  reggroup_add (gdbarch, system_reggroup);
764  reggroup_add (gdbarch, vector_reggroup);
765  reggroup_add (gdbarch, general_reggroup);
766  reggroup_add (gdbarch, float_reggroup);
767 
768  /* Xtensa-specific groups. */
769  reggroup_add (gdbarch, xtensa_ar_reggroup);
770  reggroup_add (gdbarch, xtensa_user_reggroup);
771  reggroup_add (gdbarch, xtensa_vectra_reggroup);
772 
773  for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
774  reggroup_add (gdbarch, xtensa_cp[i]);
775 }
776 
777 static int
779 {
780  int i;
781 
782  for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
783  if (group == xtensa_cp[i])
784  return i;
785 
786  return -1;
787 }
788 
789 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
790  | XTENSA_REGISTER_FLAGS_WRITABLE \
791  | XTENSA_REGISTER_FLAGS_VOLATILE)
792 
793 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
794  | XTENSA_REGISTER_FLAGS_WRITABLE)
795 
796 static int
797 xtensa_register_reggroup_p (struct gdbarch *gdbarch,
798  int regnum,
799  struct reggroup *group)
800 {
803  xtensa_register_group_t rg = reg->group;
804  int cp_number;
805 
806  if (group == save_reggroup)
807  /* Every single register should be included into the list of registers
808  to be watched for changes while using -data-list-changed-registers. */
809  return 1;
810 
811  /* First, skip registers that are not visible to this target
812  (unknown and unmapped registers when not using ISS). */
813 
814  if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
815  return 0;
816  if (group == all_reggroup)
817  return 1;
818  if (group == xtensa_ar_reggroup)
819  return rg & xtRegisterGroupAddrReg;
820  if (group == xtensa_user_reggroup)
821  return rg & xtRegisterGroupUser;
822  if (group == float_reggroup)
823  return rg & xtRegisterGroupFloat;
824  if (group == general_reggroup)
825  return rg & xtRegisterGroupGeneral;
826  if (group == system_reggroup)
827  return rg & xtRegisterGroupState;
828  if (group == vector_reggroup || group == xtensa_vectra_reggroup)
829  return rg & xtRegisterGroupVectra;
830  if (group == restore_reggroup)
831  return (regnum < gdbarch_num_regs (gdbarch)
832  && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
833  cp_number = xtensa_coprocessor_register_group (group);
834  if (cp_number >= 0)
835  return rg & (xtRegisterGroupCP0 << cp_number);
836  else
837  return 1;
838 }
839 
840 
841 /* Supply register REGNUM from the buffer specified by GREGS and LEN
842  in the general-purpose register set REGSET to register cache
843  REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
844 
845 static void
847  struct regcache *rc,
848  int regnum,
849  const void *gregs,
850  size_t len)
851 {
852  const xtensa_elf_gregset_t *regs = gregs;
853  struct gdbarch *gdbarch = get_regcache_arch (rc);
854  int i;
855 
856  DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum);
857 
858  if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1)
859  regcache_raw_supply (rc, gdbarch_pc_regnum (gdbarch), (char *) &regs->pc);
860  if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1)
861  regcache_raw_supply (rc, gdbarch_ps_regnum (gdbarch), (char *) &regs->ps);
862  if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1)
863  regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->wb_regnum,
864  (char *) &regs->windowbase);
865  if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1)
866  regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ws_regnum,
867  (char *) &regs->windowstart);
868  if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1)
869  regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lbeg_regnum,
870  (char *) &regs->lbeg);
871  if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1)
872  regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lend_regnum,
873  (char *) &regs->lend);
874  if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1)
875  regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lcount_regnum,
876  (char *) &regs->lcount);
877  if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1)
878  regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->sar_regnum,
879  (char *) &regs->sar);
880  if (regnum >=gdbarch_tdep (gdbarch)->ar_base
881  && regnum < gdbarch_tdep (gdbarch)->ar_base
882  + gdbarch_tdep (gdbarch)->num_aregs)
883  regcache_raw_supply (rc, regnum,
884  (char *) &regs->ar[regnum - gdbarch_tdep
885  (gdbarch)->ar_base]);
886  else if (regnum == -1)
887  {
888  for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i)
889  regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ar_base + i,
890  (char *) &regs->ar[i]);
891  }
892 }
893 
894 
895 /* Xtensa register set. */
896 
897 static struct regset
898 xtensa_gregset =
899 {
900  NULL,
902 };
903 
904 
905 /* Iterate over supported core file register note sections. */
906 
907 static void
908 xtensa_iterate_over_regset_sections (struct gdbarch *gdbarch,
910  void *cb_data,
911  const struct regcache *regcache)
912 {
913  DEBUGTRACE ("xtensa_iterate_over_regset_sections\n");
914 
915  cb (".reg", sizeof (xtensa_elf_gregset_t), &xtensa_gregset,
916  NULL, cb_data);
917 }
918 
919 
920 /* Handling frames. */
921 
922 /* Number of registers to save in case of Windowed ABI. */
923 #define XTENSA_NUM_SAVED_AREGS 12
924 
925 /* Frame cache part for Windowed ABI. */
927 {
928  int wb; /* WINDOWBASE of the previous frame. */
929  int callsize; /* Call size of this frame. */
930  int ws; /* WINDOWSTART of the previous frame. It keeps track of
931  life windows only. If there is no bit set for the
932  window, that means it had been already spilled
933  because of window overflow. */
934 
935  /* Addresses of spilled A-registers.
936  AREGS[i] == -1, if corresponding AR is alive. */
939 
940 /* Call0 ABI Definitions. */
941 
942 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue
943  analysis. */
944 #define C0_NREGS 16 /* Number of A-registers to track. */
945 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
946 #define C0_SP 1 /* Register used as SP. */
947 #define C0_FP 15 /* Register used as FP. */
948 #define C0_RA 0 /* Register used as return address. */
949 #define C0_ARGS 2 /* Register used as first arg/retval. */
950 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
951 
952 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
953  A-register where the current content of the reg came from (in terms
954  of an original reg and a constant). Negative values of c0_rt[n].fp_reg
955  mean that the orignal content of the register was saved to the stack.
956  c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
957  know where SP will end up until the entire prologue has been analyzed. */
958 
959 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
960 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
961 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
962 
963 extern xtensa_isa xtensa_default_isa;
964 
965 typedef struct xtensa_c0reg
966 {
967  int fr_reg; /* original register from which register content
968  is derived, or C0_CONST, or C0_INEXP. */
969  int fr_ofs; /* constant offset from reg, or immediate value. */
970  int to_stk; /* offset from original SP to register (4-byte aligned),
971  or C0_NOSTK if register has not been saved. */
973 
974 /* Frame cache part for Call0 ABI. */
976 {
977  int c0_frmsz; /* Stack frame size. */
978  int c0_hasfp; /* Current frame uses frame pointer. */
979  int fp_regnum; /* A-register used as FP. */
980  int c0_fp; /* Actual value of frame pointer. */
981  int c0_fpalign; /* Dinamic adjustment for the stack
982  pointer. It's an AND mask. Zero,
983  if alignment was not adjusted. */
984  int c0_old_sp; /* In case of dynamic adjustment, it is
985  a register holding unaligned sp.
986  C0_INEXP, when undefined. */
987  int c0_sp_ofs; /* If "c0_old_sp" was spilled it's a
988  stack offset. C0_NOSTK otherwise. */
989 
990  xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
992 
993 typedef struct xtensa_frame_cache
994 {
995  CORE_ADDR base; /* Stack pointer of this frame. */
996  CORE_ADDR pc; /* PC of this frame at the function entry point. */
997  CORE_ADDR ra; /* The raw return address of this frame. */
998  CORE_ADDR ps; /* The PS register of the previous (older) frame. */
999  CORE_ADDR prev_sp; /* Stack Pointer of the previous (older) frame. */
1000  int call0; /* It's a call0 framework (else windowed). */
1001  union
1002  {
1003  xtensa_windowed_frame_cache_t wd; /* call0 == false. */
1004  xtensa_call0_frame_cache_t c0; /* call0 == true. */
1005  };
1007 
1008 
1009 static struct xtensa_frame_cache *
1011 {
1012  xtensa_frame_cache_t *cache;
1013  int i;
1014 
1015  DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
1016 
1018 
1019  cache->base = 0;
1020  cache->pc = 0;
1021  cache->ra = 0;
1022  cache->ps = 0;
1023  cache->prev_sp = 0;
1024  cache->call0 = !windowed;
1025  if (cache->call0)
1026  {
1027  cache->c0.c0_frmsz = -1;
1028  cache->c0.c0_hasfp = 0;
1029  cache->c0.fp_regnum = -1;
1030  cache->c0.c0_fp = -1;
1031  cache->c0.c0_fpalign = 0;
1032  cache->c0.c0_old_sp = C0_INEXP;
1033  cache->c0.c0_sp_ofs = C0_NOSTK;
1034 
1035  for (i = 0; i < C0_NREGS; i++)
1036  {
1037  cache->c0.c0_rt[i].fr_reg = i;
1038  cache->c0.c0_rt[i].fr_ofs = 0;
1039  cache->c0.c0_rt[i].to_stk = C0_NOSTK;
1040  }
1041  }
1042  else
1043  {
1044  cache->wd.wb = 0;
1045  cache->wd.ws = 0;
1046  cache->wd.callsize = -1;
1047 
1048  for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
1049  cache->wd.aregs[i] = -1;
1050  }
1051  return cache;
1052 }
1053 
1054 
1055 static CORE_ADDR
1056 xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
1057 {
1058  return address & ~15;
1059 }
1060 
1061 
1062 static CORE_ADDR
1063 xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1064 {
1065  gdb_byte buf[8];
1066  CORE_ADDR pc;
1067 
1068  DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1069  host_address_to_string (next_frame));
1070 
1071  frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1072  pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1073 
1074  DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc);
1075 
1076  return pc;
1077 }
1078 
1079 
1080 static struct frame_id
1081 xtensa_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1082 {
1083  CORE_ADDR pc, fp;
1084 
1085  /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1086 
1087  pc = get_frame_pc (this_frame);
1089  (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1090 
1091  /* Make dummy frame ID unique by adding a constant. */
1092  return frame_id_build (fp + SP_ALIGNMENT, pc);
1093 }
1094 
1095 /* Returns true, if instruction to execute next is unique to Xtensa Window
1096  Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */
1097 
1098 static int
1099 xtensa_window_interrupt_insn (struct gdbarch *gdbarch, CORE_ADDR pc)
1100 {
1101  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1102  unsigned int insn = read_memory_integer (pc, 4, byte_order);
1103  unsigned int code;
1104 
1105  if (byte_order == BFD_ENDIAN_BIG)
1106  {
1107  /* Check, if this is L32E or S32E. */
1108  code = insn & 0xf000ff00;
1109  if ((code == 0x00009000) || (code == 0x00009400))
1110  return 1;
1111  /* Check, if this is RFWU or RFWO. */
1112  code = insn & 0xffffff00;
1113  return ((code == 0x00430000) || (code == 0x00530000));
1114  }
1115  else
1116  {
1117  /* Check, if this is L32E or S32E. */
1118  code = insn & 0x00ff000f;
1119  if ((code == 0x090000) || (code == 0x490000))
1120  return 1;
1121  /* Check, if this is RFWU or RFWO. */
1122  code = insn & 0x00ffffff;
1123  return ((code == 0x00003400) || (code == 0x00003500));
1124  }
1125 }
1126 
1127 /* Returns the best guess about which register is a frame pointer
1128  for the function containing CURRENT_PC. */
1129 
1130 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1131 #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
1132 
1133 static unsigned int
1134 xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc)
1135 {
1136 #define RETURN_FP goto done
1137 
1138  unsigned int fp_regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
1139  CORE_ADDR start_addr;
1140  xtensa_isa isa;
1141  xtensa_insnbuf ins, slot;
1142  gdb_byte ibuf[XTENSA_ISA_BSZ];
1143  CORE_ADDR ia, bt, ba;
1144  xtensa_format ifmt;
1145  int ilen, islots, is;
1146  xtensa_opcode opc;
1147  const char *opcname;
1148 
1149  find_pc_partial_function (current_pc, NULL, &start_addr, NULL);
1150  if (start_addr == 0)
1151  return fp_regnum;
1152 
1153  if (!xtensa_default_isa)
1154  xtensa_default_isa = xtensa_isa_init (0, 0);
1155  isa = xtensa_default_isa;
1156  gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
1157  ins = xtensa_insnbuf_alloc (isa);
1158  slot = xtensa_insnbuf_alloc (isa);
1159  ba = 0;
1160 
1161  for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen)
1162  {
1163  if (ia + xtensa_isa_maxlength (isa) > bt)
1164  {
1165  ba = ia;
1166  bt = (ba + XTENSA_ISA_BSZ) < current_pc
1167  ? ba + XTENSA_ISA_BSZ : current_pc;
1168  if (target_read_memory (ba, ibuf, bt - ba) != 0)
1169  RETURN_FP;
1170  }
1171 
1172  xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
1173  ifmt = xtensa_format_decode (isa, ins);
1174  if (ifmt == XTENSA_UNDEFINED)
1175  RETURN_FP;
1176  ilen = xtensa_format_length (isa, ifmt);
1177  if (ilen == XTENSA_UNDEFINED)
1178  RETURN_FP;
1179  islots = xtensa_format_num_slots (isa, ifmt);
1180  if (islots == XTENSA_UNDEFINED)
1181  RETURN_FP;
1182 
1183  for (is = 0; is < islots; ++is)
1184  {
1185  if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
1186  RETURN_FP;
1187 
1188  opc = xtensa_opcode_decode (isa, ifmt, is, slot);
1189  if (opc == XTENSA_UNDEFINED)
1190  RETURN_FP;
1191 
1192  opcname = xtensa_opcode_name (isa, opc);
1193 
1194  if (strcasecmp (opcname, "mov.n") == 0
1195  || strcasecmp (opcname, "or") == 0)
1196  {
1197  unsigned int register_operand;
1198 
1199  /* Possible candidate for setting frame pointer
1200  from A1. This is what we are looking for. */
1201 
1202  if (xtensa_operand_get_field (isa, opc, 1, ifmt,
1203  is, slot, &register_operand) != 0)
1204  RETURN_FP;
1205  if (xtensa_operand_decode (isa, opc, 1, &register_operand) != 0)
1206  RETURN_FP;
1207  if (register_operand == 1) /* Mov{.n} FP A1. */
1208  {
1209  if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot,
1210  &register_operand) != 0)
1211  RETURN_FP;
1212  if (xtensa_operand_decode (isa, opc, 0,
1213  &register_operand) != 0)
1214  RETURN_FP;
1215 
1216  fp_regnum
1217  = gdbarch_tdep (gdbarch)->a0_base + register_operand;
1218  RETURN_FP;
1219  }
1220  }
1221 
1222  if (
1223  /* We have problems decoding the memory. */
1224  opcname == NULL
1225  || strcasecmp (opcname, "ill") == 0
1226  || strcasecmp (opcname, "ill.n") == 0
1227  /* Hit planted breakpoint. */
1228  || strcasecmp (opcname, "break") == 0
1229  || strcasecmp (opcname, "break.n") == 0
1230  /* Flow control instructions finish prologue. */
1231  || xtensa_opcode_is_branch (isa, opc) > 0
1232  || xtensa_opcode_is_jump (isa, opc) > 0
1233  || xtensa_opcode_is_loop (isa, opc) > 0
1234  || xtensa_opcode_is_call (isa, opc) > 0
1235  || strcasecmp (opcname, "simcall") == 0
1236  || strcasecmp (opcname, "syscall") == 0)
1237  /* Can not continue analysis. */
1238  RETURN_FP;
1239  }
1240  }
1241 done:
1242  xtensa_insnbuf_free(isa, slot);
1243  xtensa_insnbuf_free(isa, ins);
1244  return fp_regnum;
1245 }
1246 
1247 /* The key values to identify the frame using "cache" are
1248 
1249  cache->base = SP (or best guess about FP) of this frame;
1250  cache->pc = entry-PC (entry point of the frame function);
1251  cache->prev_sp = SP of the previous frame. */
1252 
1253 static void
1254 call0_frame_cache (struct frame_info *this_frame,
1255  xtensa_frame_cache_t *cache, CORE_ADDR pc);
1256 
1257 static void
1259  xtensa_frame_cache_t *cache,
1260  CORE_ADDR pc);
1261 
1262 static struct xtensa_frame_cache *
1263 xtensa_frame_cache (struct frame_info *this_frame, void **this_cache)
1264 {
1265  xtensa_frame_cache_t *cache;
1266  CORE_ADDR ra, wb, ws, pc, sp, ps;
1267  struct gdbarch *gdbarch = get_frame_arch (this_frame);
1268  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1269  unsigned int fp_regnum;
1270  int windowed, ps_regnum;
1271 
1272  if (*this_cache)
1273  return *this_cache;
1274 
1275  pc = get_frame_register_unsigned (this_frame, gdbarch_pc_regnum (gdbarch));
1276  ps_regnum = gdbarch_ps_regnum (gdbarch);
1277  ps = (ps_regnum >= 0
1278  ? get_frame_register_unsigned (this_frame, ps_regnum) : TX_PS);
1279 
1280  windowed = windowing_enabled (gdbarch, ps);
1281 
1282  /* Get pristine xtensa-frame. */
1283  cache = xtensa_alloc_frame_cache (windowed);
1284  *this_cache = cache;
1285 
1286  if (windowed)
1287  {
1288  char op1;
1289 
1290  /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1291  wb = get_frame_register_unsigned (this_frame,
1292  gdbarch_tdep (gdbarch)->wb_regnum);
1293  ws = get_frame_register_unsigned (this_frame,
1294  gdbarch_tdep (gdbarch)->ws_regnum);
1295 
1296  op1 = read_memory_integer (pc, 1, byte_order);
1297  if (XTENSA_IS_ENTRY (gdbarch, op1))
1298  {
1299  int callinc = CALLINC (ps);
1301  (this_frame, gdbarch_tdep (gdbarch)->a0_base + callinc * 4);
1302 
1303  /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1304  cache->wd.callsize = 0;
1305  cache->wd.wb = wb;
1306  cache->wd.ws = ws;
1308  (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1309 
1310  /* This only can be the outermost frame since we are
1311  just about to execute ENTRY. SP hasn't been set yet.
1312  We can assume any frame size, because it does not
1313  matter, and, let's fake frame base in cache. */
1314  cache->base = cache->prev_sp - 16;
1315 
1316  cache->pc = pc;
1317  cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
1318  cache->ps = (ps & ~PS_CALLINC_MASK)
1319  | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1320 
1321  return cache;
1322  }
1323  else
1324  {
1325  fp_regnum = xtensa_scan_prologue (gdbarch, pc);
1326  ra = get_frame_register_unsigned (this_frame,
1327  gdbarch_tdep (gdbarch)->a0_base);
1328  cache->wd.callsize = WINSIZE (ra);
1329  cache->wd.wb = (wb - cache->wd.callsize / 4)
1330  & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1);
1331  cache->wd.ws = ws & ~(1 << wb);
1332 
1333  cache->pc = get_frame_func (this_frame);
1334  cache->ra = (pc & 0xc0000000) | (ra & 0x3fffffff);
1335  cache->ps = (ps & ~PS_CALLINC_MASK)
1336  | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1337  }
1338 
1339  if (cache->wd.ws == 0)
1340  {
1341  int i;
1342 
1343  /* Set A0...A3. */
1345  (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16;
1346 
1347  for (i = 0; i < 4; i++, sp += 4)
1348  {
1349  cache->wd.aregs[i] = sp;
1350  }
1351 
1352  if (cache->wd.callsize > 4)
1353  {
1354  /* Set A4...A7/A11. */
1355  /* Get the SP of the frame previous to the previous one.
1356  To achieve this, we have to dereference SP twice. */
1357  sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1358  sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1359  sp -= cache->wd.callsize * 4;
1360 
1361  for ( i = 4; i < cache->wd.callsize; i++, sp += 4)
1362  {
1363  cache->wd.aregs[i] = sp;
1364  }
1365  }
1366  }
1367 
1368  if ((cache->prev_sp == 0) && ( ra != 0 ))
1369  /* If RA is equal to 0 this frame is an outermost frame. Leave
1370  cache->prev_sp unchanged marking the boundary of the frame stack. */
1371  {
1372  if ((cache->wd.ws & (1 << cache->wd.wb)) == 0)
1373  {
1374  /* Register window overflow already happened.
1375  We can read caller's SP from the proper spill loction. */
1377  (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1378  cache->prev_sp = read_memory_integer (sp - 12, 4, byte_order);
1379  }
1380  else
1381  {
1382  /* Read caller's frame SP directly from the previous window. */
1383  int regnum = arreg_number
1384  (gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1,
1385  cache->wd.wb);
1386 
1387  cache->prev_sp = xtensa_read_register (regnum);
1388  }
1389  }
1390  }
1391  else if (xtensa_window_interrupt_insn (gdbarch, pc))
1392  {
1393  /* Execution stopped inside Xtensa Window Interrupt Handler. */
1394 
1395  xtensa_window_interrupt_frame_cache (this_frame, cache, pc);
1396  /* Everything was set already, including cache->base. */
1397  return cache;
1398  }
1399  else /* Call0 framework. */
1400  {
1401  call0_frame_cache (this_frame, cache, pc);
1402  fp_regnum = cache->c0.fp_regnum;
1403  }
1404 
1405  cache->base = get_frame_register_unsigned (this_frame, fp_regnum);
1406 
1407  return cache;
1408 }
1409 
1411 
1412 /* Report a problem with prologue analysis while doing backtracing.
1413  But, do it only once to avoid annoyng repeated messages. */
1414 
1415 static void
1417 {
1419  warning (_("\
1420 \nUnrecognised function prologue. Stack trace cannot be resolved. \
1421 This message will not be repeated in this session.\n"));
1422 
1424 }
1425 
1426 
1427 static void
1428 xtensa_frame_this_id (struct frame_info *this_frame,
1429  void **this_cache,
1430  struct frame_id *this_id)
1431 {
1432  struct xtensa_frame_cache *cache =
1433  xtensa_frame_cache (this_frame, this_cache);
1434 
1435  if (cache->prev_sp == 0)
1436  return;
1437 
1438  (*this_id) = frame_id_build (cache->prev_sp, cache->pc);
1439 }
1440 
1441 static struct value *
1443  void **this_cache,
1444  int regnum)
1445 {
1446  struct gdbarch *gdbarch = get_frame_arch (this_frame);
1447  struct xtensa_frame_cache *cache;
1448  ULONGEST saved_reg = 0;
1449  int done = 1;
1450 
1451  if (*this_cache == NULL)
1452  *this_cache = xtensa_frame_cache (this_frame, this_cache);
1453  cache = *this_cache;
1454 
1455  if (regnum ==gdbarch_pc_regnum (gdbarch))
1456  saved_reg = cache->ra;
1457  else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1)
1458  saved_reg = cache->prev_sp;
1459  else if (!cache->call0)
1460  {
1461  if (regnum == gdbarch_tdep (gdbarch)->ws_regnum)
1462  saved_reg = cache->wd.ws;
1463  else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum)
1464  saved_reg = cache->wd.wb;
1465  else if (regnum == gdbarch_ps_regnum (gdbarch))
1466  saved_reg = cache->ps;
1467  else
1468  done = 0;
1469  }
1470  else
1471  done = 0;
1472 
1473  if (done)
1474  return frame_unwind_got_constant (this_frame, regnum, saved_reg);
1475 
1476  if (!cache->call0) /* Windowed ABI. */
1477  {
1478  /* Convert A-register numbers to AR-register numbers,
1479  if we deal with A-register. */
1480  if (regnum >= gdbarch_tdep (gdbarch)->a0_base
1481  && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)
1482  regnum = arreg_number (gdbarch, regnum, cache->wd.wb);
1483 
1484  /* Check, if we deal with AR-register saved on stack. */
1485  if (regnum >= gdbarch_tdep (gdbarch)->ar_base
1486  && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1487  + gdbarch_tdep (gdbarch)->num_aregs))
1488  {
1489  int areg = areg_number (gdbarch, regnum, cache->wd.wb);
1490 
1491  if (areg >= 0
1492  && areg < XTENSA_NUM_SAVED_AREGS
1493  && cache->wd.aregs[areg] != -1)
1494  return frame_unwind_got_memory (this_frame, regnum,
1495  cache->wd.aregs[areg]);
1496  }
1497  }
1498  else /* Call0 ABI. */
1499  {
1500  int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base
1501  && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1502  + C0_NREGS))
1503  ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum;
1504 
1505  if (reg < C0_NREGS)
1506  {
1507  CORE_ADDR spe;
1508  int stkofs;
1509 
1510  /* If register was saved in the prologue, retrieve it. */
1511  stkofs = cache->c0.c0_rt[reg].to_stk;
1512  if (stkofs != C0_NOSTK)
1513  {
1514  /* Determine SP on entry based on FP. */
1515  spe = cache->c0.c0_fp
1516  - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1517 
1518  return frame_unwind_got_memory (this_frame, regnum,
1519  spe + stkofs);
1520  }
1521  }
1522  }
1523 
1524  /* All other registers have been either saved to
1525  the stack or are still alive in the processor. */
1526 
1527  return frame_unwind_got_register (this_frame, regnum, regnum);
1528 }
1529 
1530 
1531 static const struct frame_unwind
1532 xtensa_unwind =
1533 {
1534  NORMAL_FRAME,
1538  NULL,
1540 };
1541 
1542 static CORE_ADDR
1543 xtensa_frame_base_address (struct frame_info *this_frame, void **this_cache)
1544 {
1545  struct xtensa_frame_cache *cache =
1546  xtensa_frame_cache (this_frame, this_cache);
1547 
1548  return cache->base;
1549 }
1550 
1551 static const struct frame_base
1552 xtensa_frame_base =
1553 {
1554  &xtensa_unwind,
1557  xtensa_frame_base_address
1558 };
1559 
1560 
1561 static void
1563  struct regcache *regcache,
1564  void *dst)
1565 {
1566  struct gdbarch *gdbarch = get_regcache_arch (regcache);
1567  bfd_byte *valbuf = dst;
1568  int len = TYPE_LENGTH (type);
1569  ULONGEST pc, wb;
1570  int callsize, areg;
1571  int offset = 0;
1572 
1573  DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1574 
1575  gdb_assert(len > 0);
1576 
1577  if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1578  {
1579  /* First, we have to find the caller window in the register file. */
1580  regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1581  callsize = extract_call_winsize (gdbarch, pc);
1582 
1583  /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1584  if (len > (callsize > 8 ? 8 : 16))
1585  internal_error (__FILE__, __LINE__,
1586  _("cannot extract return value of %d bytes long"),
1587  len);
1588 
1589  /* Get the register offset of the return
1590  register (A2) in the caller window. */
1592  (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1593  areg = arreg_number (gdbarch,
1594  gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1595  }
1596  else
1597  {
1598  /* No windowing hardware - Call0 ABI. */
1599  areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1600  }
1601 
1602  DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1603 
1604  if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1605  offset = 4 - len;
1606 
1607  for (; len > 0; len -= 4, areg++, valbuf += 4)
1608  {
1609  if (len < 4)
1610  regcache_raw_read_part (regcache, areg, offset, len, valbuf);
1611  else
1612  regcache_raw_read (regcache, areg, valbuf);
1613  }
1614 }
1615 
1616 
1617 static void
1619  struct regcache *regcache,
1620  const void *dst)
1621 {
1622  struct gdbarch *gdbarch = get_regcache_arch (regcache);
1623  const bfd_byte *valbuf = dst;
1624  unsigned int areg;
1625  ULONGEST pc, wb;
1626  int callsize;
1627  int len = TYPE_LENGTH (type);
1628  int offset = 0;
1629 
1630  DEBUGTRACE ("xtensa_store_return_value (...)\n");
1631 
1632  if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1633  {
1635  (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1636  regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1637  callsize = extract_call_winsize (gdbarch, pc);
1638 
1639  if (len > (callsize > 8 ? 8 : 16))
1640  internal_error (__FILE__, __LINE__,
1641  _("unimplemented for this length: %d"),
1642  TYPE_LENGTH (type));
1643  areg = arreg_number (gdbarch,
1644  gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1645 
1646  DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1647  callsize, (int) wb);
1648  }
1649  else
1650  {
1651  areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1652  }
1653 
1654  if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1655  offset = 4 - len;
1656 
1657  for (; len > 0; len -= 4, areg++, valbuf += 4)
1658  {
1659  if (len < 4)
1660  regcache_raw_write_part (regcache, areg, offset, len, valbuf);
1661  else
1662  regcache_raw_write (regcache, areg, valbuf);
1663  }
1664 }
1665 
1666 
1667 static enum return_value_convention
1668 xtensa_return_value (struct gdbarch *gdbarch,
1669  struct value *function,
1670  struct type *valtype,
1671  struct regcache *regcache,
1672  gdb_byte *readbuf,
1673  const gdb_byte *writebuf)
1674 {
1675  /* Structures up to 16 bytes are returned in registers. */
1676 
1677  int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1678  || TYPE_CODE (valtype) == TYPE_CODE_UNION
1679  || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1680  && TYPE_LENGTH (valtype) > 16);
1681 
1682  if (struct_return)
1684 
1685  DEBUGTRACE ("xtensa_return_value(...)\n");
1686 
1687  if (writebuf != NULL)
1688  {
1689  xtensa_store_return_value (valtype, regcache, writebuf);
1690  }
1691 
1692  if (readbuf != NULL)
1693  {
1694  gdb_assert (!struct_return);
1695  xtensa_extract_return_value (valtype, regcache, readbuf);
1696  }
1698 }
1699 
1700 
1701 /* DUMMY FRAME */
1702 
1703 static CORE_ADDR
1704 xtensa_push_dummy_call (struct gdbarch *gdbarch,
1705  struct value *function,
1706  struct regcache *regcache,
1707  CORE_ADDR bp_addr,
1708  int nargs,
1709  struct value **args,
1710  CORE_ADDR sp,
1711  int struct_return,
1712  CORE_ADDR struct_addr)
1713 {
1714  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1715  int i;
1716  int size, onstack_size;
1717  gdb_byte *buf = (gdb_byte *) alloca (16);
1718  CORE_ADDR ra, ps;
1719  struct argument_info
1720  {
1721  const bfd_byte *contents;
1722  int length;
1723  int onstack; /* onstack == 0 => in reg */
1724  int align; /* alignment */
1725  union
1726  {
1727  int offset; /* stack offset if on stack. */
1728  int regno; /* regno if in register. */
1729  } u;
1730  };
1731 
1732  struct argument_info *arg_info =
1733  (struct argument_info *) alloca (nargs * sizeof (struct argument_info));
1734 
1735  CORE_ADDR osp = sp;
1736 
1737  DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1738 
1739  if (xtensa_debug_level > 3)
1740  {
1741  int i;
1742  DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs);
1743  DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1744  "struct_addr=0x%x\n",
1745  (int) sp, (int) struct_return, (int) struct_addr);
1746 
1747  for (i = 0; i < nargs; i++)
1748  {
1749  struct value *arg = args[i];
1750  struct type *arg_type = check_typedef (value_type (arg));
1751  fprintf_unfiltered (gdb_stdlog, "%2d: %s %3d ", i,
1752  host_address_to_string (arg),
1753  TYPE_LENGTH (arg_type));
1754  switch (TYPE_CODE (arg_type))
1755  {
1756  case TYPE_CODE_INT:
1757  fprintf_unfiltered (gdb_stdlog, "int");
1758  break;
1759  case TYPE_CODE_STRUCT:
1760  fprintf_unfiltered (gdb_stdlog, "struct");
1761  break;
1762  default:
1763  fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type));
1764  break;
1765  }
1766  fprintf_unfiltered (gdb_stdlog, " %s\n",
1768  }
1769  }
1770 
1771  /* First loop: collect information.
1772  Cast into type_long. (This shouldn't happen often for C because
1773  GDB already does this earlier.) It's possible that GDB could
1774  do it all the time but it's harmless to leave this code here. */
1775 
1776  size = 0;
1777  onstack_size = 0;
1778  i = 0;
1779 
1780  if (struct_return)
1781  size = REGISTER_SIZE;
1782 
1783  for (i = 0; i < nargs; i++)
1784  {
1785  struct argument_info *info = &arg_info[i];
1786  struct value *arg = args[i];
1787  struct type *arg_type = check_typedef (value_type (arg));
1788 
1789  switch (TYPE_CODE (arg_type))
1790  {
1791  case TYPE_CODE_INT:
1792  case TYPE_CODE_BOOL:
1793  case TYPE_CODE_CHAR:
1794  case TYPE_CODE_RANGE:
1795  case TYPE_CODE_ENUM:
1796 
1797  /* Cast argument to long if necessary as the mask does it too. */
1798  if (TYPE_LENGTH (arg_type)
1799  < TYPE_LENGTH (builtin_type (gdbarch)->builtin_long))
1800  {
1801  arg_type = builtin_type (gdbarch)->builtin_long;
1802  arg = value_cast (arg_type, arg);
1803  }
1804  /* Aligment is equal to the type length for the basic types. */
1805  info->align = TYPE_LENGTH (arg_type);
1806  break;
1807 
1808  case TYPE_CODE_FLT:
1809 
1810  /* Align doubles correctly. */
1811  if (TYPE_LENGTH (arg_type)
1812  == TYPE_LENGTH (builtin_type (gdbarch)->builtin_double))
1813  info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_double);
1814  else
1815  info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1816  break;
1817 
1818  case TYPE_CODE_STRUCT:
1819  default:
1820  info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1821  break;
1822  }
1823  info->length = TYPE_LENGTH (arg_type);
1824  info->contents = value_contents (arg);
1825 
1826  /* Align size and onstack_size. */
1827  size = (size + info->align - 1) & ~(info->align - 1);
1828  onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1829 
1830  if (size + info->length > REGISTER_SIZE * ARG_NOF (gdbarch))
1831  {
1832  info->onstack = 1;
1833  info->u.offset = onstack_size;
1834  onstack_size += info->length;
1835  }
1836  else
1837  {
1838  info->onstack = 0;
1839  info->u.regno = ARG_1ST (gdbarch) + size / REGISTER_SIZE;
1840  }
1841  size += info->length;
1842  }
1843 
1844  /* Adjust the stack pointer and align it. */
1845  sp = align_down (sp - onstack_size, SP_ALIGNMENT);
1846 
1847  /* Simulate MOVSP, if Windowed ABI. */
1848  if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1849  && (sp != osp))
1850  {
1851  read_memory (osp - 16, buf, 16);
1852  write_memory (sp - 16, buf, 16);
1853  }
1854 
1855  /* Second Loop: Load arguments. */
1856 
1857  if (struct_return)
1858  {
1859  store_unsigned_integer (buf, REGISTER_SIZE, byte_order, struct_addr);
1860  regcache_cooked_write (regcache, ARG_1ST (gdbarch), buf);
1861  }
1862 
1863  for (i = 0; i < nargs; i++)
1864  {
1865  struct argument_info *info = &arg_info[i];
1866 
1867  if (info->onstack)
1868  {
1869  int n = info->length;
1870  CORE_ADDR offset = sp + info->u.offset;
1871 
1872  /* Odd-sized structs are aligned to the lower side of a memory
1873  word in big-endian mode and require a shift. This only
1874  applies for structures smaller than one word. */
1875 
1876  if (n < REGISTER_SIZE
1877  && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1878  offset += (REGISTER_SIZE - n);
1879 
1880  write_memory (offset, info->contents, info->length);
1881 
1882  }
1883  else
1884  {
1885  int n = info->length;
1886  const bfd_byte *cp = info->contents;
1887  int r = info->u.regno;
1888 
1889  /* Odd-sized structs are aligned to the lower side of registers in
1890  big-endian mode and require a shift. The odd-sized leftover will
1891  be at the end. Note that this is only true for structures smaller
1892  than REGISTER_SIZE; for larger odd-sized structures the excess
1893  will be left-aligned in the register on both endiannesses. */
1894 
1895  if (n < REGISTER_SIZE && byte_order == BFD_ENDIAN_BIG)
1896  {
1897  ULONGEST v;
1898  v = extract_unsigned_integer (cp, REGISTER_SIZE, byte_order);
1899  v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
1900 
1901  store_unsigned_integer (buf, REGISTER_SIZE, byte_order, v);
1902  regcache_cooked_write (regcache, r, buf);
1903 
1904  cp += REGISTER_SIZE;
1905  n -= REGISTER_SIZE;
1906  r++;
1907  }
1908  else
1909  while (n > 0)
1910  {
1911  regcache_cooked_write (regcache, r, cp);
1912 
1913  cp += REGISTER_SIZE;
1914  n -= REGISTER_SIZE;
1915  r++;
1916  }
1917  }
1918  }
1919 
1920  /* Set the return address of dummy frame to the dummy address.
1921  The return address for the current function (in A0) is
1922  saved in the dummy frame, so we can savely overwrite A0 here. */
1923 
1924  if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1925  {
1926  ULONGEST val;
1927 
1928  ra = (bp_addr & 0x3fffffff) | 0x40000000;
1929  regcache_raw_read_unsigned (regcache, gdbarch_ps_regnum (gdbarch), &val);
1930  ps = (unsigned long) val & ~0x00030000;
1932  (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra);
1934  gdbarch_ps_regnum (gdbarch),
1935  ps | 0x00010000);
1936 
1937  /* All the registers have been saved. After executing
1938  dummy call, they all will be restored. So it's safe
1939  to modify WINDOWSTART register to make it look like there
1940  is only one register window corresponding to WINDOWEBASE. */
1941 
1942  regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
1944  (regcache, gdbarch_tdep (gdbarch)->ws_regnum,
1945  1 << extract_unsigned_integer (buf, 4, byte_order));
1946  }
1947  else
1948  {
1949  /* Simulate CALL0: write RA into A0 register. */
1951  (regcache, gdbarch_tdep (gdbarch)->a0_base, bp_addr);
1952  }
1953 
1954  /* Set new stack pointer and return it. */
1956  gdbarch_tdep (gdbarch)->a0_base + 1, sp);
1957  /* Make dummy frame ID unique by adding a constant. */
1958  return sp + SP_ALIGNMENT;
1959 }
1960 
1961 
1962 /* Return a breakpoint for the current location of PC. We always use
1963  the density version if we have density instructions (regardless of the
1964  current instruction at PC), and use regular instructions otherwise. */
1965 
1966 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1967 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1968 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1969 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1970 
1971 static const unsigned char *
1972 xtensa_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
1973  int *lenptr)
1974 {
1975  static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
1976  static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
1977  static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
1978  static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT;
1979 
1980  DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr);
1981 
1982  if (gdbarch_tdep (gdbarch)->isa_use_density_instructions)
1983  {
1984  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1985  {
1986  *lenptr = sizeof (density_big_breakpoint);
1987  return density_big_breakpoint;
1988  }
1989  else
1990  {
1991  *lenptr = sizeof (density_little_breakpoint);
1992  return density_little_breakpoint;
1993  }
1994  }
1995  else
1996  {
1997  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1998  {
1999  *lenptr = sizeof (big_breakpoint);
2000  return big_breakpoint;
2001  }
2002  else
2003  {
2004  *lenptr = sizeof (little_breakpoint);
2005  return little_breakpoint;
2006  }
2007  }
2008 }
2009 
2010 /* Call0 ABI support routines. */
2011 
2012 /* Return true, if PC points to "ret" or "ret.n". */
2013 
2014 static int
2015 call0_ret (CORE_ADDR start_pc, CORE_ADDR finish_pc)
2016 {
2017 #define RETURN_RET goto done
2018  xtensa_isa isa;
2019  xtensa_insnbuf ins, slot;
2020  gdb_byte ibuf[XTENSA_ISA_BSZ];
2021  CORE_ADDR ia, bt, ba;
2022  xtensa_format ifmt;
2023  int ilen, islots, is;
2024  xtensa_opcode opc;
2025  const char *opcname;
2026  int found_ret = 0;
2027 
2028  isa = xtensa_default_isa;
2029  gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2030  ins = xtensa_insnbuf_alloc (isa);
2031  slot = xtensa_insnbuf_alloc (isa);
2032  ba = 0;
2033 
2034  for (ia = start_pc, bt = ia; ia < finish_pc ; ia += ilen)
2035  {
2036  if (ia + xtensa_isa_maxlength (isa) > bt)
2037  {
2038  ba = ia;
2039  bt = (ba + XTENSA_ISA_BSZ) < finish_pc
2040  ? ba + XTENSA_ISA_BSZ : finish_pc;
2041  if (target_read_memory (ba, ibuf, bt - ba) != 0 )
2042  RETURN_RET;
2043  }
2044 
2045  xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2046  ifmt = xtensa_format_decode (isa, ins);
2047  if (ifmt == XTENSA_UNDEFINED)
2048  RETURN_RET;
2049  ilen = xtensa_format_length (isa, ifmt);
2050  if (ilen == XTENSA_UNDEFINED)
2051  RETURN_RET;
2052  islots = xtensa_format_num_slots (isa, ifmt);
2053  if (islots == XTENSA_UNDEFINED)
2054  RETURN_RET;
2055 
2056  for (is = 0; is < islots; ++is)
2057  {
2058  if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2059  RETURN_RET;
2060 
2061  opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2062  if (opc == XTENSA_UNDEFINED)
2063  RETURN_RET;
2064 
2065  opcname = xtensa_opcode_name (isa, opc);
2066 
2067  if ((strcasecmp (opcname, "ret.n") == 0)
2068  || (strcasecmp (opcname, "ret") == 0))
2069  {
2070  found_ret = 1;
2071  RETURN_RET;
2072  }
2073  }
2074  }
2075  done:
2076  xtensa_insnbuf_free(isa, slot);
2077  xtensa_insnbuf_free(isa, ins);
2078  return found_ret;
2079 }
2080 
2081 /* Call0 opcode class. Opcodes are preclassified according to what they
2082  mean for Call0 prologue analysis, and their number of significant operands.
2083  The purpose of this is to simplify prologue analysis by separating
2084  instruction decoding (libisa) from the semantics of prologue analysis. */
2085 
2086 typedef enum
2087 {
2088  c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */
2089  c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */
2090  c0opc_flow, /* Flow control insn. */
2091  c0opc_entry, /* ENTRY indicates non-Call0 prologue. */
2092  c0opc_break, /* Debugger software breakpoints. */
2093  c0opc_add, /* Adding two registers. */
2094  c0opc_addi, /* Adding a register and an immediate. */
2095  c0opc_and, /* Bitwise "and"-ing two registers. */
2096  c0opc_sub, /* Subtracting a register from a register. */
2097  c0opc_mov, /* Moving a register to a register. */
2098  c0opc_movi, /* Moving an immediate to a register. */
2099  c0opc_l32r, /* Loading a literal. */
2100  c0opc_s32i, /* Storing word at fixed offset from a base register. */
2101  c0opc_rwxsr, /* RSR, WRS, or XSR instructions. */
2102  c0opc_l32e, /* L32E instruction. */
2103  c0opc_s32e, /* S32E instruction. */
2104  c0opc_rfwo, /* RFWO instruction. */
2105  c0opc_rfwu, /* RFWU instruction. */
2106  c0opc_NrOf /* Number of opcode classifications. */
2108 
2109 /* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */
2110 
2111 static int
2112 rwx_special_register (const char *opcname)
2113 {
2114  char ch = *opcname++;
2115 
2116  if ((ch != 'r') && (ch != 'w') && (ch != 'x'))
2117  return 0;
2118  if (*opcname++ != 's')
2119  return 0;
2120  if (*opcname++ != 'r')
2121  return 0;
2122  if (*opcname++ != '.')
2123  return 0;
2124 
2125  return 1;
2126 }
2127 
2128 /* Classify an opcode based on what it means for Call0 prologue analysis. */
2129 
2130 static xtensa_insn_kind
2131 call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
2132 {
2133  const char *opcname;
2135 
2136  DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc);
2137 
2138  /* Get opcode name and handle special classifications. */
2139 
2140  opcname = xtensa_opcode_name (isa, opc);
2141 
2142  if (opcname == NULL
2143  || strcasecmp (opcname, "ill") == 0
2144  || strcasecmp (opcname, "ill.n") == 0)
2145  opclass = c0opc_illegal;
2146  else if (strcasecmp (opcname, "break") == 0
2147  || strcasecmp (opcname, "break.n") == 0)
2148  opclass = c0opc_break;
2149  else if (strcasecmp (opcname, "entry") == 0)
2150  opclass = c0opc_entry;
2151  else if (strcasecmp (opcname, "rfwo") == 0)
2152  opclass = c0opc_rfwo;
2153  else if (strcasecmp (opcname, "rfwu") == 0)
2154  opclass = c0opc_rfwu;
2155  else if (xtensa_opcode_is_branch (isa, opc) > 0
2156  || xtensa_opcode_is_jump (isa, opc) > 0
2157  || xtensa_opcode_is_loop (isa, opc) > 0
2158  || xtensa_opcode_is_call (isa, opc) > 0
2159  || strcasecmp (opcname, "simcall") == 0
2160  || strcasecmp (opcname, "syscall") == 0)
2161  opclass = c0opc_flow;
2162 
2163  /* Also, classify specific opcodes that need to be tracked. */
2164  else if (strcasecmp (opcname, "add") == 0
2165  || strcasecmp (opcname, "add.n") == 0)
2166  opclass = c0opc_add;
2167  else if (strcasecmp (opcname, "and") == 0)
2168  opclass = c0opc_and;
2169  else if (strcasecmp (opcname, "addi") == 0
2170  || strcasecmp (opcname, "addi.n") == 0
2171  || strcasecmp (opcname, "addmi") == 0)
2172  opclass = c0opc_addi;
2173  else if (strcasecmp (opcname, "sub") == 0)
2174  opclass = c0opc_sub;
2175  else if (strcasecmp (opcname, "mov.n") == 0
2176  || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */
2177  opclass = c0opc_mov;
2178  else if (strcasecmp (opcname, "movi") == 0
2179  || strcasecmp (opcname, "movi.n") == 0)
2180  opclass = c0opc_movi;
2181  else if (strcasecmp (opcname, "l32r") == 0)
2182  opclass = c0opc_l32r;
2183  else if (strcasecmp (opcname, "s32i") == 0
2184  || strcasecmp (opcname, "s32i.n") == 0)
2185  opclass = c0opc_s32i;
2186  else if (strcasecmp (opcname, "l32e") == 0)
2187  opclass = c0opc_l32e;
2188  else if (strcasecmp (opcname, "s32e") == 0)
2189  opclass = c0opc_s32e;
2190  else if (rwx_special_register (opcname))
2191  opclass = c0opc_rwxsr;
2192 
2193  return opclass;
2194 }
2195 
2196 /* Tracks register movement/mutation for a given operation, which may
2197  be within a bundle. Updates the destination register tracking info
2198  accordingly. The pc is needed only for pc-relative load instructions
2199  (eg. l32r). The SP register number is needed to identify stores to
2200  the stack frame. Returns 0, if analysis was succesfull, non-zero
2201  otherwise. */
2202 
2203 static int
2204 call0_track_op (struct gdbarch *gdbarch, xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
2205  xtensa_insn_kind opclass, int nods, unsigned odv[],
2206  CORE_ADDR pc, int spreg, xtensa_frame_cache_t *cache)
2207 {
2208  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2209  unsigned litbase, litaddr, litval;
2210 
2211  switch (opclass)
2212  {
2213  case c0opc_addi:
2214  /* 3 operands: dst, src, imm. */
2215  gdb_assert (nods == 3);
2216  dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2217  dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2];
2218  break;
2219  case c0opc_add:
2220  /* 3 operands: dst, src1, src2. */
2221  gdb_assert (nods == 3);
2222  if (src[odv[1]].fr_reg == C0_CONST)
2223  {
2224  dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2225  dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs;
2226  }
2227  else if (src[odv[2]].fr_reg == C0_CONST)
2228  {
2229  dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2230  dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs;
2231  }
2232  else dst[odv[0]].fr_reg = C0_INEXP;
2233  break;
2234  case c0opc_and:
2235  /* 3 operands: dst, src1, src2. */
2236  gdb_assert (nods == 3);
2237  if (cache->c0.c0_fpalign == 0)
2238  {
2239  /* Handle dynamic stack alignment. */
2240  if ((src[odv[0]].fr_reg == spreg) && (src[odv[1]].fr_reg == spreg))
2241  {
2242  if (src[odv[2]].fr_reg == C0_CONST)
2243  cache->c0.c0_fpalign = src[odv[2]].fr_ofs;
2244  break;
2245  }
2246  else if ((src[odv[0]].fr_reg == spreg)
2247  && (src[odv[2]].fr_reg == spreg))
2248  {
2249  if (src[odv[1]].fr_reg == C0_CONST)
2250  cache->c0.c0_fpalign = src[odv[1]].fr_ofs;
2251  break;
2252  }
2253  /* else fall through. */
2254  }
2255  if (src[odv[1]].fr_reg == C0_CONST)
2256  {
2257  dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2258  dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs & src[odv[1]].fr_ofs;
2259  }
2260  else if (src[odv[2]].fr_reg == C0_CONST)
2261  {
2262  dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2263  dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs & src[odv[2]].fr_ofs;
2264  }
2265  else dst[odv[0]].fr_reg = C0_INEXP;
2266  break;
2267  case c0opc_sub:
2268  /* 3 operands: dst, src1, src2. */
2269  gdb_assert (nods == 3);
2270  if (src[odv[2]].fr_reg == C0_CONST)
2271  {
2272  dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2273  dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs;
2274  }
2275  else dst[odv[0]].fr_reg = C0_INEXP;
2276  break;
2277  case c0opc_mov:
2278  /* 2 operands: dst, src [, src]. */
2279  gdb_assert (nods == 2);
2280  /* First, check if it's a special case of saving unaligned SP
2281  to a spare register in case of dynamic stack adjustment.
2282  But, only do it one time. The second time could be initializing
2283  frame pointer. We don't want to overwrite the first one. */
2284  if ((odv[1] == spreg) && (cache->c0.c0_old_sp == C0_INEXP))
2285  cache->c0.c0_old_sp = odv[0];
2286 
2287  dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2288  dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
2289  break;
2290  case c0opc_movi:
2291  /* 2 operands: dst, imm. */
2292  gdb_assert (nods == 2);
2293  dst[odv[0]].fr_reg = C0_CONST;
2294  dst[odv[0]].fr_ofs = odv[1];
2295  break;
2296  case c0opc_l32r:
2297  /* 2 operands: dst, literal offset. */
2298  gdb_assert (nods == 2);
2299  /* litbase = xtensa_get_litbase (pc); can be also used. */
2300  litbase = (gdbarch_tdep (gdbarch)->litbase_regnum == -1)
2301  ? 0 : xtensa_read_register
2302  (gdbarch_tdep (gdbarch)->litbase_regnum);
2303  litaddr = litbase & 1
2304  ? (litbase & ~1) + (signed)odv[1]
2305  : (pc + 3 + (signed)odv[1]) & ~3;
2306  litval = read_memory_integer (litaddr, 4, byte_order);
2307  dst[odv[0]].fr_reg = C0_CONST;
2308  dst[odv[0]].fr_ofs = litval;
2309  break;
2310  case c0opc_s32i:
2311  /* 3 operands: value, base, offset. */
2312  gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
2313  /* First, check if it's a spill for saved unaligned SP,
2314  when dynamic stack adjustment was applied to this frame. */
2315  if ((cache->c0.c0_fpalign != 0) /* Dynamic stack adjustment. */
2316  && (odv[1] == spreg) /* SP usage indicates spill. */
2317  && (odv[0] == cache->c0.c0_old_sp)) /* Old SP register spilled. */
2318  cache->c0.c0_sp_ofs = odv[2];
2319 
2320  if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
2321  && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
2322  && src[odv[0]].fr_reg >= 0 /* Value is from a register. */
2323  && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */
2324  && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */
2325  {
2326  /* ISA encoding guarantees alignment. But, check it anyway. */
2327  gdb_assert ((odv[2] & 3) == 0);
2328  dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
2329  }
2330  break;
2331  /* If we end up inside Window Overflow / Underflow interrupt handler
2332  report an error because these handlers should have been handled
2333  already in a different way. */
2334  case c0opc_l32e:
2335  case c0opc_s32e:
2336  case c0opc_rfwo:
2337  case c0opc_rfwu:
2338  return 1;
2339  default:
2340  return 1;
2341  }
2342  return 0;
2343 }
2344 
2345 /* Analyze prologue of the function at start address to determine if it uses
2346  the Call0 ABI, and if so track register moves and linear modifications
2347  in the prologue up to the PC or just beyond the prologue, whichever is
2348  first. An 'entry' instruction indicates non-Call0 ABI and the end of the
2349  prologue. The prologue may overlap non-prologue instructions but is
2350  guaranteed to end by the first flow-control instruction (jump, branch,
2351  call or return). Since an optimized function may move information around
2352  and change the stack frame arbitrarily during the prologue, the information
2353  is guaranteed valid only at the point in the function indicated by the PC.
2354  May be used to skip the prologue or identify the ABI, w/o tracking.
2355 
2356  Returns: Address of first instruction after prologue, or PC (whichever
2357  is first), or 0, if decoding failed (in libisa).
2358  Input args:
2359  start Start address of function/prologue.
2360  pc Program counter to stop at. Use 0 to continue to end of prologue.
2361  If 0, avoids infinite run-on in corrupt code memory by bounding
2362  the scan to the end of the function if that can be determined.
2363  nregs Number of general registers to track.
2364  InOut args:
2365  cache Xtensa frame cache.
2366 
2367  Note that these may produce useful results even if decoding fails
2368  because they begin with default assumptions that analysis may change. */
2369 
2370 static CORE_ADDR
2371 call0_analyze_prologue (struct gdbarch *gdbarch,
2372  CORE_ADDR start, CORE_ADDR pc,
2373  int nregs, xtensa_frame_cache_t *cache)
2374 {
2375  CORE_ADDR ia; /* Current insn address in prologue. */
2376  CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
2377  CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
2378  gdb_byte ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */
2379  xtensa_isa isa; /* libisa ISA handle. */
2380  xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
2381  xtensa_format ifmt; /* libisa instruction format. */
2382  int ilen, islots, is; /* Instruction length, nbr slots, current slot. */
2383  xtensa_opcode opc; /* Opcode in current slot. */
2384  xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */
2385  int nods; /* Opcode number of operands. */
2386  unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */
2387  xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */
2388  int j; /* General loop counter. */
2389  int fail = 0; /* Set non-zero and exit, if decoding fails. */
2390  CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */
2391  CORE_ADDR end_pc; /* The PC for the lust function insn. */
2392 
2393  struct symtab_and_line prologue_sal;
2394 
2395  DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2396  (int)start, (int)pc);
2397 
2398  /* Try to limit the scan to the end of the function if a non-zero pc
2399  arg was not supplied to avoid probing beyond the end of valid memory.
2400  If memory is full of garbage that classifies as c0opc_uninteresting.
2401  If this fails (eg. if no symbols) pc ends up 0 as it was.
2402  Intialize the Call0 frame and register tracking info.
2403  Assume it's Call0 until an 'entry' instruction is encountered.
2404  Assume we may be in the prologue until we hit a flow control instr. */
2405 
2406  rtmp = NULL;
2407  body_pc = UINT_MAX;
2408  end_pc = 0;
2409 
2410  /* Find out, if we have an information about the prologue from DWARF. */
2411  prologue_sal = find_pc_line (start, 0);
2412  if (prologue_sal.line != 0) /* Found debug info. */
2413  body_pc = prologue_sal.end;
2414 
2415  /* If we are going to analyze the prologue in general without knowing about
2416  the current PC, make the best assumtion for the end of the prologue. */
2417  if (pc == 0)
2418  {
2419  find_pc_partial_function (start, 0, NULL, &end_pc);
2420  body_pc = min (end_pc, body_pc);
2421  }
2422  else
2423  body_pc = min (pc, body_pc);
2424 
2425  cache->call0 = 1;
2426  rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
2427 
2428  if (!xtensa_default_isa)
2429  xtensa_default_isa = xtensa_isa_init (0, 0);
2430  isa = xtensa_default_isa;
2431  gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2432  ins = xtensa_insnbuf_alloc (isa);
2433  slot = xtensa_insnbuf_alloc (isa);
2434 
2435  for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
2436  {
2437  /* (Re)fill instruction buffer from memory if necessary, but do not
2438  read memory beyond PC to be sure we stay within text section
2439  (this protection only works if a non-zero pc is supplied). */
2440 
2441  if (ia + xtensa_isa_maxlength (isa) > bt)
2442  {
2443  ba = ia;
2444  bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc;
2445  if (target_read_memory (ba, ibuf, bt - ba) != 0 )
2446  error (_("Unable to read target memory ..."));
2447  }
2448 
2449  /* Decode format information. */
2450 
2451  xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2452  ifmt = xtensa_format_decode (isa, ins);
2453  if (ifmt == XTENSA_UNDEFINED)
2454  {
2455  fail = 1;
2456  goto done;
2457  }
2458  ilen = xtensa_format_length (isa, ifmt);
2459  if (ilen == XTENSA_UNDEFINED)
2460  {
2461  fail = 1;
2462  goto done;
2463  }
2464  islots = xtensa_format_num_slots (isa, ifmt);
2465  if (islots == XTENSA_UNDEFINED)
2466  {
2467  fail = 1;
2468  goto done;
2469  }
2470 
2471  /* Analyze a bundle or a single instruction, using a snapshot of
2472  the register tracking info as input for the entire bundle so that
2473  register changes do not take effect within this bundle. */
2474 
2475  for (j = 0; j < nregs; ++j)
2476  rtmp[j] = cache->c0.c0_rt[j];
2477 
2478  for (is = 0; is < islots; ++is)
2479  {
2480  /* Decode a slot and classify the opcode. */
2481 
2482  fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
2483  if (fail)
2484  goto done;
2485 
2486  opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2487  DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2488  (unsigned)ia, opc);
2489  if (opc == XTENSA_UNDEFINED)
2490  opclass = c0opc_illegal;
2491  else
2492  opclass = call0_classify_opcode (isa, opc);
2493 
2494  /* Decide whether to track this opcode, ignore it, or bail out. */
2495 
2496  switch (opclass)
2497  {
2498  case c0opc_illegal:
2499  case c0opc_break:
2500  fail = 1;
2501  goto done;
2502 
2503  case c0opc_uninteresting:
2504  continue;
2505 
2506  case c0opc_flow: /* Flow control instructions stop analysis. */
2507  case c0opc_rwxsr: /* RSR, WSR, XSR instructions stop analysis. */
2508  goto done;
2509 
2510  case c0opc_entry:
2511  cache->call0 = 0;
2512  ia += ilen; /* Skip over 'entry' insn. */
2513  goto done;
2514 
2515  default:
2516  cache->call0 = 1;
2517  }
2518 
2519  /* Only expected opcodes should get this far. */
2520 
2521  /* Extract and decode the operands. */
2522  nods = xtensa_opcode_num_operands (isa, opc);
2523  if (nods == XTENSA_UNDEFINED)
2524  {
2525  fail = 1;
2526  goto done;
2527  }
2528 
2529  for (j = 0; j < nods && j < C0_MAXOPDS; ++j)
2530  {
2531  fail = xtensa_operand_get_field (isa, opc, j, ifmt,
2532  is, slot, &odv[j]);
2533  if (fail)
2534  goto done;
2535 
2536  fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
2537  if (fail)
2538  goto done;
2539  }
2540 
2541  /* Check operands to verify use of 'mov' assembler macro. */
2542  if (opclass == c0opc_mov && nods == 3)
2543  {
2544  if (odv[2] == odv[1])
2545  {
2546  nods = 2;
2547  if ((odv[0] == 1) && (odv[1] != 1))
2548  /* OR A1, An, An , where n != 1.
2549  This means we are inside epilogue already. */
2550  goto done;
2551  }
2552  else
2553  {
2554  opclass = c0opc_uninteresting;
2555  continue;
2556  }
2557  }
2558 
2559  /* Track register movement and modification for this operation. */
2560  fail = call0_track_op (gdbarch, cache->c0.c0_rt, rtmp,
2561  opclass, nods, odv, ia, 1, cache);
2562  if (fail)
2563  goto done;
2564  }
2565  }
2566 done:
2567  DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2568  (unsigned)ia, fail ? "failed" : "succeeded");
2569  xtensa_insnbuf_free(isa, slot);
2570  xtensa_insnbuf_free(isa, ins);
2571  return fail ? XTENSA_ISA_BADPC : ia;
2572 }
2573 
2574 /* Initialize frame cache for the current frame in CALL0 ABI. */
2575 
2576 static void
2577 call0_frame_cache (struct frame_info *this_frame,
2579 {
2580  struct gdbarch *gdbarch = get_frame_arch (this_frame);
2581  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2582  CORE_ADDR start_pc; /* The beginning of the function. */
2583  CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
2584  CORE_ADDR sp, fp, ra;
2585  int fp_regnum = C0_SP, c0_hasfp = 0, c0_frmsz = 0, prev_sp = 0, to_stk;
2586 
2588  (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
2589  fp = sp; /* Assume FP == SP until proven otherwise. */
2590 
2591  /* Find the beginning of the prologue of the function containing the PC
2592  and analyze it up to the PC or the end of the prologue. */
2593 
2594  if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
2595  {
2596  body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, C0_NREGS, cache);
2597 
2598  if (body_pc == XTENSA_ISA_BADPC)
2599  {
2600  warning_once ();
2601  ra = 0;
2602  goto finish_frame_analysis;
2603  }
2604  }
2605 
2606  /* Get the frame information and FP (if used) at the current PC.
2607  If PC is in the prologue, the prologue analysis is more reliable
2608  than DWARF info. We don't not know for sure, if PC is in the prologue,
2609  but we do know no calls have yet taken place, so we can almost
2610  certainly rely on the prologue analysis. */
2611 
2612  if (body_pc <= pc)
2613  {
2614  /* Prologue analysis was successful up to the PC.
2615  It includes the cases when PC == START_PC. */
2616  c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP;
2617  /* c0_hasfp == true means there is a frame pointer because
2618  we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2619  was derived from SP. Otherwise, it would be C0_FP. */
2620  fp_regnum = c0_hasfp ? C0_FP : C0_SP;
2621  c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs;
2622  fp_regnum += gdbarch_tdep (gdbarch)->a0_base;
2623  }
2624  else /* No data from the prologue analysis. */
2625  {
2626  c0_hasfp = 0;
2627  fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP;
2628  c0_frmsz = 0;
2629  start_pc = pc;
2630  }
2631 
2632  if (cache->c0.c0_fpalign)
2633  {
2634  /* This frame has a special prologue with a dynamic stack adjustment
2635  to force an alignment, which is bigger than standard 16 bytes. */
2636 
2637  CORE_ADDR unaligned_sp;
2638 
2639  if (cache->c0.c0_old_sp == C0_INEXP)
2640  /* This can't be. Prologue code should be consistent.
2641  Unaligned stack pointer should be saved in a spare register. */
2642  {
2643  warning_once ();
2644  ra = 0;
2645  goto finish_frame_analysis;
2646  }
2647 
2648  if (cache->c0.c0_sp_ofs == C0_NOSTK)
2649  /* Saved unaligned value of SP is kept in a register. */
2650  unaligned_sp = get_frame_register_unsigned
2651  (this_frame, gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_old_sp);
2652  else
2653  /* Get the value from stack. */
2654  unaligned_sp = (CORE_ADDR)
2655  read_memory_integer (fp + cache->c0.c0_sp_ofs, 4, byte_order);
2656 
2657  prev_sp = unaligned_sp + c0_frmsz;
2658  }
2659  else
2660  prev_sp = fp + c0_frmsz;
2661 
2662  /* Frame size from debug info or prologue tracking does not account for
2663  alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2664  if (c0_hasfp)
2665  {
2666  fp = get_frame_register_unsigned (this_frame, fp_regnum);
2667 
2668  /* Update the stack frame size. */
2669  c0_frmsz += fp - sp;
2670  }
2671 
2672  /* Get the return address (RA) from the stack if saved,
2673  or try to get it from a register. */
2674 
2675  to_stk = cache->c0.c0_rt[C0_RA].to_stk;
2676  if (to_stk != C0_NOSTK)
2677  ra = (CORE_ADDR)
2678  read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk,
2679  4, byte_order);
2680 
2681  else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
2682  && cache->c0.c0_rt[C0_RA].fr_ofs == 0)
2683  {
2684  /* Special case for terminating backtrace at a function that wants to
2685  be seen as the outermost one. Such a function will clear it's RA (A0)
2686  register to 0 in the prologue instead of saving its original value. */
2687  ra = 0;
2688  }
2689  else
2690  {
2691  /* RA was copied to another register or (before any function call) may
2692  still be in the original RA register. This is not always reliable:
2693  even in a leaf function, register tracking stops after prologue, and
2694  even in prologue, non-prologue instructions (not tracked) may overwrite
2695  RA or any register it was copied to. If likely in prologue or before
2696  any call, use retracking info and hope for the best (compiler should
2697  have saved RA in stack if not in a leaf function). If not in prologue,
2698  too bad. */
2699 
2700  int i;
2701  for (i = 0;
2702  (i < C0_NREGS)
2703  && (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
2704  ++i);
2705  if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA)
2706  i = C0_RA;
2707  if (i < C0_NREGS)
2708  {
2710  (this_frame,
2711  gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_rt[i].fr_reg);
2712  }
2713  else ra = 0;
2714  }
2715 
2716  finish_frame_analysis:
2717  cache->pc = start_pc;
2718  cache->ra = ra;
2719  /* RA == 0 marks the outermost frame. Do not go past it. */
2720  cache->prev_sp = (ra != 0) ? prev_sp : 0;
2721  cache->c0.fp_regnum = fp_regnum;
2722  cache->c0.c0_frmsz = c0_frmsz;
2723  cache->c0.c0_hasfp = c0_hasfp;
2724  cache->c0.c0_fp = fp;
2725 }
2726 
2730 static int a0_was_saved;
2731 static int a7_was_saved;
2732 static int a11_was_saved;
2733 
2734 /* Simulate L32E instruction: AT <-- ref (AS + offset). */
2735 static void
2736 execute_l32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
2737 {
2738  int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb);
2739  int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb);
2740  CORE_ADDR addr = xtensa_read_register (asreg) + offset;
2741  unsigned int spilled_value
2742  = read_memory_unsigned_integer (addr, 4, gdbarch_byte_order (gdbarch));
2743 
2744  if ((at == 0) && !a0_was_saved)
2745  {
2746  a0_saved = xtensa_read_register (atreg);
2747  a0_was_saved = 1;
2748  }
2749  else if ((at == 7) && !a7_was_saved)
2750  {
2751  a7_saved = xtensa_read_register (atreg);
2752  a7_was_saved = 1;
2753  }
2754  else if ((at == 11) && !a11_was_saved)
2755  {
2756  a11_saved = xtensa_read_register (atreg);
2757  a11_was_saved = 1;
2758  }
2759 
2760  xtensa_write_register (atreg, spilled_value);
2761 }
2762 
2763 /* Simulate S32E instruction: AT --> ref (AS + offset). */
2764 static void
2765 execute_s32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
2766 {
2767  int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb);
2768  int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb);
2769  CORE_ADDR addr = xtensa_read_register (asreg) + offset;
2770  ULONGEST spilled_value = xtensa_read_register (atreg);
2771 
2773  gdbarch_byte_order (gdbarch),
2774  spilled_value);
2775 }
2776 
2777 #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
2778 
2779 typedef enum
2780 {
2785 
2786 /* Execute instruction stream from current PC until hitting RFWU or RFWO.
2787  Return type of Xtensa Window Interrupt Handler on success. */
2789 execute_code (struct gdbarch *gdbarch, CORE_ADDR current_pc, CORE_ADDR wb)
2790 {
2791  xtensa_isa isa;
2792  xtensa_insnbuf ins, slot;
2793  gdb_byte ibuf[XTENSA_ISA_BSZ];
2794  CORE_ADDR ia, bt, ba;
2795  xtensa_format ifmt;
2796  int ilen, islots, is;
2797  xtensa_opcode opc;
2798  int insn_num = 0;
2799  int fail = 0;
2800  void (*func) (struct gdbarch *, int, int, int, CORE_ADDR);
2801 
2802  uint32_t at, as, offset;
2803 
2804  /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */
2805  int WindowUnderflow12 = (current_pc & 0x1ff) >= 0x140;
2806 
2807  isa = xtensa_default_isa;
2808  gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2809  ins = xtensa_insnbuf_alloc (isa);
2810  slot = xtensa_insnbuf_alloc (isa);
2811  ba = 0;
2812  ia = current_pc;
2813  bt = ia;
2814 
2815  a0_was_saved = 0;
2816  a7_was_saved = 0;
2817  a11_was_saved = 0;
2818 
2819  while (insn_num++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN)
2820  {
2821  if (ia + xtensa_isa_maxlength (isa) > bt)
2822  {
2823  ba = ia;
2824  bt = (ba + XTENSA_ISA_BSZ);
2825  if (target_read_memory (ba, ibuf, bt - ba) != 0)
2826  return xtNoExceptionHandler;
2827  }
2828  xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2829  ifmt = xtensa_format_decode (isa, ins);
2830  if (ifmt == XTENSA_UNDEFINED)
2831  return xtNoExceptionHandler;
2832  ilen = xtensa_format_length (isa, ifmt);
2833  if (ilen == XTENSA_UNDEFINED)
2834  return xtNoExceptionHandler;
2835  islots = xtensa_format_num_slots (isa, ifmt);
2836  if (islots == XTENSA_UNDEFINED)
2837  return xtNoExceptionHandler;
2838  for (is = 0; is < islots; ++is)
2839  {
2840  if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2841  return xtNoExceptionHandler;
2842  opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2843  if (opc == XTENSA_UNDEFINED)
2844  return xtNoExceptionHandler;
2845  switch (call0_classify_opcode (isa, opc))
2846  {
2847  case c0opc_illegal:
2848  case c0opc_flow:
2849  case c0opc_entry:
2850  case c0opc_break:
2851  /* We expect none of them here. */
2852  return xtNoExceptionHandler;
2853  case c0opc_l32e:
2854  func = execute_l32e;
2855  break;
2856  case c0opc_s32e:
2857  func = execute_s32e;
2858  break;
2859  case c0opc_rfwo: /* RFWO. */
2860  /* Here, we return from WindowOverflow handler and,
2861  if we stopped at the very beginning, which means
2862  A0 was saved, we have to restore it now. */
2863  if (a0_was_saved)
2864  {
2865  int arreg = arreg_number (gdbarch,
2866  gdbarch_tdep (gdbarch)->a0_base,
2867  wb);
2869  }
2870  return xtWindowOverflow;
2871  case c0opc_rfwu: /* RFWU. */
2872  /* Here, we return from WindowUnderflow handler.
2873  Let's see if either A7 or A11 has to be restored. */
2874  if (WindowUnderflow12)
2875  {
2876  if (a11_was_saved)
2877  {
2878  int arreg = arreg_number (gdbarch,
2879  gdbarch_tdep (gdbarch)->a0_base + 11,
2880  wb);
2882  }
2883  }
2884  else if (a7_was_saved)
2885  {
2886  int arreg = arreg_number (gdbarch,
2887  gdbarch_tdep (gdbarch)->a0_base + 7,
2888  wb);
2890  }
2891  return xtWindowUnderflow;
2892  default: /* Simply skip this insns. */
2893  continue;
2894  }
2895 
2896  /* Decode arguments for L32E / S32E and simulate their execution. */
2897  if ( xtensa_opcode_num_operands (isa, opc) != 3 )
2898  return xtNoExceptionHandler;
2899  if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, &at))
2900  return xtNoExceptionHandler;
2901  if (xtensa_operand_decode (isa, opc, 0, &at))
2902  return xtNoExceptionHandler;
2903  if (xtensa_operand_get_field (isa, opc, 1, ifmt, is, slot, &as))
2904  return xtNoExceptionHandler;
2905  if (xtensa_operand_decode (isa, opc, 1, &as))
2906  return xtNoExceptionHandler;
2907  if (xtensa_operand_get_field (isa, opc, 2, ifmt, is, slot, &offset))
2908  return xtNoExceptionHandler;
2909  if (xtensa_operand_decode (isa, opc, 2, &offset))
2910  return xtNoExceptionHandler;
2911 
2912  (*func) (gdbarch, at, as, offset, wb);
2913  }
2914 
2915  ia += ilen;
2916  }
2917  return xtNoExceptionHandler;
2918 }
2919 
2920 /* Handle Window Overflow / Underflow exception frames. */
2921 
2922 static void
2924  xtensa_frame_cache_t *cache,
2925  CORE_ADDR pc)
2926 {
2927  struct gdbarch *gdbarch = get_frame_arch (this_frame);
2928  CORE_ADDR ps, wb, ws, ra;
2929  int epc1_regnum, i, regnum;
2931 
2932  /* Read PS, WB, and WS from the hardware. Note that PS register
2933  must be present, if Windowed ABI is supported. */
2934  ps = xtensa_read_register (gdbarch_ps_regnum (gdbarch));
2935  wb = xtensa_read_register (gdbarch_tdep (gdbarch)->wb_regnum);
2936  ws = xtensa_read_register (gdbarch_tdep (gdbarch)->ws_regnum);
2937 
2938  /* Execute all the remaining instructions from Window Interrupt Handler
2939  by simulating them on the remote protocol level. On return, set the
2940  type of Xtensa Window Interrupt Handler, or report an error. */
2941  eh_type = execute_code (gdbarch, pc, wb);
2942  if (eh_type == xtNoExceptionHandler)
2943  error (_("\
2944 Unable to decode Xtensa Window Interrupt Handler's code."));
2945 
2946  cache->ps = ps ^ PS_EXC; /* Clear the exception bit in PS. */
2947  cache->call0 = 0; /* It's Windowed ABI. */
2948 
2949  /* All registers for the cached frame will be alive. */
2950  for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
2951  cache->wd.aregs[i] = -1;
2952 
2953  if (eh_type == xtWindowOverflow)
2954  cache->wd.ws = ws ^ (1 << wb);
2955  else /* eh_type == xtWindowUnderflow. */
2956  cache->wd.ws = ws | (1 << wb);
2957 
2958  cache->wd.wb = (ps & 0xf00) >> 8; /* Set WB to OWB. */
2959  regnum = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base,
2960  cache->wd.wb);
2961  ra = xtensa_read_register (regnum);
2962  cache->wd.callsize = WINSIZE (ra);
2963  cache->prev_sp = xtensa_read_register (regnum + 1);
2964  /* Set regnum to a frame pointer of the frame being cached. */
2965  regnum = xtensa_scan_prologue (gdbarch, pc);
2966  regnum = arreg_number (gdbarch,
2967  gdbarch_tdep (gdbarch)->a0_base + regnum,
2968  cache->wd.wb);
2969  cache->base = get_frame_register_unsigned (this_frame, regnum);
2970 
2971  /* Read PC of interrupted function from EPC1 register. */
2972  epc1_regnum = xtensa_find_register_by_name (gdbarch,"epc1");
2973  if (epc1_regnum < 0)
2974  error(_("Unable to read Xtensa register EPC1"));
2975  cache->ra = xtensa_read_register (epc1_regnum);
2976  cache->pc = get_frame_func (this_frame);
2977 }
2978 
2979 
2980 /* Skip function prologue.
2981 
2982  Return the pc of the first instruction after prologue. GDB calls this to
2983  find the address of the first line of the function or (if there is no line
2984  number information) to skip the prologue for planting breakpoints on
2985  function entries. Use debug info (if present) or prologue analysis to skip
2986  the prologue to achieve reliable debugging behavior. For windowed ABI,
2987  only the 'entry' instruction is skipped. It is not strictly necessary to
2988  skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2989  backtrace at any point in the prologue, however certain potential hazards
2990  are avoided and a more "normal" debugging experience is ensured by
2991  skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2992  For example, if we don't skip the prologue:
2993  - Some args may not yet have been saved to the stack where the debug
2994  info expects to find them (true anyway when only 'entry' is skipped);
2995  - Software breakpoints ('break' instrs) may not have been unplanted
2996  when the prologue analysis is done on initializing the frame cache,
2997  and breaks in the prologue will throw off the analysis.
2998 
2999  If we have debug info ( line-number info, in particular ) we simply skip
3000  the code associated with the first function line effectively skipping
3001  the prologue code. It works even in cases like
3002 
3003  int main()
3004  { int local_var = 1;
3005  ....
3006  }
3007 
3008  because, for this source code, both Xtensa compilers will generate two
3009  separate entries ( with the same line number ) in dwarf line-number
3010  section to make sure there is a boundary between the prologue code and
3011  the rest of the function.
3012 
3013  If there is no debug info, we need to analyze the code. */
3014 
3015 /* #define DONT_SKIP_PROLOGUE */
3016 
3017 static CORE_ADDR
3018 xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
3019 {
3020  struct symtab_and_line prologue_sal;
3021  CORE_ADDR body_pc;
3022 
3023  DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc);
3024 
3025 #if DONT_SKIP_PROLOGUE
3026  return start_pc;
3027 #endif
3028 
3029  /* Try to find first body line from debug info. */
3030 
3031  prologue_sal = find_pc_line (start_pc, 0);
3032  if (prologue_sal.line != 0) /* Found debug info. */
3033  {
3034  /* In Call0, it is possible to have a function with only one instruction
3035  ('ret') resulting from a one-line optimized function that does nothing.
3036  In that case, prologue_sal.end may actually point to the start of the
3037  next function in the text section, causing a breakpoint to be set at
3038  the wrong place. Check, if the end address is within a different
3039  function, and if so return the start PC. We know we have symbol
3040  information. */
3041 
3042  CORE_ADDR end_func;
3043 
3044  if ((gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only)
3045  && call0_ret (start_pc, prologue_sal.end))
3046  return start_pc;
3047 
3048  find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL);
3049  if (end_func != start_pc)
3050  return start_pc;
3051 
3052  return prologue_sal.end;
3053  }
3054 
3055  /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
3056  body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0,
3058  return body_pc != 0 ? body_pc : start_pc;
3059 }
3060 
3061 /* Verify the current configuration. */
3062 static void
3063 xtensa_verify_config (struct gdbarch *gdbarch)
3064 {
3065  struct ui_file *log;
3066  struct cleanup *cleanups;
3067  struct gdbarch_tdep *tdep;
3068  long length;
3069  char *buf;
3070 
3071  tdep = gdbarch_tdep (gdbarch);
3072  log = mem_fileopen ();
3073  cleanups = make_cleanup_ui_file_delete (log);
3074 
3075  /* Verify that we got a reasonable number of AREGS. */
3076  if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs)
3077  fprintf_unfiltered (log, _("\
3078 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
3079  tdep->num_aregs);
3080 
3081  /* Verify that certain registers exist. */
3082 
3083  if (tdep->pc_regnum == -1)
3084  fprintf_unfiltered (log, _("\n\tpc_regnum: No PC register"));
3085  if (tdep->isa_use_exceptions && tdep->ps_regnum == -1)
3086  fprintf_unfiltered (log, _("\n\tps_regnum: No PS register"));
3087 
3088  if (tdep->isa_use_windowed_registers)
3089  {
3090  if (tdep->wb_regnum == -1)
3091  fprintf_unfiltered (log, _("\n\twb_regnum: No WB register"));
3092  if (tdep->ws_regnum == -1)
3093  fprintf_unfiltered (log, _("\n\tws_regnum: No WS register"));
3094  if (tdep->ar_base == -1)
3095  fprintf_unfiltered (log, _("\n\tar_base: No AR registers"));
3096  }
3097 
3098  if (tdep->a0_base == -1)
3099  fprintf_unfiltered (log, _("\n\ta0_base: No Ax registers"));
3100 
3101  buf = ui_file_xstrdup (log, &length);
3102  make_cleanup (xfree, buf);
3103  if (length > 0)
3104  internal_error (__FILE__, __LINE__,
3105  _("the following are invalid: %s"), buf);
3106  do_cleanups (cleanups);
3107 }
3108 
3109 
3110 /* Derive specific register numbers from the array of registers. */
3111 
3112 static void
3114 {
3116  int n, max_size = 4;
3117 
3118  tdep->num_regs = 0;
3119  tdep->num_nopriv_regs = 0;
3120 
3121 /* Special registers 0..255 (core). */
3122 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
3123 
3124  for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++)
3125  {
3126  if (rmap->target_number == 0x0020)
3127  tdep->pc_regnum = n;
3128  else if (rmap->target_number == 0x0100)
3129  tdep->ar_base = n;
3130  else if (rmap->target_number == 0x0000)
3131  tdep->a0_base = n;
3132  else if (rmap->target_number == XTENSA_DBREGN_SREG(72))
3133  tdep->wb_regnum = n;
3134  else if (rmap->target_number == XTENSA_DBREGN_SREG(73))
3135  tdep->ws_regnum = n;
3136  else if (rmap->target_number == XTENSA_DBREGN_SREG(233))
3137  tdep->debugcause_regnum = n;
3138  else if (rmap->target_number == XTENSA_DBREGN_SREG(232))
3139  tdep->exccause_regnum = n;
3140  else if (rmap->target_number == XTENSA_DBREGN_SREG(238))
3141  tdep->excvaddr_regnum = n;
3142  else if (rmap->target_number == XTENSA_DBREGN_SREG(0))
3143  tdep->lbeg_regnum = n;
3144  else if (rmap->target_number == XTENSA_DBREGN_SREG(1))
3145  tdep->lend_regnum = n;
3146  else if (rmap->target_number == XTENSA_DBREGN_SREG(2))
3147  tdep->lcount_regnum = n;
3148  else if (rmap->target_number == XTENSA_DBREGN_SREG(3))
3149  tdep->sar_regnum = n;
3150  else if (rmap->target_number == XTENSA_DBREGN_SREG(5))
3151  tdep->litbase_regnum = n;
3152  else if (rmap->target_number == XTENSA_DBREGN_SREG(230))
3153  tdep->ps_regnum = n;
3154 #if 0
3155  else if (rmap->target_number == XTENSA_DBREGN_SREG(226))
3156  tdep->interrupt_regnum = n;
3157  else if (rmap->target_number == XTENSA_DBREGN_SREG(227))
3158  tdep->interrupt2_regnum = n;
3159  else if (rmap->target_number == XTENSA_DBREGN_SREG(224))
3160  tdep->cpenable_regnum = n;
3161 #endif
3162 
3163  if (rmap->byte_size > max_size)
3164  max_size = rmap->byte_size;
3165  if (rmap->mask != 0 && tdep->num_regs == 0)
3166  tdep->num_regs = n;
3167  /* Find out out how to deal with priveleged registers.
3168 
3169  if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3170  && tdep->num_nopriv_regs == 0)
3171  tdep->num_nopriv_regs = n;
3172  */
3173  if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3174  && tdep->num_regs == 0)
3175  tdep->num_regs = n;
3176  }
3177 
3178  /* Number of pseudo registers. */
3179  tdep->num_pseudo_regs = n - tdep->num_regs;
3180 
3181  /* Empirically determined maximum sizes. */
3182  tdep->max_register_raw_size = max_size;
3183  tdep->max_register_virtual_size = max_size;
3184 }
3185 
3186 /* Module "constructor" function. */
3187 
3188 extern struct gdbarch_tdep xtensa_tdep;
3189 
3190 static struct gdbarch *
3191 xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3192 {
3193  struct gdbarch_tdep *tdep;
3194  struct gdbarch *gdbarch;
3195  struct xtensa_abi_handler *abi_handler;
3196 
3197  DEBUGTRACE ("gdbarch_init()\n");
3198 
3199  /* We have to set the byte order before we call gdbarch_alloc. */
3200  info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
3201 
3202  tdep = &xtensa_tdep;
3203  gdbarch = gdbarch_alloc (&info, tdep);
3204  xtensa_derive_tdep (tdep);
3205 
3206  /* Verify our configuration. */
3207  xtensa_verify_config (gdbarch);
3209 
3210  /* Pseudo-Register read/write. */
3213 
3214  /* Set target information. */
3215  set_gdbarch_num_regs (gdbarch, tdep->num_regs);
3217  set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1);
3218  set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum);
3219  set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum);
3220 
3221  /* Renumber registers for known formats (stabs and dwarf2). */
3224 
3225  /* We provide our own function to get register information. */
3228 
3229  /* To call functions from GDB using dummy frame. */
3231 
3232  set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3233 
3235 
3236  /* Advance PC across any prologue instructions to reach "real" code. */
3238 
3239  /* Stack grows downward. */
3241 
3242  /* Set breakpoints. */
3244 
3245  /* After breakpoint instruction or illegal instruction, pc still
3246  points at break instruction, so don't decrement. */
3247  set_gdbarch_decr_pc_after_break (gdbarch, 0);
3248 
3249  /* We don't skip args. */
3250  set_gdbarch_frame_args_skip (gdbarch, 0);
3251 
3253 
3255 
3257 
3258  /* Frame handling. */
3259  frame_base_set_default (gdbarch, &xtensa_frame_base);
3260  frame_unwind_append_unwinder (gdbarch, &xtensa_unwind);
3261  dwarf2_append_unwinders (gdbarch);
3262 
3263  set_gdbarch_print_insn (gdbarch, print_insn_xtensa);
3264 
3266 
3267  xtensa_add_reggroups (gdbarch);
3269 
3272 
3275 
3276  return gdbarch;
3277 }
3278 
3279 static void
3280 xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3281 {
3282  error (_("xtensa_dump_tdep(): not implemented"));
3283 }
3284 
3285 /* Provide a prototype to silence -Wmissing-prototypes. */
3287 
3288 void
3290 {
3291  struct cmd_list_element *c;
3292 
3295 
3296  add_setshow_zuinteger_cmd ("xtensa",
3299  _("Set Xtensa debugging."),
3300  _("Show Xtensa debugging."), _("\
3301 When non-zero, Xtensa-specific debugging is enabled. \
3302 Can be 1, 2, 3, or 4 indicating the level of debugging."),
3303  NULL,
3304  NULL,
3306 }
struct xtensa_frame_cache xtensa_frame_cache_t
void reggroup_add(struct gdbarch *gdbarch, struct reggroup *group)
Definition: reggroups.c:103
void set_gdbarch_num_regs(struct gdbarch *gdbarch, int num_regs)
Definition: gdbarch.c:1909
void set_gdbarch_frame_align(struct gdbarch *gdbarch, gdbarch_frame_align_ftype frame_align)
Definition: gdbarch.c:2935
void set_gdbarch_have_nonsteppable_watchpoint(struct gdbarch *gdbarch, int have_nonsteppable_watchpoint)
Definition: gdbarch.c:3261
#define DEBUGINFO(args...)
Definition: xtensa-tdep.c:62
ULONGEST extract_unsigned_integer(const gdb_byte *, int, enum bfd_endian)
Definition: findvar.c:84
static enum register_status xtensa_register_read_masked(struct regcache *regcache, xtensa_register_t *reg, gdb_byte *buffer)
Definition: xtensa-tdep.c:453
xtensa_isa xtensa_default_isa
void set_gdbarch_ps_regnum(struct gdbarch *gdbarch, int ps_regnum)
Definition: gdbarch.c:2025
static enum return_value_convention xtensa_return_value(struct gdbarch *gdbarch, struct value *function, struct type *valtype, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf)
Definition: xtensa-tdep.c:1668
static CORE_ADDR xtensa_frame_base_address(struct frame_info *this_frame, void **this_cache)
Definition: xtensa-tdep.c:1543
struct frame_id frame_id_build(CORE_ADDR stack_addr, CORE_ADDR code_addr)
Definition: frame.c:554
CORE_ADDR extract_typed_address(const gdb_byte *buf, struct type *type)
Definition: findvar.c:169
static int xtensa_find_register_by_name(struct gdbarch *gdbarch, char *name)
Definition: xtensa-tdep.c:229
static int rwx_special_register(const char *opcname)
Definition: xtensa-tdep.c:2112
struct type * virtual_type
Definition: xtensa-tdep.h:169
#define CALLINC(ps)
Definition: xtensa-tdep.c:88
CORE_ADDR get_frame_pc(struct frame_info *frame)
Definition: frame.c:2217
static int a7_was_saved
Definition: xtensa-tdep.c:2731
#define SP_ALIGNMENT
Definition: xtensa-tdep.c:76
void add_setshow_zuinteger_cmd(const char *name, enum command_class theclass, unsigned int *var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_sfunc_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
Definition: cli-decode.c:763
#define PS_WOE
Definition: xtensa-tdep.c:118
bfd_vma CORE_ADDR
Definition: common-types.h:41
struct reggroup * reggroup_new(const char *name, enum reggroup_type type)
Definition: reggroups.c:39
#define C0_RA
Definition: xtensa-tdep.c:948
void xfree(void *)
Definition: common-utils.c:97
static void xtensa_supply_gregset(const struct regset *regset, struct regcache *rc, int regnum, const void *gregs, size_t len)
Definition: xtensa-tdep.c:846
static int windowing_enabled(struct gdbarch *gdbarch, unsigned int ps)
Definition: xtensa-tdep.c:122
xtensa_insn_kind
Definition: xtensa-tdep.c:2086
#define C0_NOSTK
Definition: xtensa-tdep.c:961
struct gdbarch * get_regcache_arch(const struct regcache *regcache)
Definition: regcache.c:297
struct value * frame_unwind_got_memory(struct frame_info *frame, int regnum, CORE_ADDR addr)
Definition: frame-unwind.c:228
void write_memory_unsigned_integer(CORE_ADDR addr, int len, enum bfd_endian byte_order, ULONGEST value)
Definition: corefile.c:412
void(* func)(char *)
if(!(yy_init))
Definition: ada-lex.c:1072
struct xtensa_call0_frame_cache xtensa_call0_frame_cache_t
static struct xtensa_frame_cache * xtensa_alloc_frame_cache(int windowed)
Definition: xtensa-tdep.c:1010
void warning(const char *fmt,...)
Definition: errors.c:26
CORE_ADDR end
Definition: symtab.h:1377
#define DENSITY_BIG_BREAKPOINT
Definition: xtensa-tdep.c:1968
void set_gdbarch_stab_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_stab_reg_to_regnum_ftype stab_reg_to_regnum)
Definition: gdbarch.c:2059
xtensa_elf_greg_t ar[64]
Definition: xtensa-tdep.h:100
char * ui_file_xstrdup(struct ui_file *file, long *length)
Definition: ui-file.c:345
ULONGEST align_down(ULONGEST v, int n)
Definition: utils.c:2971
xtensa_elf_greg_t ps
Definition: xtensa-tdep.h:92
const struct builtin_type * builtin_type(struct gdbarch *gdbarch)
Definition: gdbtypes.c:4766
struct gdbarch_tdep xtensa_tdep
unsigned int isa_use_windowed_registers
Definition: xtensa-tdep.h:194
#define REGISTER_SIZE
Definition: xtensa-tdep.c:82
void internal_error(const char *file, int line, const char *fmt,...)
Definition: errors.c:50
static struct xtensa_frame_cache * xtensa_frame_cache(struct frame_info *this_frame, void **this_cache)
Definition: xtensa-tdep.c:1263
void frame_unwind_register(struct frame_info *frame, int regnum, gdb_byte *buf)
Definition: frame.c:1065
static int arreg_number(struct gdbarch *gdbarch, int a_regnum, ULONGEST wb)
Definition: xtensa-tdep.c:134
int interrupt_regnum
Definition: xtensa-tdep.h:224
#define TX_PS
Definition: xtensa-tdep.c:94
struct m32c_reg * pc
Definition: m32c-tdep.c:111
return_value_convention
Definition: defs.h:206
static int xtensa_register_reggroup_p(struct gdbarch *gdbarch, int regnum, struct reggroup *group)
Definition: xtensa-tdep.c:797
struct type * builtin_uint8
Definition: gdbtypes.h:1515
static int extract_call_winsize(struct gdbarch *gdbarch, CORE_ADDR pc)
Definition: xtensa-tdep.c:190
#define PS_CALLINC_SHIFT
Definition: xtensa-tdep.c:86
static CORE_ADDR xtensa_skip_prologue(struct gdbarch *gdbarch, CORE_ADDR start_pc)
Definition: xtensa-tdep.c:3018
struct type * builtin_uint16
Definition: gdbtypes.h:1517
void set_gdbarch_register_reggroup_p(struct gdbarch *gdbarch, gdbarch_register_reggroup_p_ftype register_reggroup_p)
Definition: gdbarch.c:3350
#define BIG_BREAKPOINT
Definition: xtensa-tdep.c:1966
xtensa_register_t * regmap
Definition: xtensa-tdep.h:204
static enum register_status xtensa_pseudo_register_read(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, gdb_byte *buffer)
Definition: xtensa-tdep.c:546
struct link_map_offsets * svr4_ilp32_fetch_link_map_offsets(void)
Definition: solib-svr4.c:3149
static unsigned int xtensa_scan_prologue(struct gdbarch *gdbarch, CORE_ADDR current_pc)
Definition: xtensa-tdep.c:1134
xtensa_call0_frame_cache_t c0
Definition: xtensa-tdep.c:1004
struct xtensa_c0reg xtensa_c0reg_t
static struct reggroup * xtensa_user_reggroup
Definition: xtensa-tdep.c:733
xtensa_elf_greg_t lbeg
Definition: xtensa-tdep.h:93
static struct type * xtensa_register_type(struct gdbarch *gdbarch, int regnum)
Definition: xtensa-tdep.c:259
struct reggroup *const restore_reggroup
Definition: reggroups.c:298
int gdbarch_num_regs(struct gdbarch *gdbarch)
Definition: gdbarch.c:1898
xtensa_windowed_frame_cache_t wd
Definition: xtensa-tdep.c:1003
struct reggroup *const all_reggroup
Definition: reggroups.c:296
xtensa_elf_greg_t lend
Definition: xtensa-tdep.h:94
#define _(String)
Definition: gdb_locale.h:40
static struct reggroup * xtensa_vectra_reggroup
Definition: xtensa-tdep.c:734
static int regmap[]
void set_gdbarch_dwarf2_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_dwarf2_reg_to_regnum_ftype dwarf2_reg_to_regnum)
Definition: gdbarch.c:2110
#define RETURN_RET
struct gdbarch_tdep * gdbarch_tdep(struct gdbarch *gdbarch)
Definition: gdbarch.c:1402
int gdbarch_ps_regnum(struct gdbarch *gdbarch)
Definition: gdbarch.c:2015
#define C0_SP
Definition: xtensa-tdep.c:946
void frame_unwind_append_unwinder(struct gdbarch *gdbarch, const struct frame_unwind *unwinder)
Definition: frame-unwind.c:78
int max_register_virtual_size
Definition: xtensa-tdep.h:232
#define ARG_1ST(gdbarch)
Definition: xtensa-tdep.c:100
struct regcache * get_current_regcache(void)
Definition: regcache.c:541
tuple m
Definition: arm-linux.py:44
#define XTENSA_MAX_COPROCESSOR
Definition: xtensa-tdep.h:45
#define FRAME_OBSTACK_ZALLOC(TYPE)
Definition: frame.h:660
void store_unsigned_integer(gdb_byte *, int, enum bfd_endian, ULONGEST)
Definition: findvar.c:212
int ps_regnum
Definition: gdbarch.c:194
struct ctype_cache * next
Definition: xtensa-tdep.h:167
static struct reggroup * xtensa_ar_reggroup
Definition: xtensa-tdep.c:732
struct value * frame_unwind_got_constant(struct frame_info *frame, int regnum, ULONGEST val)
Definition: frame-unwind.c:241
void gdbarch_register(enum bfd_architecture bfd_architecture, gdbarch_init_ftype *init, gdbarch_dump_tdep_ftype *dump_tdep)
Definition: gdbarch.c:4933
Definition: regset.h:34
static void warning_once(void)
Definition: xtensa-tdep.c:1416
mach_port_t kern_return_t mach_port_t msgports mach_port_t kern_return_t pid_t pid mach_port_t kern_return_t mach_port_t task mach_port_t kern_return_t int flags
Definition: gnu-nat.c:1885
int gdbarch_num_pseudo_regs(struct gdbarch *gdbarch)
Definition: gdbarch.c:1916
struct type * ctype
Definition: xtensa-tdep.h:130
struct reggroup *const float_reggroup
Definition: reggroups.c:293
void frame_base_set_default(struct gdbarch *gdbarch, const struct frame_base *default_base)
Definition: frame-base.c:94
const char *const name
Definition: aarch64-tdep.c:68
void set_gdbarch_pseudo_register_write(struct gdbarch *gdbarch, gdbarch_pseudo_register_write_ftype pseudo_register_write)
Definition: gdbarch.c:1891
static CORE_ADDR xtensa_unwind_pc(struct gdbarch *gdbarch, struct frame_info *next_frame)
Definition: xtensa-tdep.c:1063
#define SAVE_REST_FLAGS
Definition: xtensa-tdep.c:789
static void xtensa_iterate_over_regset_sections(struct gdbarch *gdbarch, iterate_over_regset_sections_cb *cb, void *cb_data, const struct regcache *regcache)
Definition: xtensa-tdep.c:908
void set_gdbarch_register_type(struct gdbarch *gdbarch, gdbarch_register_type_ftype register_type)
Definition: gdbarch.c:2151
struct type * check_typedef(struct type *type)
Definition: gdbtypes.c:2217
LONGEST read_memory_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition: corefile.c:311
unsigned int isa_use_exceptions
Definition: xtensa-tdep.h:196
const gdb_byte * value_contents(struct value *value)
Definition: value.c:1329
struct reggroup *const general_reggroup
Definition: reggroups.c:292
enum register_status regcache_raw_read_part(struct regcache *regcache, int regnum, int offset, int len, gdb_byte *buf)
Definition: regcache.c:995
static void xtensa_add_reggroups(struct gdbarch *gdbarch)
Definition: xtensa-tdep.c:755
#define C0_CONST
Definition: xtensa-tdep.c:959
unsigned int num_aregs
Definition: xtensa-tdep.h:209
void initialize_file_ftype(void)
Definition: defs.h:281
struct symtab_and_line find_pc_line(CORE_ADDR pc, int notcurrent)
Definition: symtab.c:3315
static void xtensa_derive_tdep(struct gdbarch_tdep *tdep)
Definition: xtensa-tdep.c:3113
#define UINT_MAX
Definition: defs.h:505
int exccause_regnum
Definition: xtensa-tdep.h:228
register_status
Definition: regcache.h:50
#define XTENSA_DBREGN_SREG(n)
enum register_status regcache_cooked_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition: regcache.c:837
struct reggroup *const system_reggroup
Definition: reggroups.c:294
void set_gdbarch_sp_regnum(struct gdbarch *gdbarch, int sp_regnum)
Definition: gdbarch.c:1991
static const char * xtensa_register_name(struct gdbarch *gdbarch, int regnum)
Definition: xtensa-tdep.c:245
void set_gdbarch_decr_pc_after_break(struct gdbarch *gdbarch, CORE_ADDR decr_pc_after_break)
Definition: gdbarch.c:2764
xtensa_elf_greg_t windowstart
Definition: xtensa-tdep.h:97
void set_gdbarch_dummy_id(struct gdbarch *gdbarch, gdbarch_dummy_id_ftype dummy_id)
Definition: gdbarch.c:2175
void fprintf_unfiltered(struct ui_file *stream, const char *format,...)
Definition: utils.c:2361
mach_port_t mach_port_t name mach_port_t mach_port_t name error_t int status
Definition: gnu-nat.c:1816
static CORE_ADDR xtensa_push_dummy_call(struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr)
Definition: xtensa-tdep.c:1704
struct_return
Definition: arm-tdep.h:148
void set_gdbarch_believe_pcc_promotion(struct gdbarch *gdbarch, int believe_pcc_promotion)
Definition: gdbarch.c:2406
xtensa_exception_handler_t
Definition: xtensa-tdep.c:2779
xtensa_register_type_t
Definition: xtensa-tdep.h:28
enum bfd_endian gdbarch_byte_order(struct gdbarch *gdbarch)
Definition: gdbarch.c:1420
struct cleanup * make_cleanup(make_cleanup_ftype *function, void *arg)
Definition: cleanups.c:117
static const unsigned char * xtensa_breakpoint_from_pc(struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
Definition: xtensa-tdep.c:1972
#define WINSIZE(ra)
Definition: xtensa-tdep.c:89
static void execute_l32e(struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
Definition: xtensa-tdep.c:2736
#define TARGET_CHAR_BIT
Definition: host-defs.h:29
void set_solib_svr4_fetch_link_map_offsets(struct gdbarch *gdbarch, struct link_map_offsets *(*flmo)(void))
Definition: solib-svr4.c:3108
#define PS_CALLINC_MASK
Definition: xtensa-tdep.c:87
xtensa_register_group_t group
Definition: xtensa-tdep.h:129
int cpenable_regnum
Definition: xtensa-tdep.h:226
Definition: gdbtypes.h:749
int find_pc_partial_function(CORE_ADDR pc, const char **name, CORE_ADDR *address, CORE_ADDR *endaddr)
Definition: blockframe.c:321
#define C0_FP
Definition: xtensa-tdep.c:947
static void call0_frame_cache(struct frame_info *this_frame, xtensa_frame_cache_t *cache, CORE_ADDR pc)
Definition: xtensa-tdep.c:2577
static void xtensa_init_reggroups(void)
Definition: xtensa-tdep.c:738
unsigned int num_nopriv_regs
Definition: xtensa-tdep.h:207
void set_gdbarch_unwind_pc(struct gdbarch *gdbarch, gdbarch_unwind_pc_ftype unwind_pc)
Definition: gdbarch.c:2863
void set_gdbarch_breakpoint_from_pc(struct gdbarch *gdbarch, gdbarch_breakpoint_from_pc_ftype breakpoint_from_pc)
Definition: gdbarch.c:2672
struct type * builtin_uint32
Definition: gdbtypes.h:1519
int default_frame_sniffer(const struct frame_unwind *self, struct frame_info *this_frame, void **this_prologue_cache)
Definition: frame-unwind.c:170
xtensa_c0reg_t c0_rt[C0_NREGS]
Definition: xtensa-tdep.c:990
#define C0_MAXOPDS
Definition: xtensa-tdep.c:942
#define C0_NREGS
Definition: xtensa-tdep.c:944
static xtensa_exception_handler_t execute_code(struct gdbarch *gdbarch, CORE_ADDR current_pc, CORE_ADDR wb)
Definition: xtensa-tdep.c:2789
#define gdb_assert(expr)
Definition: gdb_assert.h:33
static int a11_was_saved
Definition: xtensa-tdep.c:2732
#define ARG_NOF(gdbarch)
Definition: xtensa-tdep.c:97
#define min(a, b)
Definition: defs.h:106
#define WB_SHIFT
Definition: xtensa-tdep.h:300
struct type * builtin_long
Definition: gdbtypes.h:1484
struct value * value_cast(struct type *type, struct value *arg2)
Definition: valops.c:351
enum register_status regcache_raw_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition: regcache.c:690
static const struct frame_unwind xtensa_unwind
Definition: xtensa-tdep.c:1532
xtensa_elf_greg_t windowbase
Definition: xtensa-tdep.h:98
static CORE_ADDR call0_analyze_prologue(struct gdbarch *gdbarch, CORE_ADDR start, CORE_ADDR pc, int nregs, xtensa_frame_cache_t *cache)
Definition: xtensa-tdep.c:2371
static int xtensa_window_interrupt_insn(struct gdbarch *gdbarch, CORE_ADDR pc)
Definition: xtensa-tdep.c:1099
static CORE_ADDR a0_saved
Definition: xtensa-tdep.c:2727
char * xstrprintf(const char *format,...)
Definition: common-utils.c:107
int regnum
Definition: aarch64-tdep.c:69
struct type * arch_integer_type(struct gdbarch *gdbarch, int bit, int unsigned_p, char *name)
Definition: gdbtypes.c:4552
struct cmd_list_element * setdebuglist
Definition: cli-cmds.c:173
void read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition: corefile.c:244
void( iterate_over_regset_sections_cb)(const char *sect_name, int size, const struct regset *regset, const char *human_name, void *cb_data)
Definition: gdbarch.h:98
struct reggroup *const vector_reggroup
Definition: reggroups.c:295
ULONGEST get_frame_register_unsigned(struct frame_info *frame, int regnum)
Definition: frame.c:1194
void * xmalloc(YYSIZE_T)
struct ui_file * gdb_stdlog
Definition: main.c:73
struct ui_file * mem_fileopen(void)
Definition: ui-file.c:427
static void xtensa_dump_tdep(struct gdbarch *gdbarch, struct ui_file *file)
Definition: xtensa-tdep.c:3280
struct type * builtin_uint128
Definition: gdbtypes.h:1523
void set_gdbarch_frame_args_skip(struct gdbarch *gdbarch, CORE_ADDR frame_args_skip)
Definition: gdbarch.c:2839
CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS]
Definition: xtensa-tdep.c:937
int litbase_regnum
Definition: xtensa-tdep.h:222
xtensa_elf_greg_t lcount
Definition: xtensa-tdep.h:95
Definition: regdef.h:22
int max_register_raw_size
Definition: xtensa-tdep.h:231
Definition: value.c:172
static void xtensa_write_register(int regnum, ULONGEST value)
Definition: xtensa-tdep.c:173
static int call0_track_op(struct gdbarch *gdbarch, xtensa_c0reg_t dst[], xtensa_c0reg_t src[], xtensa_insn_kind opclass, int nods, unsigned odv[], CORE_ADDR pc, int spreg, xtensa_frame_cache_t *cache)
Definition: xtensa-tdep.c:2204
int interrupt2_regnum
Definition: xtensa-tdep.h:225
static CORE_ADDR xtensa_frame_align(struct gdbarch *gdbarch, CORE_ADDR address)
Definition: xtensa-tdep.c:1056
static CORE_ADDR a7_saved
Definition: xtensa-tdep.c:2728
void regcache_raw_write_part(struct regcache *regcache, int regnum, int offset, int len, const gdb_byte *buf)
Definition: regcache.c:1006
static void execute_s32e(struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
Definition: xtensa-tdep.c:2765
unsigned int target_number
Definition: xtensa-tdep.h:135
const char const char int
Definition: command.h:229
int core_addr_lessthan(CORE_ADDR lhs, CORE_ADDR rhs)
Definition: arch-utils.c:138
bfd_byte gdb_byte
Definition: common-types.h:38
int debugcause_regnum
Definition: xtensa-tdep.h:227
void set_gdbarch_pseudo_register_read(struct gdbarch *gdbarch, gdbarch_pseudo_register_read_ftype pseudo_register_read)
Definition: gdbarch.c:1843
#define RETURN_FP
static int areg_number(struct gdbarch *gdbarch, int ar_regnum, unsigned int wb)
Definition: xtensa-tdep.c:149
struct cleanup * make_cleanup_ui_file_delete(struct ui_file *arg)
Definition: utils.c:237
#define DEBUGVERB(args...)
Definition: xtensa-tdep.c:70
#define PS_EXC
Definition: xtensa-tdep.c:119
unsigned int target_flags
Definition: xtensa-tdep.h:176
#define TYPE_CODE(thistype)
Definition: gdbtypes.h:1240
enum register_status regcache_raw_read(struct regcache *regcache, int regnum, gdb_byte *buf)
Definition: regcache.c:637
static struct value * xtensa_frame_prev_register(struct frame_info *this_frame, void **this_cache, int regnum)
Definition: xtensa-tdep.c:1442
struct value * frame_unwind_got_register(struct frame_info *frame, int regnum, int new_regnum)
Definition: frame-unwind.c:218
void regcache_cooked_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
Definition: regcache.c:871
#define LITTLE_BREAKPOINT
Definition: xtensa-tdep.c:1967
int target_read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition: target.c:1393
struct type * builtin_data_ptr
Definition: gdbtypes.h:1533
#define XTENSA_ISA_BADPC
Definition: xtensa-tdep.c:1131
const xtensa_mask_t * mask
Definition: xtensa-tdep.h:140
static void xtensa_frame_this_id(struct frame_info *this_frame, void **this_cache, struct frame_id *this_id)
Definition: xtensa-tdep.c:1428
static void xtensa_verify_config(struct gdbarch *gdbarch)
Definition: xtensa-tdep.c:3063
xtensa_register_type_t type
Definition: xtensa-tdep.h:128
int offset
Definition: agent.c:65
void regcache_raw_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
Definition: regcache.c:723
int code
Definition: ser-unix.c:684
Definition: buffer.h:23
void set_gdbarch_num_pseudo_regs(struct gdbarch *gdbarch, int num_pseudo_regs)
Definition: gdbarch.c:1926
static xtensa_insn_kind call0_classify_opcode(xtensa_isa isa, xtensa_opcode opc)
Definition: xtensa-tdep.c:2131
void dwarf2_append_unwinders(struct gdbarch *gdbarch)
#define C0_INEXP
Definition: xtensa-tdep.c:960
xtensa_elf_greg_t sar
Definition: xtensa-tdep.h:96
struct ctype_cache * type_entries
Definition: xtensa-tdep.h:238
static void xtensa_store_return_value(struct type *type, struct regcache *regcache, const void *dst)
Definition: xtensa-tdep.c:1618
CORE_ADDR pc
Definition: symtab.h:1376
#define DENSITY_LITTLE_BREAKPOINT
Definition: xtensa-tdep.c:1969
static int xtensa_reg_to_regnum(struct gdbarch *gdbarch, int regnum)
Definition: xtensa-tdep.c:344
#define SAVE_REST_VALID
Definition: xtensa-tdep.c:793
#define XTENSA_NUM_SAVED_AREGS
Definition: xtensa-tdep.c:923
xtensa_elf_greg_t pc
Definition: xtensa-tdep.h:91
#define XTENSA_ISA_BSZ
Definition: xtensa-tdep.c:1130
void regcache_raw_supply(struct regcache *regcache, int regnum, const void *buf)
Definition: regcache.c:1041
static void xtensa_window_interrupt_frame_cache(struct frame_info *this_frame, xtensa_frame_cache_t *cache, CORE_ADDR pc)
Definition: xtensa-tdep.c:2923
static int a0_was_saved
Definition: xtensa-tdep.c:2730
#define C0_ARGS
Definition: xtensa-tdep.c:949
unsigned long long ULONGEST
Definition: common-types.h:53
enum unwind_stop_reason default_frame_unwind_stop_reason(struct frame_info *this_frame, void **this_cache)
Definition: frame-unwind.c:180
static unsigned int xtensa_debug_level
Definition: xtensa-tdep.c:56
struct type * value_type(const struct value *value)
Definition: value.c:1021
void set_gdbarch_return_value(struct gdbarch *gdbarch, gdbarch_return_value_ftype return_value)
Definition: gdbarch.c:2556
struct cmd_list_element * showdebuglist
Definition: cli-cmds.c:175
int gdbarch_pc_regnum(struct gdbarch *gdbarch)
Definition: gdbarch.c:1998
xtensa_register_group_t
Definition: xtensa-tdep.h:47
static CORE_ADDR a11_saved
Definition: xtensa-tdep.c:2729
static void xtensa_pseudo_register_write(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buffer)
Definition: xtensa-tdep.c:642
struct reggroup *const save_reggroup
Definition: reggroups.c:297
#define TYPE_LENGTH(thistype)
Definition: gdbtypes.h:1237
static void xtensa_extract_return_value(struct type *type, struct regcache *regcache, void *dst)
Definition: xtensa-tdep.c:1562
static int xtensa_coprocessor_register_group(struct reggroup *group)
Definition: xtensa-tdep.c:778
void set_gdbarch_push_dummy_call(struct gdbarch *gdbarch, gdbarch_push_dummy_call_ftype push_dummy_call)
Definition: gdbarch.c:2216
static struct gdbarch * xtensa_gdbarch_init(struct gdbarch_info info, struct gdbarch_list *arches)
Definition: xtensa-tdep.c:3191
int excvaddr_regnum
Definition: xtensa-tdep.h:229
#define XTENSA_IS_ENTRY(gdbarch, op1)
Definition: xtensa-tdep.c:108
ULONGEST read_memory_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition: corefile.c:321
struct type * builtin_uint64
Definition: gdbtypes.h:1521
void set_gdbarch_iterate_over_regset_sections(struct gdbarch *gdbarch, gdbarch_iterate_over_regset_sections_ftype iterate_over_regset_sections)
Definition: gdbarch.c:3398
unsigned int num_pseudo_regs
Definition: xtensa-tdep.h:208
#define DEBUGTRACE(args...)
Definition: xtensa-tdep.c:66
void write_memory(CORE_ADDR memaddr, const bfd_byte *myaddr, ssize_t len)
Definition: corefile.c:389
void set_gdbarch_skip_prologue(struct gdbarch *gdbarch, gdbarch_skip_prologue_ftype skip_prologue)
Definition: gdbarch.c:2590
#define XTENSA_REGISTER_FLAGS_PRIVILEGED
Definition: xtensa-tdep.h:151
static unsigned long xtensa_read_register(int regnum)
Definition: xtensa-tdep.c:163
enum bfd_endian byte_order
Definition: gdbarch.h:1552
static struct frame_id xtensa_dummy_id(struct gdbarch *gdbarch, struct frame_info *this_frame)
Definition: xtensa-tdep.c:1081
struct xtensa_windowed_frame_cache xtensa_windowed_frame_cache_t
enum bfd_endian byte_order
Definition: gdbarch.c:128
void set_gdbarch_pc_regnum(struct gdbarch *gdbarch, int pc_regnum)
Definition: gdbarch.c:2008
void set_gdbarch_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype register_name)
Definition: gdbarch.c:2127
CORE_ADDR get_frame_func(struct frame_info *this_frame)
Definition: frame.c:920
void error(const char *fmt,...)
Definition: errors.c:38
size_t size
Definition: go32-nat.c:242
struct gdbarch * gdbarch_alloc(const struct gdbarch_info *info, struct gdbarch_tdep *tdep)
Definition: gdbarch.c:339
void set_gdbarch_inner_than(struct gdbarch *gdbarch, gdbarch_inner_than_ftype inner_than)
Definition: gdbarch.c:2655
struct gdbarch * get_frame_arch(struct frame_info *this_frame)
Definition: frame.c:2535
static void xtensa_register_write_masked(struct regcache *regcache, xtensa_register_t *reg, const gdb_byte *buffer)
Definition: xtensa-tdep.c:369
static int xtensa_session_once_reported
Definition: xtensa-tdep.c:1410
void do_cleanups(struct cleanup *old_chain)
Definition: cleanups.c:175
void regcache_cooked_write(struct regcache *regcache, int regnum, const gdb_byte *buf)
Definition: regcache.c:930
#define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN
Definition: xtensa-tdep.c:2777
initialize_file_ftype _initialize_xtensa_tdep
static int call0_ret(CORE_ADDR start_pc, CORE_ADDR finish_pc)
Definition: xtensa-tdep.c:2015
void set_gdbarch_print_insn(struct gdbarch *gdbarch, gdbarch_print_insn_ftype print_insn)
Definition: gdbarch.c:3067
struct type * builtin_int
Definition: gdbtypes.h:1483
void regcache_raw_write(struct regcache *regcache, int regnum, const gdb_byte *buf)
Definition: regcache.c:885
const ULONGEST const LONGEST len
Definition: target.h:309
xtensa_register_t rmap[]
Definition: xtensa-config.c:65