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1 /* Common target dependent code for GDB on ARM systems.
2  Copyright (C) 2002-2015 Free Software Foundation, Inc.
3 
4  This file is part of GDB.
5 
6  This program is free software; you can redistribute it and/or modify
7  it under the terms of the GNU General Public License as published by
8  the Free Software Foundation; either version 3 of the License, or
9  (at your option) any later version.
10 
11  This program is distributed in the hope that it will be useful,
12  but WITHOUT ANY WARRANTY; without even the implied warranty of
13  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  GNU General Public License for more details.
15 
16  You should have received a copy of the GNU General Public License
17  along with this program. If not, see <http://www.gnu.org/licenses/>. */
18 
19 #ifndef ARM_TDEP_H
20 #define ARM_TDEP_H
21 
22 /* Forward declarations. */
23 struct gdbarch;
24 struct regset;
25 struct address_space;
26 
27 /* Register numbers of various important registers. */
28 
29 enum gdb_regnum {
30  ARM_A1_REGNUM = 0, /* first integer-like argument */
31  ARM_A4_REGNUM = 3, /* last integer-like argument */
34  ARM_SP_REGNUM = 13, /* Contains address of top of stack */
35  ARM_LR_REGNUM = 14, /* address to return to from a function call */
36  ARM_PC_REGNUM = 15, /* Contains program counter */
37  ARM_F0_REGNUM = 16, /* first floating point register */
38  ARM_F3_REGNUM = 19, /* last floating point argument register */
39  ARM_F7_REGNUM = 23, /* last floating point register */
40  ARM_FPS_REGNUM = 24, /* floating point status register */
41  ARM_PS_REGNUM = 25, /* Contains processor status */
42  ARM_WR0_REGNUM, /* WMMX data registers. */
44  ARM_WC0_REGNUM, /* WMMX control registers. */
48  ARM_WCGR0_REGNUM, /* WMMX general purpose registers. */
51  ARM_D0_REGNUM, /* VFP double-precision registers. */
54 
56 
57  /* Other useful registers. */
58  ARM_FP_REGNUM = 11, /* Frame register in ARM code, if used. */
59  THUMB_FP_REGNUM = 7, /* Frame register in Thumb code, if used. */
64 };
65 
66 /* Size of integer registers. */
67 #define INT_REGISTER_SIZE 4
68 
69 /* Say how long FP registers are. Used for documentation purposes and
70  code readability in this header. IEEE extended doubles are 80
71  bits. DWORD aligned they use 96 bits. */
72 #define FP_REGISTER_SIZE 12
73 
74 /* Say how long VFP double precision registers are. Used for documentation
75  purposes and code readability. These are fixed at 64 bits. */
76 #define VFP_REGISTER_SIZE 8
77 
78 /* Number of machine registers. The only define actually required
79  is gdbarch_num_regs. The other definitions are used for documentation
80  purposes and code readability. */
81 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
82  (and called PS for processor status) so the status bits can be cleared
83  from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed
84  in PS. */
85 #define NUM_FREGS 8 /* Number of floating point registers. */
86 #define NUM_SREGS 2 /* Number of status registers. */
87 #define NUM_GREGS 16 /* Number of general purpose registers. */
88 
89 
90 /* Instruction condition field values. */
91 #define INST_EQ 0x0
92 #define INST_NE 0x1
93 #define INST_CS 0x2
94 #define INST_CC 0x3
95 #define INST_MI 0x4
96 #define INST_PL 0x5
97 #define INST_VS 0x6
98 #define INST_VC 0x7
99 #define INST_HI 0x8
100 #define INST_LS 0x9
101 #define INST_GE 0xa
102 #define INST_LT 0xb
103 #define INST_GT 0xc
104 #define INST_LE 0xd
105 #define INST_AL 0xe
106 #define INST_NV 0xf
107 
108 #define FLAG_N 0x80000000
109 #define FLAG_Z 0x40000000
110 #define FLAG_C 0x20000000
111 #define FLAG_V 0x10000000
112 
113 #define CPSR_T 0x20
114 
115 #define XPSR_T 0x01000000
116 
117 /* Type of floating-point code in use by inferior. There are really 3 models
118  that are traditionally supported (plus the endianness issue), but gcc can
119  only generate 2 of those. The third is APCS_FLOAT, where arguments to
120  functions are passed in floating-point registers.
121 
122  In addition to the traditional models, VFP adds two more.
123 
124  If you update this enum, don't forget to update fp_model_strings in
125  arm-tdep.c. */
126 
128 {
129  ARM_FLOAT_AUTO, /* Automatic detection. Do not set in tdep. */
130  ARM_FLOAT_SOFT_FPA, /* Traditional soft-float (mixed-endian on LE ARM). */
131  ARM_FLOAT_FPA, /* FPA co-processor. GCC calling convention. */
132  ARM_FLOAT_SOFT_VFP, /* Soft-float with pure-endian doubles. */
133  ARM_FLOAT_VFP, /* Full VFP calling convention. */
134  ARM_FLOAT_LAST /* Keep at end. */
135 };
136 
137 /* ABI used by the inferior. */
139 {
144 };
145 
146 /* Convention for returning structures. */
147 
148 enum struct_return
149 {
150  pcc_struct_return, /* Return "short" structures in memory. */
151  reg_struct_return /* Return "short" structures in registers. */
152 };
153 
154 /* Target-dependent structure in gdbarch. */
155 struct gdbarch_tdep
156 {
157  /* The ABI for this architecture. It should never be set to
158  ARM_ABI_AUTO. */
160 
161  enum arm_float_model fp_model; /* Floating point calling conventions. */
162 
163  int have_fpa_registers; /* Does the target report the FPA registers? */
164  int have_wmmx_registers; /* Does the target report the WMMX registers? */
165  /* The number of VFP registers reported by the target. It is zero
166  if VFP registers are not supported. */
168  int have_vfp_pseudos; /* Are we synthesizing the single precision
169  VFP registers? */
170  int have_neon_pseudos; /* Are we synthesizing the quad precision
171  NEON registers? Requires
172  have_vfp_pseudos. */
173  int have_neon; /* Do we have a NEON unit? */
174 
175  int is_m; /* Does the target follow the "M" profile. */
176  CORE_ADDR lowest_pc; /* Lowest address at which instructions
177  will appear. */
178 
179  const gdb_byte *arm_breakpoint; /* Breakpoint pattern for an ARM insn. */
180  int arm_breakpoint_size; /* And its size. */
181  const gdb_byte *thumb_breakpoint; /* Breakpoint pattern for a Thumb insn. */
182  int thumb_breakpoint_size; /* And its size. */
183 
184  /* If the Thumb breakpoint is an undefined instruction (which is
185  affected by IT blocks) rather than a BKPT instruction (which is
186  not), then we need a 32-bit Thumb breakpoint to preserve the
187  instruction count in IT blocks. */
190 
191  int jb_pc; /* Offset to PC value in jump buffer.
192  If this is negative, longjmp support
193  will be disabled. */
194  size_t jb_elt_size; /* And the size of each entry in the buf. */
195 
196  /* Convention for returning structures. */
197  enum struct_return struct_return;
198 
199  /* ISA-specific data types. */
203 
204  /* Return the expected next PC if FRAME is stopped at a syscall
205  instruction. */
207 
208  /* syscall record. */
209  int (*arm_syscall_record) (struct regcache *regcache, unsigned long svc_number);
210 };
211 
212 /* Structures used for displaced stepping. */
213 
214 /* The maximum number of temporaries available for displaced instructions. */
215 #define DISPLACED_TEMPS 16
216 /* The maximum number of modified instructions generated for one single-stepped
217  instruction, including the breakpoint (usually at the end of the instruction
218  sequence) and any scratch words, etc. */
219 #define DISPLACED_MODIFIED_INSNS 8
220 
222 {
224  int rd;
226  union
227  {
228  struct
229  {
230  int xfersize;
231  int rn; /* Writeback register. */
232  unsigned int immed : 1; /* Offset is immediate. */
233  unsigned int writeback : 1; /* Perform base-register writeback. */
234  unsigned int restore_r4 : 1; /* Used r4 as scratch. */
235  } ldst;
236 
237  struct
238  {
239  unsigned long dest;
240  unsigned int link : 1;
241  unsigned int exchange : 1;
242  unsigned int cond : 4;
243  } branch;
244 
245  struct
246  {
247  unsigned int regmask;
248  int rn;
250  unsigned int load : 1;
251  unsigned int user : 1;
252  unsigned int increment : 1;
253  unsigned int before : 1;
254  unsigned int writeback : 1;
255  unsigned int cond : 4;
256  } block;
257 
258  struct
259  {
260  unsigned int immed : 1;
261  } preload;
262 
263  struct
264  {
265  /* If non-NULL, override generic SVC handling (e.g. for a particular
266  OS). */
267  int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs,
268  struct displaced_step_closure *dsc);
269  } svc;
270  } u;
271 
272  /* The size of original instruction, 2 or 4. */
273  unsigned int insn_size;
274  /* True if the original insn (and thus all replacement insns) are Thumb
275  instead of ARM. */
276  unsigned int is_thumb;
277 
278  /* The slots in the array is used in this way below,
279  - ARM instruction occupies one slot,
280  - Thumb 16 bit instruction occupies one slot,
281  - Thumb 32-bit instruction occupies *two* slots, one part for each. */
283  int numinsns;
286  void (*cleanup) (struct gdbarch *, struct regcache *,
287  struct displaced_step_closure *);
288 };
289 
290 /* Values for the WRITE_PC argument to displaced_write_reg. If the register
291  write may write to the PC, specifies the way the CPSR T bit, etc. is
292  modified by the instruction. */
293 
295 {
301 };
302 
303 extern void
305  CORE_ADDR to, struct regcache *regs,
306  struct displaced_step_closure *dsc);
307 extern void
309  CORE_ADDR to, struct displaced_step_closure *dsc);
310 extern ULONGEST
311  displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
312  int regno);
313 extern void
314  displaced_write_reg (struct regcache *regs,
315  struct displaced_step_closure *dsc, int regno,
316  ULONGEST val, enum pc_write_style write_pc);
317 
321  struct address_space *, CORE_ADDR);
323 int arm_software_single_step (struct frame_info *);
324 int arm_frame_is_thumb (struct frame_info *frame);
325 
326 extern struct displaced_step_closure *
328  struct regcache *);
329 extern void arm_displaced_step_fixup (struct gdbarch *,
330  struct displaced_step_closure *,
331  CORE_ADDR, CORE_ADDR, struct regcache *);
332 
333 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
334 extern int arm_psr_thumb_bit (struct gdbarch *);
335 
336 /* Is the instruction at the given memory address a Thumb or ARM
337  instruction? */
338 extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);
339 
340 extern int arm_process_record (struct gdbarch *gdbarch,
341  struct regcache *regcache, CORE_ADDR addr);
342 /* Functions exported from armbsd-tdep.h. */
343 
344 /* Return the appropriate register set for the core section identified
345  by SECT_NAME and SECT_SIZE. */
346 
347 extern void
350  void *cb_data,
351  const struct regcache *regcache);
352 
353 /* Target descriptions. */
354 extern struct target_desc *tdesc_arm_with_m;
355 extern struct target_desc *tdesc_arm_with_iwmmxt;
356 extern struct target_desc *tdesc_arm_with_vfpv2;
357 extern struct target_desc *tdesc_arm_with_vfpv3;
358 extern struct target_desc *tdesc_arm_with_neon;
359 
360 #endif /* arm-tdep.h */
struct displaced_step_closure::@19::@22 block
arm_float_model
Definition: arm-tdep.h:127
CORE_ADDR(* syscall_next_pc)(struct frame_info *frame)
Definition: arm-tdep.h:206
struct target_desc * tdesc_arm_with_iwmmxt
const gdb_byte * thumb_breakpoint
Definition: arm-tdep.h:181
bfd_vma CORE_ADDR
Definition: common-types.h:41
unsigned long modinsn[DISPLACED_MODIFIED_INSNS]
Definition: arm-tdep.h:282
unsigned int insn_size
Definition: arm-tdep.h:273
struct target_desc * tdesc_arm_with_vfpv2
Definition: arm-with-vfpv2.c:8
struct displaced_step_closure::@19::@23 preload
CORE_ADDR scratch_base
Definition: arm-tdep.h:285
int(* copy_svc_os)(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc)
Definition: arm-tdep.h:267
struct displaced_step_closure::@19::@20 ldst
int arm_software_single_step(struct frame_info *)
Definition: arm-tdep.c:5302
enum arm_float_model fp_model
Definition: arm-tdep.h:161
int arm_psr_thumb_bit(struct gdbarch *)
Definition: arm-tdep.c:283
const gdb_byte * arm_breakpoint
Definition: arm-tdep.h:179
CORE_ADDR lowest_pc
Definition: aarch64-tdep.h:76
ULONGEST tmp[DISPLACED_TEMPS]
Definition: arm-tdep.h:223
unsigned int user
Definition: arm-tdep.h:251
CORE_ADDR arm_get_next_pc(struct frame_info *, CORE_ADDR)
Definition: arm-tdep.c:5044
unsigned int exchange
Definition: arm-tdep.h:241
int arm_frame_is_thumb(struct frame_info *frame)
Definition: arm-tdep.c:294
enum arm_abi_kind arm_abi
Definition: arm-tdep.h:159
pc_write_style
Definition: arm-tdep.h:294
struct type * neon_double_type
Definition: arm-tdep.h:201
Definition: regset.h:34
union displaced_step_closure::@19 u
unsigned int load
Definition: arm-tdep.h:250
struct displaced_step_closure * arm_displaced_step_copy_insn(struct gdbarch *, CORE_ADDR, CORE_ADDR, struct regcache *)
Definition: arm-tdep.c:8736
int have_fpa_registers
Definition: arm-tdep.h:163
int * from
Definition: varobj.h:282
void arm_displaced_init_closure(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct displaced_step_closure *dsc)
Definition: arm-tdep.c:8679
int thumb_breakpoint_size
Definition: arm-tdep.h:182
unsigned int is_thumb
Definition: arm-tdep.h:276
CORE_ADDR arm_skip_stub(struct frame_info *, CORE_ADDR)
Definition: arm-tdep.c:9295
void displaced_write_reg(struct regcache *regs, struct displaced_step_closure *dsc, int regno, ULONGEST val, enum pc_write_style write_pc)
Definition: arm-tdep.c:5655
int arm_pc_is_thumb(struct gdbarch *, CORE_ADDR)
Definition: arm-tdep.c:381
int have_vfp_pseudos
Definition: arm-tdep.h:168
struct_return
Definition: arm-tdep.h:148
void arm_process_displaced_insn(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct regcache *regs, struct displaced_step_closure *dsc)
Definition: arm-tdep.c:8619
int have_neon_pseudos
Definition: arm-tdep.h:170
Definition: gdbtypes.h:749
unsigned int regmask
Definition: arm-tdep.h:247
unsigned int before
Definition: arm-tdep.h:253
void( iterate_over_regset_sections_cb)(const char *sect_name, int size, const struct regset *regset, const char *human_name, void *cb_data)
Definition: gdbarch.h:98
int have_wmmx_registers
Definition: arm-tdep.h:164
gdb_regnum
Definition: arm-tdep.h:29
void arm_displaced_step_fixup(struct gdbarch *, struct displaced_step_closure *, CORE_ADDR, CORE_ADDR, struct regcache *)
Definition: arm-tdep.c:8752
size_t jb_elt_size
Definition: aarch64-tdep.h:83
int(* arm_syscall_record)(struct regcache *regcache, unsigned long svc_number)
Definition: arm-tdep.h:209
struct type * neon_quad_type
Definition: arm-tdep.h:202
void armbsd_iterate_over_regset_sections(struct gdbarch *gdbarch, iterate_over_regset_sections_cb *cb, void *cb_data, const struct regcache *regcache)
Definition: armbsd-tdep.c:115
const char const char int
Definition: command.h:229
bfd_byte gdb_byte
Definition: common-types.h:38
struct type * arm_ext_type
Definition: arm-tdep.h:200
unsigned int immed
Definition: arm-tdep.h:232
unsigned int cond
Definition: arm-tdep.h:242
const gdb_byte * thumb2_breakpoint
Definition: arm-tdep.h:188
struct displaced_step_closure::@19::@24 svc
int thumb2_breakpoint_size
Definition: arm-tdep.h:189
unsigned int restore_r4
Definition: arm-tdep.h:234
unsigned int writeback
Definition: arm-tdep.h:233
ULONGEST displaced_read_reg(struct regcache *regs, struct displaced_step_closure *dsc, int regno)
Definition: arm-tdep.c:5535
unsigned long dest
Definition: arm-tdep.h:239
void arm_insert_single_step_breakpoint(struct gdbarch *, struct address_space *, CORE_ADDR)
Definition: arm-tdep.c:5061
int vfp_register_count
Definition: arm-tdep.h:167
int arm_process_record(struct gdbarch *gdbarch, struct regcache *regcache, CORE_ADDR addr)
Definition: arm-tdep.c:13918
struct displaced_step_closure::@19::@21 branch
int have_neon
Definition: arm-tdep.h:173
#define DISPLACED_TEMPS
Definition: arm-tdep.h:215
struct target_desc * tdesc_arm_with_m
Definition: arm-with-m.c:8
unsigned long long ULONGEST
Definition: common-types.h:53
unsigned int increment
Definition: arm-tdep.h:252
int int * to
Definition: varobj.h:282
int arm_deal_with_atomic_sequence(struct frame_info *)
Definition: arm-tdep.c:5288
#define DISPLACED_MODIFIED_INSNS
Definition: arm-tdep.h:219
arm_abi_kind
Definition: arm-tdep.h:138
struct target_desc * tdesc_arm_with_vfpv3
Definition: arm-with-vfpv3.c:8
unsigned int link
Definition: arm-tdep.h:240
int arm_breakpoint_size
Definition: arm-tdep.h:180
struct target_desc * tdesc_arm_with_neon
Definition: arm-with-neon.c:8