24 #define XTENSA_TDEP_VERSION 0x60
45 #define XTENSA_MAX_COPROCESSOR 0x10
103 #define XTENSA_ELF_NGREG (sizeof (xtensa_elf_gregset_t) \
104 / sizeof (xtensa_elf_greg_t))
146 #define XTREG(index,ofs,bsz,sz,al,tnum,flg,cp,ty,gr,name,fet,sto,mas,ct,x,y) \
147 {#name, ofs, ty, ((gr) | ((xtRegisterGroupNCP >> 2) << (cp + 2))), \
148 ct, bsz, sz, al, tnum, flg, cp, mas, fet, sto},
149 #define XTREG_END {0, 0, 0, 0, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0},
151 #define XTENSA_REGISTER_FLAGS_PRIVILEGED 0x0001
152 #define XTENSA_REGISTER_FLAGS_READABLE 0x0002
153 #define XTENSA_REGISTER_FLAGS_WRITABLE 0x0004
154 #define XTENSA_REGISTER_FLAGS_VOLATILE 0x0008
243 #define XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spillsz) \
246 .spill_location = -1, \
247 .spill_size = (spillsz), \
250 .debug_interrupt_level = XCHAL_DEBUGLEVEL, \
251 .icache_line_bytes = XCHAL_ICACHE_LINESIZE, \
252 .dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \
253 .dcache_writeback = XCHAL_DCACHE_IS_WRITEBACK, \
254 .isa_use_windowed_registers = (XSHAL_ABI != XTHAL_ABI_CALL0), \
255 .isa_use_density_instructions = XCHAL_HAVE_DENSITY, \
256 .isa_use_exceptions = XCHAL_HAVE_EXCEPTIONS, \
257 .isa_use_ext_l32r = XSHAL_USE_ABSOLUTE_LITERALS, \
258 .isa_max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE, \
259 .debug_num_ibreaks = XCHAL_NUM_IBREAK, \
260 .debug_num_dbreaks = XCHAL_NUM_DBREAK, \
263 .num_nopriv_regs = 0, \
264 .num_pseudo_regs = 0, \
265 .num_aregs = XCHAL_NUM_AREGS, \
266 .num_contexts = XCHAL_NUM_CONTEXTS, \
275 .lcount_regnum = -1, \
277 .litbase_regnum = -1, \
278 .interrupt_regnum = -1, \
279 .interrupt2_regnum = -1, \
280 .cpenable_regnum = -1, \
281 .debugcause_regnum = -1, \
282 .exccause_regnum = -1, \
283 .excvaddr_regnum = -1, \
284 .max_register_raw_size = 0, \
285 .max_register_virtual_size = 0, \
287 .fp_layout_bytes = 0, \
290 #define XTENSA_CONFIG_INSTANTIATE(rmap,spill_size) \
291 struct gdbarch_tdep xtensa_tdep = \
292 XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spill_size);
294 #ifndef XCHAL_NUM_CONTEXTS
295 #define XCHAL_NUM_CONTEXTS 0
297 #ifndef XCHAL_HAVE_EXCEPTIONS
298 #define XCHAL_HAVE_EXCEPTIONS 1
unsigned int debug_interrupt_level
unsigned int spill_location
struct type * virtual_type
unsigned int debug_num_ibreaks
unsigned int dcache_line_bytes
unsigned int isa_use_windowed_registers
unsigned int icache_line_bytes
xtensa_register_t * regmap
int max_register_virtual_size
struct ctype_cache * next
unsigned int isa_use_ext_l32r
unsigned int isa_use_exceptions
xtensa_elf_greg_t windowstart
unsigned int num_contexts
xtensa_register_group_t group
unsigned int num_nopriv_regs
xtensa_elf_greg_t windowbase
unsigned int isa_use_density_instructions
int max_register_raw_size
unsigned long * fp_layout
unsigned int target_number
unsigned int isa_max_insn_size
uint32_t xtensa_elf_greg_t
unsigned int target_flags
const xtensa_mask_t * mask
xtensa_register_type_t type
struct ctype_cache * type_entries
unsigned int debug_num_dbreaks
unsigned int dcache_writeback
unsigned int fp_layout_bytes
unsigned int num_pseudo_regs