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/tmp/gdb-7.10/gdb/rs6000-tdep.c
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1 /* Target-dependent code for GDB, the GNU debugger.
2 
3  Copyright (C) 1986-2015 Free Software Foundation, Inc.
4 
5  This file is part of GDB.
6 
7  This program is free software; you can redistribute it and/or modify
8  it under the terms of the GNU General Public License as published by
9  the Free Software Foundation; either version 3 of the License, or
10  (at your option) any later version.
11 
12  This program is distributed in the hope that it will be useful,
13  but WITHOUT ANY WARRANTY; without even the implied warranty of
14  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  GNU General Public License for more details.
16 
17  You should have received a copy of the GNU General Public License
18  along with this program. If not, see <http://www.gnu.org/licenses/>. */
19 
20 #include "defs.h"
21 #include "frame.h"
22 #include "inferior.h"
23 #include "infrun.h"
24 #include "symtab.h"
25 #include "target.h"
26 #include "gdbcore.h"
27 #include "gdbcmd.h"
28 #include "objfiles.h"
29 #include "arch-utils.h"
30 #include "regcache.h"
31 #include "regset.h"
32 #include "doublest.h"
33 #include "value.h"
34 #include "parser-defs.h"
35 #include "osabi.h"
36 #include "infcall.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2-frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
44 #include "auxv.h"
45 
46 #include "libbfd.h" /* for bfd_default_set_arch_mach */
47 #include "coff/internal.h" /* for libcoff.h */
48 #include "libcoff.h" /* for xcoff_data */
49 #include "coff/xcoff.h"
50 #include "libxcoff.h"
51 
52 #include "elf-bfd.h"
53 #include "elf/ppc.h"
54 #include "elf/ppc64.h"
55 
56 #include "solib-svr4.h"
57 #include "ppc-tdep.h"
58 #include "ppc-ravenscar-thread.h"
59 
60 #include "dis-asm.h"
61 
62 #include "trad-frame.h"
63 #include "frame-unwind.h"
64 #include "frame-base.h"
65 
84 #include "features/rs6000/rs6000.c"
85 
86 /* Determine if regnum is an SPE pseudo-register. */
87 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
88  && (regnum) >= (tdep)->ppc_ev0_regnum \
89  && (regnum) < (tdep)->ppc_ev0_regnum + 32)
90 
91 /* Determine if regnum is a decimal float pseudo-register. */
92 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
93  && (regnum) >= (tdep)->ppc_dl0_regnum \
94  && (regnum) < (tdep)->ppc_dl0_regnum + 16)
95 
96 /* Determine if regnum is a POWER7 VSX register. */
97 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
98  && (regnum) >= (tdep)->ppc_vsr0_regnum \
99  && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
100 
101 /* Determine if regnum is a POWER7 Extended FP register. */
102 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
103  && (regnum) >= (tdep)->ppc_efpr0_regnum \
104  && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
105 
106 /* The list of available "set powerpc ..." and "show powerpc ..."
107  commands. */
108 static struct cmd_list_element *setpowerpccmdlist = NULL;
109 static struct cmd_list_element *showpowerpccmdlist = NULL;
110 
112 
113 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
114 static const char *const powerpc_vector_strings[] =
115 {
116  "auto",
117  "generic",
118  "altivec",
119  "spe",
120  NULL
121 };
122 
123 /* A variable that can be configured by the user. */
125 static const char *powerpc_vector_abi_string = "auto";
126 
127 /* To be used by skip_prologue. */
128 
130  {
131  int offset; /* total size of frame --- the distance
132  by which we decrement sp to allocate
133  the frame */
134  int saved_gpr; /* smallest # of saved gpr */
135  unsigned int gpr_mask; /* Each bit is an individual saved GPR. */
136  int saved_fpr; /* smallest # of saved fpr */
137  int saved_vr; /* smallest # of saved vr */
138  int saved_ev; /* smallest # of saved ev */
139  int alloca_reg; /* alloca register number (frame ptr) */
140  char frameless; /* true if frameless functions. */
141  char nosavedpc; /* true if pc not saved. */
142  char used_bl; /* true if link register clobbered */
143  int gpr_offset; /* offset of saved gprs from prev sp */
144  int fpr_offset; /* offset of saved fprs from prev sp */
145  int vr_offset; /* offset of saved vrs from prev sp */
146  int ev_offset; /* offset of saved evs from prev sp */
147  int lr_offset; /* offset of saved lr */
148  int lr_register; /* register of saved lr, if trustworthy */
149  int cr_offset; /* offset of saved cr */
150  int vrsave_offset; /* offset of saved vrsave register */
151  };
152 
153 
154 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
155 int
156 vsx_register_p (struct gdbarch *gdbarch, int regno)
157 {
158  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
159  if (tdep->ppc_vsr0_regnum < 0)
160  return 0;
161  else
162  return (regno >= tdep->ppc_vsr0_upper_regnum && regno
163  <= tdep->ppc_vsr0_upper_regnum + 31);
164 }
165 
166 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
167 int
168 altivec_register_p (struct gdbarch *gdbarch, int regno)
169 {
170  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
171  if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
172  return 0;
173  else
174  return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
175 }
176 
177 
178 /* Return true if REGNO is an SPE register, false otherwise. */
179 int
180 spe_register_p (struct gdbarch *gdbarch, int regno)
181 {
182  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
183 
184  /* Is it a reference to EV0 -- EV31, and do we have those? */
185  if (IS_SPE_PSEUDOREG (tdep, regno))
186  return 1;
187 
188  /* Is it a reference to one of the raw upper GPR halves? */
189  if (tdep->ppc_ev0_upper_regnum >= 0
190  && tdep->ppc_ev0_upper_regnum <= regno
191  && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
192  return 1;
193 
194  /* Is it a reference to the 64-bit accumulator, and do we have that? */
195  if (tdep->ppc_acc_regnum >= 0
196  && tdep->ppc_acc_regnum == regno)
197  return 1;
198 
199  /* Is it a reference to the SPE floating-point status and control register,
200  and do we have that? */
201  if (tdep->ppc_spefscr_regnum >= 0
202  && tdep->ppc_spefscr_regnum == regno)
203  return 1;
204 
205  return 0;
206 }
207 
208 
209 /* Return non-zero if the architecture described by GDBARCH has
210  floating-point registers (f0 --- f31 and fpscr). */
211 int
212 ppc_floating_point_unit_p (struct gdbarch *gdbarch)
213 {
214  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
215 
216  return (tdep->ppc_fp0_regnum >= 0
217  && tdep->ppc_fpscr_regnum >= 0);
218 }
219 
220 /* Return non-zero if the architecture described by GDBARCH has
221  VSX registers (vsr0 --- vsr63). */
222 static int
223 ppc_vsx_support_p (struct gdbarch *gdbarch)
224 {
225  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
226 
227  return tdep->ppc_vsr0_regnum >= 0;
228 }
229 
230 /* Return non-zero if the architecture described by GDBARCH has
231  Altivec registers (vr0 --- vr31, vrsave and vscr). */
232 int
233 ppc_altivec_support_p (struct gdbarch *gdbarch)
234 {
235  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
236 
237  return (tdep->ppc_vr0_regnum >= 0
238  && tdep->ppc_vrsave_regnum >= 0);
239 }
240 
241 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
242  set it to SIM_REGNO.
243 
244  This is a helper function for init_sim_regno_table, constructing
245  the table mapping GDB register numbers to sim register numbers; we
246  initialize every element in that table to -1 before we start
247  filling it in. */
248 static void
249 set_sim_regno (int *table, int gdb_regno, int sim_regno)
250 {
251  /* Make sure we don't try to assign any given GDB register a sim
252  register number more than once. */
253  gdb_assert (table[gdb_regno] == -1);
254  table[gdb_regno] = sim_regno;
255 }
256 
257 
258 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
259  numbers to simulator register numbers, based on the values placed
260  in the ARCH->tdep->ppc_foo_regnum members. */
261 static void
262 init_sim_regno_table (struct gdbarch *arch)
263 {
264  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
265  int total_regs = gdbarch_num_regs (arch);
266  int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
267  int i;
268  static const char *const segment_regs[] = {
269  "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
270  "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
271  };
272 
273  /* Presume that all registers not explicitly mentioned below are
274  unavailable from the sim. */
275  for (i = 0; i < total_regs; i++)
276  sim_regno[i] = -1;
277 
278  /* General-purpose registers. */
279  for (i = 0; i < ppc_num_gprs; i++)
280  set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
281 
282  /* Floating-point registers. */
283  if (tdep->ppc_fp0_regnum >= 0)
284  for (i = 0; i < ppc_num_fprs; i++)
285  set_sim_regno (sim_regno,
286  tdep->ppc_fp0_regnum + i,
287  sim_ppc_f0_regnum + i);
288  if (tdep->ppc_fpscr_regnum >= 0)
289  set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
290 
291  set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
292  set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
293  set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
294 
295  /* Segment registers. */
296  for (i = 0; i < ppc_num_srs; i++)
297  {
298  int gdb_regno;
299 
300  gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1);
301  if (gdb_regno >= 0)
302  set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i);
303  }
304 
305  /* Altivec registers. */
306  if (tdep->ppc_vr0_regnum >= 0)
307  {
308  for (i = 0; i < ppc_num_vrs; i++)
309  set_sim_regno (sim_regno,
310  tdep->ppc_vr0_regnum + i,
311  sim_ppc_vr0_regnum + i);
312 
313  /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
314  we can treat this more like the other cases. */
315  set_sim_regno (sim_regno,
316  tdep->ppc_vr0_regnum + ppc_num_vrs,
317  sim_ppc_vscr_regnum);
318  }
319  /* vsave is a special-purpose register, so the code below handles it. */
320 
321  /* SPE APU (E500) registers. */
322  if (tdep->ppc_ev0_upper_regnum >= 0)
323  for (i = 0; i < ppc_num_gprs; i++)
324  set_sim_regno (sim_regno,
325  tdep->ppc_ev0_upper_regnum + i,
326  sim_ppc_rh0_regnum + i);
327  if (tdep->ppc_acc_regnum >= 0)
328  set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
329  /* spefscr is a special-purpose register, so the code below handles it. */
330 
331 #ifdef WITH_SIM
332  /* Now handle all special-purpose registers. Verify that they
333  haven't mistakenly been assigned numbers by any of the above
334  code. */
335  for (i = 0; i < sim_ppc_num_sprs; i++)
336  {
337  const char *spr_name = sim_spr_register_name (i);
338  int gdb_regno = -1;
339 
340  if (spr_name != NULL)
341  gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1);
342 
343  if (gdb_regno != -1)
344  set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i);
345  }
346 #endif
347 
348  /* Drop the initialized array into place. */
349  tdep->sim_regno = sim_regno;
350 }
351 
352 
353 /* Given a GDB register number REG, return the corresponding SIM
354  register number. */
355 static int
356 rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg)
357 {
358  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
359  int sim_regno;
360 
361  if (tdep->sim_regno == NULL)
362  init_sim_regno_table (gdbarch);
363 
364  gdb_assert (0 <= reg
365  && reg <= gdbarch_num_regs (gdbarch)
366  + gdbarch_num_pseudo_regs (gdbarch));
367  sim_regno = tdep->sim_regno[reg];
368 
369  if (sim_regno >= 0)
370  return sim_regno;
371  else
373 }
374 
375 
376 
377 /* Register set support functions. */
378 
379 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
380  Write the register to REGCACHE. */
381 
382 void
384  const gdb_byte *regs, size_t offset, int regsize)
385 {
386  if (regnum != -1 && offset != -1)
387  {
388  if (regsize > 4)
389  {
390  struct gdbarch *gdbarch = get_regcache_arch (regcache);
391  int gdb_regsize = register_size (gdbarch, regnum);
392  if (gdb_regsize < regsize
393  && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
394  offset += regsize - gdb_regsize;
395  }
396  regcache_raw_supply (regcache, regnum, regs + offset);
397  }
398 }
399 
400 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
401  in a field REGSIZE wide. Zero pad as necessary. */
402 
403 void
405  gdb_byte *regs, size_t offset, int regsize)
406 {
407  if (regnum != -1 && offset != -1)
408  {
409  if (regsize > 4)
410  {
411  struct gdbarch *gdbarch = get_regcache_arch (regcache);
412  int gdb_regsize = register_size (gdbarch, regnum);
413  if (gdb_regsize < regsize)
414  {
415  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
416  {
417  memset (regs + offset, 0, regsize - gdb_regsize);
418  offset += regsize - gdb_regsize;
419  }
420  else
421  memset (regs + offset + regsize - gdb_regsize, 0,
422  regsize - gdb_regsize);
423  }
424  }
425  regcache_raw_collect (regcache, regnum, regs + offset);
426  }
427 }
428 
429 static int
430 ppc_greg_offset (struct gdbarch *gdbarch,
431  struct gdbarch_tdep *tdep,
432  const struct ppc_reg_offsets *offsets,
433  int regnum,
434  int *regsize)
435 {
436  *regsize = offsets->gpr_size;
437  if (regnum >= tdep->ppc_gp0_regnum
438  && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs)
439  return (offsets->r0_offset
440  + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size);
441 
442  if (regnum == gdbarch_pc_regnum (gdbarch))
443  return offsets->pc_offset;
444 
445  if (regnum == tdep->ppc_ps_regnum)
446  return offsets->ps_offset;
447 
448  if (regnum == tdep->ppc_lr_regnum)
449  return offsets->lr_offset;
450 
451  if (regnum == tdep->ppc_ctr_regnum)
452  return offsets->ctr_offset;
453 
454  *regsize = offsets->xr_size;
455  if (regnum == tdep->ppc_cr_regnum)
456  return offsets->cr_offset;
457 
458  if (regnum == tdep->ppc_xer_regnum)
459  return offsets->xer_offset;
460 
461  if (regnum == tdep->ppc_mq_regnum)
462  return offsets->mq_offset;
463 
464  return -1;
465 }
466 
467 static int
469  const struct ppc_reg_offsets *offsets,
470  int regnum)
471 {
472  if (regnum >= tdep->ppc_fp0_regnum
473  && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs)
474  return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8;
475 
476  if (regnum == tdep->ppc_fpscr_regnum)
477  return offsets->fpscr_offset;
478 
479  return -1;
480 }
481 
482 static int
484  const struct ppc_reg_offsets *offsets,
485  int regnum)
486 {
487  if (regnum >= tdep->ppc_vr0_regnum
488  && regnum < tdep->ppc_vr0_regnum + ppc_num_vrs)
489  return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16;
490 
491  if (regnum == tdep->ppc_vrsave_regnum - 1)
492  return offsets->vscr_offset;
493 
494  if (regnum == tdep->ppc_vrsave_regnum)
495  return offsets->vrsave_offset;
496 
497  return -1;
498 }
499 
500 /* Supply register REGNUM in the general-purpose register set REGSET
501  from the buffer specified by GREGS and LEN to register cache
502  REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
503 
504 void
506  int regnum, const void *gregs, size_t len)
507 {
508  struct gdbarch *gdbarch = get_regcache_arch (regcache);
509  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
510  const struct ppc_reg_offsets *offsets = regset->regmap;
511  size_t offset;
512  int regsize;
513 
514  if (regnum == -1)
515  {
516  int i;
517  int gpr_size = offsets->gpr_size;
518 
519  for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
520  i < tdep->ppc_gp0_regnum + ppc_num_gprs;
521  i++, offset += gpr_size)
522  ppc_supply_reg (regcache, i, gregs, offset, gpr_size);
523 
524  ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch),
525  gregs, offsets->pc_offset, gpr_size);
526  ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
527  gregs, offsets->ps_offset, gpr_size);
528  ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
529  gregs, offsets->lr_offset, gpr_size);
530  ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
531  gregs, offsets->ctr_offset, gpr_size);
532  ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
533  gregs, offsets->cr_offset, offsets->xr_size);
534  ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
535  gregs, offsets->xer_offset, offsets->xr_size);
536  ppc_supply_reg (regcache, tdep->ppc_mq_regnum,
537  gregs, offsets->mq_offset, offsets->xr_size);
538  return;
539  }
540 
541  offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
542  ppc_supply_reg (regcache, regnum, gregs, offset, regsize);
543 }
544 
545 /* Supply register REGNUM in the floating-point register set REGSET
546  from the buffer specified by FPREGS and LEN to register cache
547  REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
548 
549 void
551  int regnum, const void *fpregs, size_t len)
552 {
553  struct gdbarch *gdbarch = get_regcache_arch (regcache);
554  struct gdbarch_tdep *tdep;
555  const struct ppc_reg_offsets *offsets;
556  size_t offset;
557 
558  if (!ppc_floating_point_unit_p (gdbarch))
559  return;
560 
561  tdep = gdbarch_tdep (gdbarch);
562  offsets = regset->regmap;
563  if (regnum == -1)
564  {
565  int i;
566 
567  for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
568  i < tdep->ppc_fp0_regnum + ppc_num_fprs;
569  i++, offset += 8)
570  ppc_supply_reg (regcache, i, fpregs, offset, 8);
571 
572  ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
573  fpregs, offsets->fpscr_offset, offsets->fpscr_size);
574  return;
575  }
576 
577  offset = ppc_fpreg_offset (tdep, offsets, regnum);
578  ppc_supply_reg (regcache, regnum, fpregs, offset,
579  regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
580 }
581 
582 /* Supply register REGNUM in the VSX register set REGSET
583  from the buffer specified by VSXREGS and LEN to register cache
584  REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
585 
586 void
588  int regnum, const void *vsxregs, size_t len)
589 {
590  struct gdbarch *gdbarch = get_regcache_arch (regcache);
591  struct gdbarch_tdep *tdep;
592 
593  if (!ppc_vsx_support_p (gdbarch))
594  return;
595 
596  tdep = gdbarch_tdep (gdbarch);
597 
598  if (regnum == -1)
599  {
600  int i;
601 
602  for (i = tdep->ppc_vsr0_upper_regnum;
603  i < tdep->ppc_vsr0_upper_regnum + 32;
604  i++)
605  ppc_supply_reg (regcache, i, vsxregs, 0, 8);
606 
607  return;
608  }
609  else
610  ppc_supply_reg (regcache, regnum, vsxregs, 0, 8);
611 }
612 
613 /* Supply register REGNUM in the Altivec register set REGSET
614  from the buffer specified by VRREGS and LEN to register cache
615  REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
616 
617 void
619  int regnum, const void *vrregs, size_t len)
620 {
621  struct gdbarch *gdbarch = get_regcache_arch (regcache);
622  struct gdbarch_tdep *tdep;
623  const struct ppc_reg_offsets *offsets;
624  size_t offset;
625 
626  if (!ppc_altivec_support_p (gdbarch))
627  return;
628 
629  tdep = gdbarch_tdep (gdbarch);
630  offsets = regset->regmap;
631  if (regnum == -1)
632  {
633  int i;
634 
635  for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
636  i < tdep->ppc_vr0_regnum + ppc_num_vrs;
637  i++, offset += 16)
638  ppc_supply_reg (regcache, i, vrregs, offset, 16);
639 
640  ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
641  vrregs, offsets->vscr_offset, 4);
642 
643  ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum,
644  vrregs, offsets->vrsave_offset, 4);
645  return;
646  }
647 
648  offset = ppc_vrreg_offset (tdep, offsets, regnum);
649  if (regnum != tdep->ppc_vrsave_regnum
650  && regnum != tdep->ppc_vrsave_regnum - 1)
651  ppc_supply_reg (regcache, regnum, vrregs, offset, 16);
652  else
653  ppc_supply_reg (regcache, regnum,
654  vrregs, offset, 4);
655 }
656 
657 /* Collect register REGNUM in the general-purpose register set
658  REGSET from register cache REGCACHE into the buffer specified by
659  GREGS and LEN. If REGNUM is -1, do this for all registers in
660  REGSET. */
661 
662 void
664  const struct regcache *regcache,
665  int regnum, void *gregs, size_t len)
666 {
667  struct gdbarch *gdbarch = get_regcache_arch (regcache);
668  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
669  const struct ppc_reg_offsets *offsets = regset->regmap;
670  size_t offset;
671  int regsize;
672 
673  if (regnum == -1)
674  {
675  int i;
676  int gpr_size = offsets->gpr_size;
677 
678  for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
679  i < tdep->ppc_gp0_regnum + ppc_num_gprs;
680  i++, offset += gpr_size)
681  ppc_collect_reg (regcache, i, gregs, offset, gpr_size);
682 
683  ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch),
684  gregs, offsets->pc_offset, gpr_size);
685  ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
686  gregs, offsets->ps_offset, gpr_size);
687  ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
688  gregs, offsets->lr_offset, gpr_size);
689  ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
690  gregs, offsets->ctr_offset, gpr_size);
691  ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
692  gregs, offsets->cr_offset, offsets->xr_size);
693  ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
694  gregs, offsets->xer_offset, offsets->xr_size);
695  ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
696  gregs, offsets->mq_offset, offsets->xr_size);
697  return;
698  }
699 
700  offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
701  ppc_collect_reg (regcache, regnum, gregs, offset, regsize);
702 }
703 
704 /* Collect register REGNUM in the floating-point register set
705  REGSET from register cache REGCACHE into the buffer specified by
706  FPREGS and LEN. If REGNUM is -1, do this for all registers in
707  REGSET. */
708 
709 void
711  const struct regcache *regcache,
712  int regnum, void *fpregs, size_t len)
713 {
714  struct gdbarch *gdbarch = get_regcache_arch (regcache);
715  struct gdbarch_tdep *tdep;
716  const struct ppc_reg_offsets *offsets;
717  size_t offset;
718 
719  if (!ppc_floating_point_unit_p (gdbarch))
720  return;
721 
722  tdep = gdbarch_tdep (gdbarch);
723  offsets = regset->regmap;
724  if (regnum == -1)
725  {
726  int i;
727 
728  for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
729  i < tdep->ppc_fp0_regnum + ppc_num_fprs;
730  i++, offset += 8)
731  ppc_collect_reg (regcache, i, fpregs, offset, 8);
732 
733  ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
734  fpregs, offsets->fpscr_offset, offsets->fpscr_size);
735  return;
736  }
737 
738  offset = ppc_fpreg_offset (tdep, offsets, regnum);
739  ppc_collect_reg (regcache, regnum, fpregs, offset,
740  regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
741 }
742 
743 /* Collect register REGNUM in the VSX register set
744  REGSET from register cache REGCACHE into the buffer specified by
745  VSXREGS and LEN. If REGNUM is -1, do this for all registers in
746  REGSET. */
747 
748 void
750  const struct regcache *regcache,
751  int regnum, void *vsxregs, size_t len)
752 {
753  struct gdbarch *gdbarch = get_regcache_arch (regcache);
754  struct gdbarch_tdep *tdep;
755 
756  if (!ppc_vsx_support_p (gdbarch))
757  return;
758 
759  tdep = gdbarch_tdep (gdbarch);
760 
761  if (regnum == -1)
762  {
763  int i;
764 
765  for (i = tdep->ppc_vsr0_upper_regnum;
766  i < tdep->ppc_vsr0_upper_regnum + 32;
767  i++)
768  ppc_collect_reg (regcache, i, vsxregs, 0, 8);
769 
770  return;
771  }
772  else
773  ppc_collect_reg (regcache, regnum, vsxregs, 0, 8);
774 }
775 
776 
777 /* Collect register REGNUM in the Altivec register set
778  REGSET from register cache REGCACHE into the buffer specified by
779  VRREGS and LEN. If REGNUM is -1, do this for all registers in
780  REGSET. */
781 
782 void
784  const struct regcache *regcache,
785  int regnum, void *vrregs, size_t len)
786 {
787  struct gdbarch *gdbarch = get_regcache_arch (regcache);
788  struct gdbarch_tdep *tdep;
789  const struct ppc_reg_offsets *offsets;
790  size_t offset;
791 
792  if (!ppc_altivec_support_p (gdbarch))
793  return;
794 
795  tdep = gdbarch_tdep (gdbarch);
796  offsets = regset->regmap;
797  if (regnum == -1)
798  {
799  int i;
800 
801  for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
802  i < tdep->ppc_vr0_regnum + ppc_num_vrs;
803  i++, offset += 16)
804  ppc_collect_reg (regcache, i, vrregs, offset, 16);
805 
806  ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
807  vrregs, offsets->vscr_offset, 4);
808 
809  ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum,
810  vrregs, offsets->vrsave_offset, 4);
811  return;
812  }
813 
814  offset = ppc_vrreg_offset (tdep, offsets, regnum);
815  if (regnum != tdep->ppc_vrsave_regnum
816  && regnum != tdep->ppc_vrsave_regnum - 1)
817  ppc_collect_reg (regcache, regnum, vrregs, offset, 16);
818  else
819  ppc_collect_reg (regcache, regnum,
820  vrregs, offset, 4);
821 }
822 
823 
824 static int
825 insn_changes_sp_or_jumps (unsigned long insn)
826 {
827  int opcode = (insn >> 26) & 0x03f;
828  int sd = (insn >> 21) & 0x01f;
829  int a = (insn >> 16) & 0x01f;
830  int subcode = (insn >> 1) & 0x3ff;
831 
832  /* Changes the stack pointer. */
833 
834  /* NOTE: There are many ways to change the value of a given register.
835  The ways below are those used when the register is R1, the SP,
836  in a funtion's epilogue. */
837 
838  if (opcode == 31 && subcode == 444 && a == 1)
839  return 1; /* mr R1,Rn */
840  if (opcode == 14 && sd == 1)
841  return 1; /* addi R1,Rn,simm */
842  if (opcode == 58 && sd == 1)
843  return 1; /* ld R1,ds(Rn) */
844 
845  /* Transfers control. */
846 
847  if (opcode == 18)
848  return 1; /* b */
849  if (opcode == 16)
850  return 1; /* bc */
851  if (opcode == 19 && subcode == 16)
852  return 1; /* bclr */
853  if (opcode == 19 && subcode == 528)
854  return 1; /* bcctr */
855 
856  return 0;
857 }
858 
859 /* Return true if we are in the function's epilogue, i.e. after the
860  instruction that destroyed the function's stack frame.
861 
862  1) scan forward from the point of execution:
863  a) If you find an instruction that modifies the stack pointer
864  or transfers control (except a return), execution is not in
865  an epilogue, return.
866  b) Stop scanning if you find a return instruction or reach the
867  end of the function or reach the hard limit for the size of
868  an epilogue.
869  2) scan backward from the point of execution:
870  a) If you find an instruction that modifies the stack pointer,
871  execution *is* in an epilogue, return.
872  b) Stop scanning if you reach an instruction that transfers
873  control or the beginning of the function or reach the hard
874  limit for the size of an epilogue. */
875 
876 static int
878  struct gdbarch *gdbarch, CORE_ADDR pc)
879 {
880  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
881  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
882  bfd_byte insn_buf[PPC_INSN_SIZE];
883  CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
884  unsigned long insn;
885 
886  /* Find the search limits based on function boundaries and hard limit. */
887 
888  if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
889  return 0;
890 
891  epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
892  if (epilogue_start < func_start) epilogue_start = func_start;
893 
894  epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
895  if (epilogue_end > func_end) epilogue_end = func_end;
896 
897  /* Scan forward until next 'blr'. */
898 
899  for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
900  {
901  if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
902  return 0;
903  insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
904  if (insn == 0x4e800020)
905  break;
906  /* Assume a bctr is a tail call unless it points strictly within
907  this function. */
908  if (insn == 0x4e800420)
909  {
911  tdep->ppc_ctr_regnum);
912  if (ctr > func_start && ctr < func_end)
913  return 0;
914  else
915  break;
916  }
917  if (insn_changes_sp_or_jumps (insn))
918  return 0;
919  }
920 
921  /* Scan backward until adjustment to stack pointer (R1). */
922 
923  for (scan_pc = pc - PPC_INSN_SIZE;
924  scan_pc >= epilogue_start;
925  scan_pc -= PPC_INSN_SIZE)
926  {
927  if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
928  return 0;
929  insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
930  if (insn_changes_sp_or_jumps (insn))
931  return 1;
932  }
933 
934  return 0;
935 }
936 
937 /* Implement the stack_frame_destroyed_p gdbarch method. */
938 
939 static int
940 rs6000_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
941 {
943  gdbarch, pc);
944 }
945 
946 /* Get the ith function argument for the current function. */
947 static CORE_ADDR
948 rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
949  struct type *type)
950 {
951  return get_frame_register_unsigned (frame, 3 + argi);
952 }
953 
954 /* Sequence of bytes for breakpoint instruction. */
955 
956 static const unsigned char *
957 rs6000_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr,
958  int *bp_size)
959 {
960  static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
961  static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
962  *bp_size = 4;
963  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
964  return big_breakpoint;
965  else
966  return little_breakpoint;
967 }
968 
969 /* Instruction masks for displaced stepping. */
970 #define BRANCH_MASK 0xfc000000
971 #define BP_MASK 0xFC0007FE
972 #define B_INSN 0x48000000
973 #define BC_INSN 0x40000000
974 #define BXL_INSN 0x4c000000
975 #define BP_INSN 0x7C000008
976 
977 /* Fix up the state of registers and memory after having single-stepped
978  a displaced instruction. */
979 static void
980 ppc_displaced_step_fixup (struct gdbarch *gdbarch,
981  struct displaced_step_closure *closure,
983  struct regcache *regs)
984 {
985  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
986  /* Since we use simple_displaced_step_copy_insn, our closure is a
987  copy of the instruction. */
988  ULONGEST insn = extract_unsigned_integer ((gdb_byte *) closure,
989  PPC_INSN_SIZE, byte_order);
990  ULONGEST opcode = 0;
991  /* Offset for non PC-relative instructions. */
993 
994  opcode = insn & BRANCH_MASK;
995 
996  if (debug_displaced)
998  "displaced: (ppc) fixup (%s, %s)\n",
999  paddress (gdbarch, from), paddress (gdbarch, to));
1000 
1001 
1002  /* Handle PC-relative branch instructions. */
1003  if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN)
1004  {
1005  ULONGEST current_pc;
1006 
1007  /* Read the current PC value after the instruction has been executed
1008  in a displaced location. Calculate the offset to be applied to the
1009  original PC value before the displaced stepping. */
1011  &current_pc);
1012  offset = current_pc - to;
1013 
1014  if (opcode != BXL_INSN)
1015  {
1016  /* Check for AA bit indicating whether this is an absolute
1017  addressing or PC-relative (1: absolute, 0: relative). */
1018  if (!(insn & 0x2))
1019  {
1020  /* PC-relative addressing is being used in the branch. */
1021  if (debug_displaced)
1023  (gdb_stdlog,
1024  "displaced: (ppc) branch instruction: %s\n"
1025  "displaced: (ppc) adjusted PC from %s to %s\n",
1026  paddress (gdbarch, insn), paddress (gdbarch, current_pc),
1027  paddress (gdbarch, from + offset));
1028 
1030  gdbarch_pc_regnum (gdbarch),
1031  from + offset);
1032  }
1033  }
1034  else
1035  {
1036  /* If we're here, it means we have a branch to LR or CTR. If the
1037  branch was taken, the offset is probably greater than 4 (the next
1038  instruction), so it's safe to assume that an offset of 4 means we
1039  did not take the branch. */
1040  if (offset == PPC_INSN_SIZE)
1042  from + PPC_INSN_SIZE);
1043  }
1044 
1045  /* Check for LK bit indicating whether we should set the link
1046  register to point to the next instruction
1047  (1: Set, 0: Don't set). */
1048  if (insn & 0x1)
1049  {
1050  /* Link register needs to be set to the next instruction's PC. */
1052  gdbarch_tdep (gdbarch)->ppc_lr_regnum,
1053  from + PPC_INSN_SIZE);
1054  if (debug_displaced)
1056  "displaced: (ppc) adjusted LR to %s\n",
1057  paddress (gdbarch, from + PPC_INSN_SIZE));
1058 
1059  }
1060  }
1061  /* Check for breakpoints in the inferior. If we've found one, place the PC
1062  right at the breakpoint instruction. */
1063  else if ((insn & BP_MASK) == BP_INSN)
1064  regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from);
1065  else
1066  /* Handle any other instructions that do not fit in the categories above. */
1068  from + offset);
1069 }
1070 
1071 /* Always use hardware single-stepping to execute the
1072  displaced instruction. */
1073 static int
1074 ppc_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
1075  struct displaced_step_closure *closure)
1076 {
1077  return 1;
1078 }
1079 
1080 /* Instruction masks used during single-stepping of atomic sequences. */
1081 #define LWARX_MASK 0xfc0007fe
1082 #define LWARX_INSTRUCTION 0x7c000028
1083 #define LDARX_INSTRUCTION 0x7c0000A8
1084 #define STWCX_MASK 0xfc0007ff
1085 #define STWCX_INSTRUCTION 0x7c00012d
1086 #define STDCX_INSTRUCTION 0x7c0001ad
1087 
1088 /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
1089  instruction and ending with a STWCX/STDCX instruction. If such a sequence
1090  is found, attempt to step through it. A breakpoint is placed at the end of
1091  the sequence. */
1092 
1093 int
1095 {
1096  struct gdbarch *gdbarch = get_frame_arch (frame);
1097  struct address_space *aspace = get_frame_address_space (frame);
1098  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1099  CORE_ADDR pc = get_frame_pc (frame);
1100  CORE_ADDR breaks[2] = {-1, -1};
1101  CORE_ADDR loc = pc;
1102  CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
1103  int insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
1104  int insn_count;
1105  int index;
1106  int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
1107  const int atomic_sequence_length = 16; /* Instruction sequence length. */
1108  int opcode; /* Branch instruction's OPcode. */
1109  int bc_insn_count = 0; /* Conditional branch instruction count. */
1110 
1111  /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1112  if ((insn & LWARX_MASK) != LWARX_INSTRUCTION
1113  && (insn & LWARX_MASK) != LDARX_INSTRUCTION)
1114  return 0;
1115 
1116  /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1117  instructions. */
1118  for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
1119  {
1120  loc += PPC_INSN_SIZE;
1121  insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
1122 
1123  /* Assume that there is at most one conditional branch in the atomic
1124  sequence. If a conditional branch is found, put a breakpoint in
1125  its destination address. */
1126  if ((insn & BRANCH_MASK) == BC_INSN)
1127  {
1128  int immediate = ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1129  int absolute = insn & 2;
1130 
1131  if (bc_insn_count >= 1)
1132  return 0; /* More than one conditional branch found, fallback
1133  to the standard single-step code. */
1134 
1135  if (absolute)
1136  breaks[1] = immediate;
1137  else
1138  breaks[1] = loc + immediate;
1139 
1140  bc_insn_count++;
1141  last_breakpoint++;
1142  }
1143 
1144  if ((insn & STWCX_MASK) == STWCX_INSTRUCTION
1145  || (insn & STWCX_MASK) == STDCX_INSTRUCTION)
1146  break;
1147  }
1148 
1149  /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1150  if ((insn & STWCX_MASK) != STWCX_INSTRUCTION
1151  && (insn & STWCX_MASK) != STDCX_INSTRUCTION)
1152  return 0;
1153 
1154  closing_insn = loc;
1155  loc += PPC_INSN_SIZE;
1156  insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
1157 
1158  /* Insert a breakpoint right after the end of the atomic sequence. */
1159  breaks[0] = loc;
1160 
1161  /* Check for duplicated breakpoints. Check also for a breakpoint
1162  placed (branch instruction's destination) anywhere in sequence. */
1163  if (last_breakpoint
1164  && (breaks[1] == breaks[0]
1165  || (breaks[1] >= pc && breaks[1] <= closing_insn)))
1166  last_breakpoint = 0;
1167 
1168  /* Effectively inserts the breakpoints. */
1169  for (index = 0; index <= last_breakpoint; index++)
1170  insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
1171 
1172  return 1;
1173 }
1174 
1175 
1176 #define SIGNED_SHORT(x) \
1177  ((sizeof (short) == 2) \
1178  ? ((int)(short)(x)) \
1179  : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1180 
1181 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1182 
1183 /* Limit the number of skipped non-prologue instructions, as the examining
1184  of the prologue is expensive. */
1186 
1187 /* Return nonzero if the given instruction OP can be part of the prologue
1188  of a function and saves a parameter on the stack. FRAMEP should be
1189  set if one of the previous instructions in the function has set the
1190  Frame Pointer. */
1191 
1192 static int
1193 store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
1194 {
1195  /* Move parameters from argument registers to temporary register. */
1196  if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1197  {
1198  /* Rx must be scratch register r0. */
1199  const int rx_regno = (op >> 16) & 31;
1200  /* Ry: Only r3 - r10 are used for parameter passing. */
1201  const int ry_regno = GET_SRC_REG (op);
1202 
1203  if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
1204  {
1205  *r0_contains_arg = 1;
1206  return 1;
1207  }
1208  else
1209  return 0;
1210  }
1211 
1212  /* Save a General Purpose Register on stack. */
1213 
1214  if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1215  (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1216  {
1217  /* Rx: Only r3 - r10 are used for parameter passing. */
1218  const int rx_regno = GET_SRC_REG (op);
1219 
1220  return (rx_regno >= 3 && rx_regno <= 10);
1221  }
1222 
1223  /* Save a General Purpose Register on stack via the Frame Pointer. */
1224 
1225  if (framep &&
1226  ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1227  (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1228  (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1229  {
1230  /* Rx: Usually, only r3 - r10 are used for parameter passing.
1231  However, the compiler sometimes uses r0 to hold an argument. */
1232  const int rx_regno = GET_SRC_REG (op);
1233 
1234  return ((rx_regno >= 3 && rx_regno <= 10)
1235  || (rx_regno == 0 && *r0_contains_arg));
1236  }
1237 
1238  if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1239  {
1240  /* Only f2 - f8 are used for parameter passing. */
1241  const int src_regno = GET_SRC_REG (op);
1242 
1243  return (src_regno >= 2 && src_regno <= 8);
1244  }
1245 
1246  if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1247  {
1248  /* Only f2 - f8 are used for parameter passing. */
1249  const int src_regno = GET_SRC_REG (op);
1250 
1251  return (src_regno >= 2 && src_regno <= 8);
1252  }
1253 
1254  /* Not an insn that saves a parameter on stack. */
1255  return 0;
1256 }
1257 
1258 /* Assuming that INSN is a "bl" instruction located at PC, return
1259  nonzero if the destination of the branch is a "blrl" instruction.
1260 
1261  This sequence is sometimes found in certain function prologues.
1262  It allows the function to load the LR register with a value that
1263  they can use to access PIC data using PC-relative offsets. */
1264 
1265 static int
1266 bl_to_blrl_insn_p (CORE_ADDR pc, int insn, enum bfd_endian byte_order)
1267 {
1268  CORE_ADDR dest;
1269  int immediate;
1270  int absolute;
1271  int dest_insn;
1272 
1273  absolute = (int) ((insn >> 1) & 1);
1274  immediate = ((insn & ~3) << 6) >> 6;
1275  if (absolute)
1276  dest = immediate;
1277  else
1278  dest = pc + immediate;
1279 
1280  dest_insn = read_memory_integer (dest, 4, byte_order);
1281  if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
1282  return 1;
1283 
1284  return 0;
1285 }
1286 
1287 /* Masks for decoding a branch-and-link (bl) instruction.
1288 
1289  BL_MASK and BL_INSTRUCTION are used in combination with each other.
1290  The former is anded with the opcode in question; if the result of
1291  this masking operation is equal to BL_INSTRUCTION, then the opcode in
1292  question is a ``bl'' instruction.
1293 
1294  BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1295  the branch displacement. */
1296 
1297 #define BL_MASK 0xfc000001
1298 #define BL_INSTRUCTION 0x48000001
1299 #define BL_DISPLACEMENT_MASK 0x03fffffc
1300 
1301 static unsigned long
1302 rs6000_fetch_instruction (struct gdbarch *gdbarch, const CORE_ADDR pc)
1303 {
1304  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1305  gdb_byte buf[4];
1306  unsigned long op;
1307 
1308  /* Fetch the instruction and convert it to an integer. */
1309  if (target_read_memory (pc, buf, 4))
1310  return 0;
1311  op = extract_unsigned_integer (buf, 4, byte_order);
1312 
1313  return op;
1314 }
1315 
1316 /* GCC generates several well-known sequences of instructions at the begining
1317  of each function prologue when compiling with -fstack-check. If one of
1318  such sequences starts at START_PC, then return the address of the
1319  instruction immediately past this sequence. Otherwise, return START_PC. */
1320 
1321 static CORE_ADDR
1322 rs6000_skip_stack_check (struct gdbarch *gdbarch, const CORE_ADDR start_pc)
1323 {
1324  CORE_ADDR pc = start_pc;
1325  unsigned long op = rs6000_fetch_instruction (gdbarch, pc);
1326 
1327  /* First possible sequence: A small number of probes.
1328  stw 0, -<some immediate>(1)
1329  [repeat this instruction any (small) number of times]. */
1330 
1331  if ((op & 0xffff0000) == 0x90010000)
1332  {
1333  while ((op & 0xffff0000) == 0x90010000)
1334  {
1335  pc = pc + 4;
1336  op = rs6000_fetch_instruction (gdbarch, pc);
1337  }
1338  return pc;
1339  }
1340 
1341  /* Second sequence: A probing loop.
1342  addi 12,1,-<some immediate>
1343  lis 0,-<some immediate>
1344  [possibly ori 0,0,<some immediate>]
1345  add 0,12,0
1346  cmpw 0,12,0
1347  beq 0,<disp>
1348  addi 12,12,-<some immediate>
1349  stw 0,0(12)
1350  b <disp>
1351  [possibly one last probe: stw 0,<some immediate>(12)]. */
1352 
1353  while (1)
1354  {
1355  /* addi 12,1,-<some immediate> */
1356  if ((op & 0xffff0000) != 0x39810000)
1357  break;
1358 
1359  /* lis 0,-<some immediate> */
1360  pc = pc + 4;
1361  op = rs6000_fetch_instruction (gdbarch, pc);
1362  if ((op & 0xffff0000) != 0x3c000000)
1363  break;
1364 
1365  pc = pc + 4;
1366  op = rs6000_fetch_instruction (gdbarch, pc);
1367  /* [possibly ori 0,0,<some immediate>] */
1368  if ((op & 0xffff0000) == 0x60000000)
1369  {
1370  pc = pc + 4;
1371  op = rs6000_fetch_instruction (gdbarch, pc);
1372  }
1373  /* add 0,12,0 */
1374  if (op != 0x7c0c0214)
1375  break;
1376 
1377  /* cmpw 0,12,0 */
1378  pc = pc + 4;
1379  op = rs6000_fetch_instruction (gdbarch, pc);
1380  if (op != 0x7c0c0000)
1381  break;
1382 
1383  /* beq 0,<disp> */
1384  pc = pc + 4;
1385  op = rs6000_fetch_instruction (gdbarch, pc);
1386  if ((op & 0xff9f0001) != 0x41820000)
1387  break;
1388 
1389  /* addi 12,12,-<some immediate> */
1390  pc = pc + 4;
1391  op = rs6000_fetch_instruction (gdbarch, pc);
1392  if ((op & 0xffff0000) != 0x398c0000)
1393  break;
1394 
1395  /* stw 0,0(12) */
1396  pc = pc + 4;
1397  op = rs6000_fetch_instruction (gdbarch, pc);
1398  if (op != 0x900c0000)
1399  break;
1400 
1401  /* b <disp> */
1402  pc = pc + 4;
1403  op = rs6000_fetch_instruction (gdbarch, pc);
1404  if ((op & 0xfc000001) != 0x48000000)
1405  break;
1406 
1407  /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1408  pc = pc + 4;
1409  op = rs6000_fetch_instruction (gdbarch, pc);
1410  if ((op & 0xffff0000) == 0x900c0000)
1411  {
1412  pc = pc + 4;
1413  op = rs6000_fetch_instruction (gdbarch, pc);
1414  }
1415 
1416  /* We found a valid stack-check sequence, return the new PC. */
1417  return pc;
1418  }
1419 
1420  /* Third sequence: No probe; instead, a comparizon between the stack size
1421  limit (saved in a run-time global variable) and the current stack
1422  pointer:
1423 
1424  addi 0,1,-<some immediate>
1425  lis 12,__gnat_stack_limit@ha
1426  lwz 12,__gnat_stack_limit@l(12)
1427  twllt 0,12
1428 
1429  or, with a small variant in the case of a bigger stack frame:
1430  addis 0,1,<some immediate>
1431  addic 0,0,-<some immediate>
1432  lis 12,__gnat_stack_limit@ha
1433  lwz 12,__gnat_stack_limit@l(12)
1434  twllt 0,12
1435  */
1436  while (1)
1437  {
1438  /* addi 0,1,-<some immediate> */
1439  if ((op & 0xffff0000) != 0x38010000)
1440  {
1441  /* small stack frame variant not recognized; try the
1442  big stack frame variant: */
1443 
1444  /* addis 0,1,<some immediate> */
1445  if ((op & 0xffff0000) != 0x3c010000)
1446  break;
1447 
1448  /* addic 0,0,-<some immediate> */
1449  pc = pc + 4;
1450  op = rs6000_fetch_instruction (gdbarch, pc);
1451  if ((op & 0xffff0000) != 0x30000000)
1452  break;
1453  }
1454 
1455  /* lis 12,<some immediate> */
1456  pc = pc + 4;
1457  op = rs6000_fetch_instruction (gdbarch, pc);
1458  if ((op & 0xffff0000) != 0x3d800000)
1459  break;
1460 
1461  /* lwz 12,<some immediate>(12) */
1462  pc = pc + 4;
1463  op = rs6000_fetch_instruction (gdbarch, pc);
1464  if ((op & 0xffff0000) != 0x818c0000)
1465  break;
1466 
1467  /* twllt 0,12 */
1468  pc = pc + 4;
1469  op = rs6000_fetch_instruction (gdbarch, pc);
1470  if ((op & 0xfffffffe) != 0x7c406008)
1471  break;
1472 
1473  /* We found a valid stack-check sequence, return the new PC. */
1474  return pc;
1475  }
1476 
1477  /* No stack check code in our prologue, return the start_pc. */
1478  return start_pc;
1479 }
1480 
1481 /* return pc value after skipping a function prologue and also return
1482  information about a function frame.
1483 
1484  in struct rs6000_framedata fdata:
1485  - frameless is TRUE, if function does not have a frame.
1486  - nosavedpc is TRUE, if function does not save %pc value in its frame.
1487  - offset is the initial size of this stack frame --- the amount by
1488  which we decrement the sp to allocate the frame.
1489  - saved_gpr is the number of the first saved gpr.
1490  - saved_fpr is the number of the first saved fpr.
1491  - saved_vr is the number of the first saved vr.
1492  - saved_ev is the number of the first saved ev.
1493  - alloca_reg is the number of the register used for alloca() handling.
1494  Otherwise -1.
1495  - gpr_offset is the offset of the first saved gpr from the previous frame.
1496  - fpr_offset is the offset of the first saved fpr from the previous frame.
1497  - vr_offset is the offset of the first saved vr from the previous frame.
1498  - ev_offset is the offset of the first saved ev from the previous frame.
1499  - lr_offset is the offset of the saved lr
1500  - cr_offset is the offset of the saved cr
1501  - vrsave_offset is the offset of the saved vrsave register. */
1502 
1503 static CORE_ADDR
1504 skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc,
1505  struct rs6000_framedata *fdata)
1506 {
1507  CORE_ADDR orig_pc = pc;
1508  CORE_ADDR last_prologue_pc = pc;
1509  CORE_ADDR li_found_pc = 0;
1510  gdb_byte buf[4];
1511  unsigned long op;
1512  long offset = 0;
1513  long vr_saved_offset = 0;
1514  int lr_reg = -1;
1515  int cr_reg = -1;
1516  int vr_reg = -1;
1517  int ev_reg = -1;
1518  long ev_offset = 0;
1519  int vrsave_reg = -1;
1520  int reg;
1521  int framep = 0;
1522  int minimal_toc_loaded = 0;
1523  int prev_insn_was_prologue_insn = 1;
1524  int num_skip_non_prologue_insns = 0;
1525  int r0_contains_arg = 0;
1526  const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch);
1527  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1528  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1529 
1530  memset (fdata, 0, sizeof (struct rs6000_framedata));
1531  fdata->saved_gpr = -1;
1532  fdata->saved_fpr = -1;
1533  fdata->saved_vr = -1;
1534  fdata->saved_ev = -1;
1535  fdata->alloca_reg = -1;
1536  fdata->frameless = 1;
1537  fdata->nosavedpc = 1;
1538  fdata->lr_register = -1;
1539 
1540  pc = rs6000_skip_stack_check (gdbarch, pc);
1541  if (pc >= lim_pc)
1542  pc = lim_pc;
1543 
1544  for (;; pc += 4)
1545  {
1546  /* Sometimes it isn't clear if an instruction is a prologue
1547  instruction or not. When we encounter one of these ambiguous
1548  cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1549  Otherwise, we'll assume that it really is a prologue instruction. */
1550  if (prev_insn_was_prologue_insn)
1551  last_prologue_pc = pc;
1552 
1553  /* Stop scanning if we've hit the limit. */
1554  if (pc >= lim_pc)
1555  break;
1556 
1557  prev_insn_was_prologue_insn = 1;
1558 
1559  /* Fetch the instruction and convert it to an integer. */
1560  if (target_read_memory (pc, buf, 4))
1561  break;
1562  op = extract_unsigned_integer (buf, 4, byte_order);
1563 
1564  if ((op & 0xfc1fffff) == 0x7c0802a6)
1565  { /* mflr Rx */
1566  /* Since shared library / PIC code, which needs to get its
1567  address at runtime, can appear to save more than one link
1568  register vis:
1569 
1570  *INDENT-OFF*
1571  stwu r1,-304(r1)
1572  mflr r3
1573  bl 0xff570d0 (blrl)
1574  stw r30,296(r1)
1575  mflr r30
1576  stw r31,300(r1)
1577  stw r3,308(r1);
1578  ...
1579  *INDENT-ON*
1580 
1581  remember just the first one, but skip over additional
1582  ones. */
1583  if (lr_reg == -1)
1584  lr_reg = (op & 0x03e00000) >> 21;
1585  if (lr_reg == 0)
1586  r0_contains_arg = 0;
1587  continue;
1588  }
1589  else if ((op & 0xfc1fffff) == 0x7c000026)
1590  { /* mfcr Rx */
1591  cr_reg = (op & 0x03e00000);
1592  if (cr_reg == 0)
1593  r0_contains_arg = 0;
1594  continue;
1595 
1596  }
1597  else if ((op & 0xfc1f0000) == 0xd8010000)
1598  { /* stfd Rx,NUM(r1) */
1599  reg = GET_SRC_REG (op);
1600  if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
1601  {
1602  fdata->saved_fpr = reg;
1603  fdata->fpr_offset = SIGNED_SHORT (op) + offset;
1604  }
1605  continue;
1606 
1607  }
1608  else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1609  (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1610  (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1611  (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1612  {
1613 
1614  reg = GET_SRC_REG (op);
1615  if ((op & 0xfc1f0000) == 0xbc010000)
1616  fdata->gpr_mask |= ~((1U << reg) - 1);
1617  else
1618  fdata->gpr_mask |= 1U << reg;
1619  if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1620  {
1621  fdata->saved_gpr = reg;
1622  if ((op & 0xfc1f0003) == 0xf8010000)
1623  op &= ~3UL;
1624  fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1625  }
1626  continue;
1627 
1628  }
1629  else if ((op & 0xffff0000) == 0x3c4c0000
1630  || (op & 0xffff0000) == 0x3c400000
1631  || (op & 0xffff0000) == 0x38420000)
1632  {
1633  /* . 0: addis 2,12,.TOC.-0b@ha
1634  . addi 2,2,.TOC.-0b@l
1635  or
1636  . lis 2,.TOC.@ha
1637  . addi 2,2,.TOC.@l
1638  used by ELFv2 global entry points to set up r2. */
1639  continue;
1640  }
1641  else if (op == 0x60000000)
1642  {
1643  /* nop */
1644  /* Allow nops in the prologue, but do not consider them to
1645  be part of the prologue unless followed by other prologue
1646  instructions. */
1647  prev_insn_was_prologue_insn = 0;
1648  continue;
1649 
1650  }
1651  else if ((op & 0xffff0000) == 0x3c000000)
1652  { /* addis 0,0,NUM, used for >= 32k frames */
1653  fdata->offset = (op & 0x0000ffff) << 16;
1654  fdata->frameless = 0;
1655  r0_contains_arg = 0;
1656  continue;
1657 
1658  }
1659  else if ((op & 0xffff0000) == 0x60000000)
1660  { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1661  fdata->offset |= (op & 0x0000ffff);
1662  fdata->frameless = 0;
1663  r0_contains_arg = 0;
1664  continue;
1665 
1666  }
1667  else if (lr_reg >= 0 &&
1668  /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1669  (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1670  /* stw Rx, NUM(r1) */
1671  ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1672  /* stwu Rx, NUM(r1) */
1673  ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1674  { /* where Rx == lr */
1675  fdata->lr_offset = offset;
1676  fdata->nosavedpc = 0;
1677  /* Invalidate lr_reg, but don't set it to -1.
1678  That would mean that it had never been set. */
1679  lr_reg = -2;
1680  if ((op & 0xfc000003) == 0xf8000000 || /* std */
1681  (op & 0xfc000000) == 0x90000000) /* stw */
1682  {
1683  /* Does not update r1, so add displacement to lr_offset. */
1684  fdata->lr_offset += SIGNED_SHORT (op);
1685  }
1686  continue;
1687 
1688  }
1689  else if (cr_reg >= 0 &&
1690  /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1691  (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1692  /* stw Rx, NUM(r1) */
1693  ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1694  /* stwu Rx, NUM(r1) */
1695  ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1696  { /* where Rx == cr */
1697  fdata->cr_offset = offset;
1698  /* Invalidate cr_reg, but don't set it to -1.
1699  That would mean that it had never been set. */
1700  cr_reg = -2;
1701  if ((op & 0xfc000003) == 0xf8000000 ||
1702  (op & 0xfc000000) == 0x90000000)
1703  {
1704  /* Does not update r1, so add displacement to cr_offset. */
1705  fdata->cr_offset += SIGNED_SHORT (op);
1706  }
1707  continue;
1708 
1709  }
1710  else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1711  {
1712  /* bcl 20,xx,.+4 is used to get the current PC, with or without
1713  prediction bits. If the LR has already been saved, we can
1714  skip it. */
1715  continue;
1716  }
1717  else if (op == 0x48000005)
1718  { /* bl .+4 used in
1719  -mrelocatable */
1720  fdata->used_bl = 1;
1721  continue;
1722 
1723  }
1724  else if (op == 0x48000004)
1725  { /* b .+4 (xlc) */
1726  break;
1727 
1728  }
1729  else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1730  in V.4 -mminimal-toc */
1731  (op & 0xffff0000) == 0x3bde0000)
1732  { /* addi 30,30,foo@l */
1733  continue;
1734 
1735  }
1736  else if ((op & 0xfc000001) == 0x48000001)
1737  { /* bl foo,
1738  to save fprs??? */
1739 
1740  fdata->frameless = 0;
1741 
1742  /* If the return address has already been saved, we can skip
1743  calls to blrl (for PIC). */
1744  if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op, byte_order))
1745  {
1746  fdata->used_bl = 1;
1747  continue;
1748  }
1749 
1750  /* Don't skip over the subroutine call if it is not within
1751  the first three instructions of the prologue and either
1752  we have no line table information or the line info tells
1753  us that the subroutine call is not part of the line
1754  associated with the prologue. */
1755  if ((pc - orig_pc) > 8)
1756  {
1757  struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1758  struct symtab_and_line this_sal = find_pc_line (pc, 0);
1759 
1760  if ((prologue_sal.line == 0)
1761  || (prologue_sal.line != this_sal.line))
1762  break;
1763  }
1764 
1765  op = read_memory_integer (pc + 4, 4, byte_order);
1766 
1767  /* At this point, make sure this is not a trampoline
1768  function (a function that simply calls another functions,
1769  and nothing else). If the next is not a nop, this branch
1770  was part of the function prologue. */
1771 
1772  if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
1773  break; /* Don't skip over
1774  this branch. */
1775 
1776  fdata->used_bl = 1;
1777  continue;
1778  }
1779  /* update stack pointer */
1780  else if ((op & 0xfc1f0000) == 0x94010000)
1781  { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1782  fdata->frameless = 0;
1783  fdata->offset = SIGNED_SHORT (op);
1784  offset = fdata->offset;
1785  continue;
1786  }
1787  else if ((op & 0xfc1f016a) == 0x7c01016e)
1788  { /* stwux rX,r1,rY */
1789  /* No way to figure out what r1 is going to be. */
1790  fdata->frameless = 0;
1791  offset = fdata->offset;
1792  continue;
1793  }
1794  else if ((op & 0xfc1f0003) == 0xf8010001)
1795  { /* stdu rX,NUM(r1) */
1796  fdata->frameless = 0;
1797  fdata->offset = SIGNED_SHORT (op & ~3UL);
1798  offset = fdata->offset;
1799  continue;
1800  }
1801  else if ((op & 0xfc1f016a) == 0x7c01016a)
1802  { /* stdux rX,r1,rY */
1803  /* No way to figure out what r1 is going to be. */
1804  fdata->frameless = 0;
1805  offset = fdata->offset;
1806  continue;
1807  }
1808  else if ((op & 0xffff0000) == 0x38210000)
1809  { /* addi r1,r1,SIMM */
1810  fdata->frameless = 0;
1811  fdata->offset += SIGNED_SHORT (op);
1812  offset = fdata->offset;
1813  continue;
1814  }
1815  /* Load up minimal toc pointer. Do not treat an epilogue restore
1816  of r31 as a minimal TOC load. */
1817  else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1818  (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
1819  && !framep
1820  && !minimal_toc_loaded)
1821  {
1822  minimal_toc_loaded = 1;
1823  continue;
1824 
1825  /* move parameters from argument registers to local variable
1826  registers */
1827  }
1828  else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1829  (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1830  (((op >> 21) & 31) <= 10) &&
1831  ((long) ((op >> 16) & 31)
1832  >= fdata->saved_gpr)) /* Rx: local var reg */
1833  {
1834  continue;
1835 
1836  /* store parameters in stack */
1837  }
1838  /* Move parameters from argument registers to temporary register. */
1839  else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
1840  {
1841  continue;
1842 
1843  /* Set up frame pointer */
1844  }
1845  else if (op == 0x603d0000) /* oril r29, r1, 0x0 */
1846  {
1847  fdata->frameless = 0;
1848  framep = 1;
1849  fdata->alloca_reg = (tdep->ppc_gp0_regnum + 29);
1850  continue;
1851 
1852  /* Another way to set up the frame pointer. */
1853  }
1854  else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1855  || op == 0x7c3f0b78)
1856  { /* mr r31, r1 */
1857  fdata->frameless = 0;
1858  framep = 1;
1859  fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
1860  continue;
1861 
1862  /* Another way to set up the frame pointer. */
1863  }
1864  else if ((op & 0xfc1fffff) == 0x38010000)
1865  { /* addi rX, r1, 0x0 */
1866  fdata->frameless = 0;
1867  framep = 1;
1868  fdata->alloca_reg = (tdep->ppc_gp0_regnum
1869  + ((op & ~0x38010000) >> 21));
1870  continue;
1871  }
1872  /* AltiVec related instructions. */
1873  /* Store the vrsave register (spr 256) in another register for
1874  later manipulation, or load a register into the vrsave
1875  register. 2 instructions are used: mfvrsave and
1876  mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1877  and mtspr SPR256, Rn. */
1878  /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1879  mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1880  else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1881  {
1882  vrsave_reg = GET_SRC_REG (op);
1883  continue;
1884  }
1885  else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1886  {
1887  continue;
1888  }
1889  /* Store the register where vrsave was saved to onto the stack:
1890  rS is the register where vrsave was stored in a previous
1891  instruction. */
1892  /* 100100 sssss 00001 dddddddd dddddddd */
1893  else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1894  {
1895  if (vrsave_reg == GET_SRC_REG (op))
1896  {
1897  fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1898  vrsave_reg = -1;
1899  }
1900  continue;
1901  }
1902  /* Compute the new value of vrsave, by modifying the register
1903  where vrsave was saved to. */
1904  else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1905  || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1906  {
1907  continue;
1908  }
1909  /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1910  in a pair of insns to save the vector registers on the
1911  stack. */
1912  /* 001110 00000 00000 iiii iiii iiii iiii */
1913  /* 001110 01110 00000 iiii iiii iiii iiii */
1914  else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1915  || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1916  {
1917  if ((op & 0xffff0000) == 0x38000000)
1918  r0_contains_arg = 0;
1919  li_found_pc = pc;
1920  vr_saved_offset = SIGNED_SHORT (op);
1921 
1922  /* This insn by itself is not part of the prologue, unless
1923  if part of the pair of insns mentioned above. So do not
1924  record this insn as part of the prologue yet. */
1925  prev_insn_was_prologue_insn = 0;
1926  }
1927  /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1928  /* 011111 sssss 11111 00000 00111001110 */
1929  else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1930  {
1931  if (pc == (li_found_pc + 4))
1932  {
1933  vr_reg = GET_SRC_REG (op);
1934  /* If this is the first vector reg to be saved, or if
1935  it has a lower number than others previously seen,
1936  reupdate the frame info. */
1937  if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1938  {
1939  fdata->saved_vr = vr_reg;
1940  fdata->vr_offset = vr_saved_offset + offset;
1941  }
1942  vr_saved_offset = -1;
1943  vr_reg = -1;
1944  li_found_pc = 0;
1945  }
1946  }
1947  /* End AltiVec related instructions. */
1948 
1949  /* Start BookE related instructions. */
1950  /* Store gen register S at (r31+uimm).
1951  Any register less than r13 is volatile, so we don't care. */
1952  /* 000100 sssss 11111 iiiii 01100100001 */
1953  else if (arch_info->mach == bfd_mach_ppc_e500
1954  && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1955  {
1956  if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1957  {
1958  unsigned int imm;
1959  ev_reg = GET_SRC_REG (op);
1960  imm = (op >> 11) & 0x1f;
1961  ev_offset = imm * 8;
1962  /* If this is the first vector reg to be saved, or if
1963  it has a lower number than others previously seen,
1964  reupdate the frame info. */
1965  if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1966  {
1967  fdata->saved_ev = ev_reg;
1968  fdata->ev_offset = ev_offset + offset;
1969  }
1970  }
1971  continue;
1972  }
1973  /* Store gen register rS at (r1+rB). */
1974  /* 000100 sssss 00001 bbbbb 01100100000 */
1975  else if (arch_info->mach == bfd_mach_ppc_e500
1976  && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1977  {
1978  if (pc == (li_found_pc + 4))
1979  {
1980  ev_reg = GET_SRC_REG (op);
1981  /* If this is the first vector reg to be saved, or if
1982  it has a lower number than others previously seen,
1983  reupdate the frame info. */
1984  /* We know the contents of rB from the previous instruction. */
1985  if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1986  {
1987  fdata->saved_ev = ev_reg;
1988  fdata->ev_offset = vr_saved_offset + offset;
1989  }
1990  vr_saved_offset = -1;
1991  ev_reg = -1;
1992  li_found_pc = 0;
1993  }
1994  continue;
1995  }
1996  /* Store gen register r31 at (rA+uimm). */
1997  /* 000100 11111 aaaaa iiiii 01100100001 */
1998  else if (arch_info->mach == bfd_mach_ppc_e500
1999  && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
2000  {
2001  /* Wwe know that the source register is 31 already, but
2002  it can't hurt to compute it. */
2003  ev_reg = GET_SRC_REG (op);
2004  ev_offset = ((op >> 11) & 0x1f) * 8;
2005  /* If this is the first vector reg to be saved, or if
2006  it has a lower number than others previously seen,
2007  reupdate the frame info. */
2008  if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
2009  {
2010  fdata->saved_ev = ev_reg;
2011  fdata->ev_offset = ev_offset + offset;
2012  }
2013 
2014  continue;
2015  }
2016  /* Store gen register S at (r31+r0).
2017  Store param on stack when offset from SP bigger than 4 bytes. */
2018  /* 000100 sssss 11111 00000 01100100000 */
2019  else if (arch_info->mach == bfd_mach_ppc_e500
2020  && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2021  {
2022  if (pc == (li_found_pc + 4))
2023  {
2024  if ((op & 0x03e00000) >= 0x01a00000)
2025  {
2026  ev_reg = GET_SRC_REG (op);
2027  /* If this is the first vector reg to be saved, or if
2028  it has a lower number than others previously seen,
2029  reupdate the frame info. */
2030  /* We know the contents of r0 from the previous
2031  instruction. */
2032  if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
2033  {
2034  fdata->saved_ev = ev_reg;
2035  fdata->ev_offset = vr_saved_offset + offset;
2036  }
2037  ev_reg = -1;
2038  }
2039  vr_saved_offset = -1;
2040  li_found_pc = 0;
2041  continue;
2042  }
2043  }
2044  /* End BookE related instructions. */
2045 
2046  else
2047  {
2048  unsigned int all_mask = ~((1U << fdata->saved_gpr) - 1);
2049 
2050  /* Not a recognized prologue instruction.
2051  Handle optimizer code motions into the prologue by continuing
2052  the search if we have no valid frame yet or if the return
2053  address is not yet saved in the frame. Also skip instructions
2054  if some of the GPRs expected to be saved are not yet saved. */
2055  if (fdata->frameless == 0 && fdata->nosavedpc == 0
2056  && (fdata->gpr_mask & all_mask) == all_mask)
2057  break;
2058 
2059  if (op == 0x4e800020 /* blr */
2060  || op == 0x4e800420) /* bctr */
2061  /* Do not scan past epilogue in frameless functions or
2062  trampolines. */
2063  break;
2064  if ((op & 0xf4000000) == 0x40000000) /* bxx */
2065  /* Never skip branches. */
2066  break;
2067 
2068  if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
2069  /* Do not scan too many insns, scanning insns is expensive with
2070  remote targets. */
2071  break;
2072 
2073  /* Continue scanning. */
2074  prev_insn_was_prologue_insn = 0;
2075  continue;
2076  }
2077  }
2078 
2079 #if 0
2080 /* I have problems with skipping over __main() that I need to address
2081  * sometime. Previously, I used to use misc_function_vector which
2082  * didn't work as well as I wanted to be. -MGO */
2083 
2084  /* If the first thing after skipping a prolog is a branch to a function,
2085  this might be a call to an initializer in main(), introduced by gcc2.
2086  We'd like to skip over it as well. Fortunately, xlc does some extra
2087  work before calling a function right after a prologue, thus we can
2088  single out such gcc2 behaviour. */
2089 
2090 
2091  if ((op & 0xfc000001) == 0x48000001)
2092  { /* bl foo, an initializer function? */
2093  op = read_memory_integer (pc + 4, 4, byte_order);
2094 
2095  if (op == 0x4def7b82)
2096  { /* cror 0xf, 0xf, 0xf (nop) */
2097 
2098  /* Check and see if we are in main. If so, skip over this
2099  initializer function as well. */
2100 
2101  tmp = find_pc_misc_function (pc);
2102  if (tmp >= 0
2103  && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
2104  return pc + 8;
2105  }
2106  }
2107 #endif /* 0 */
2108 
2109  if (pc == lim_pc && lr_reg >= 0)
2110  fdata->lr_register = lr_reg;
2111 
2112  fdata->offset = -fdata->offset;
2113  return last_prologue_pc;
2114 }
2115 
2116 static CORE_ADDR
2117 rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
2118 {
2119  struct rs6000_framedata frame;
2120  CORE_ADDR limit_pc, func_addr, func_end_addr = 0;
2121 
2122  /* See if we can determine the end of the prologue via the symbol table.
2123  If so, then return either PC, or the PC after the prologue, whichever
2124  is greater. */
2125  if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr))
2126  {
2127  CORE_ADDR post_prologue_pc
2128  = skip_prologue_using_sal (gdbarch, func_addr);
2129  if (post_prologue_pc != 0)
2130  return max (pc, post_prologue_pc);
2131  }
2132 
2133  /* Can't determine prologue from the symbol table, need to examine
2134  instructions. */
2135 
2136  /* Find an upper limit on the function prologue using the debug
2137  information. If the debug information could not be used to provide
2138  that bound, then use an arbitrary large number as the upper bound. */
2139  limit_pc = skip_prologue_using_sal (gdbarch, pc);
2140  if (limit_pc == 0)
2141  limit_pc = pc + 100; /* Magic. */
2142 
2143  /* Do not allow limit_pc to be past the function end, if we know
2144  where that end is... */
2145  if (func_end_addr && limit_pc > func_end_addr)
2146  limit_pc = func_end_addr;
2147 
2148  pc = skip_prologue (gdbarch, pc, limit_pc, &frame);
2149  return pc;
2150 }
2151 
2152 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2153  in the prologue of main().
2154 
2155  The function below examines the code pointed at by PC and checks to
2156  see if it corresponds to a call to __eabi. If so, it returns the
2157  address of the instruction following that call. Otherwise, it simply
2158  returns PC. */
2159 
2160 static CORE_ADDR
2161 rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
2162 {
2163  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2164  gdb_byte buf[4];
2165  unsigned long op;
2166 
2167  if (target_read_memory (pc, buf, 4))
2168  return pc;
2169  op = extract_unsigned_integer (buf, 4, byte_order);
2170 
2171  if ((op & BL_MASK) == BL_INSTRUCTION)
2172  {
2173  CORE_ADDR displ = op & BL_DISPLACEMENT_MASK;
2174  CORE_ADDR call_dest = pc + 4 + displ;
2175  struct bound_minimal_symbol s = lookup_minimal_symbol_by_pc (call_dest);
2176 
2177  /* We check for ___eabi (three leading underscores) in addition
2178  to __eabi in case the GCC option "-fleading-underscore" was
2179  used to compile the program. */
2180  if (s.minsym != NULL
2181  && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL
2182  && (strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__eabi") == 0
2183  || strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "___eabi") == 0))
2184  pc += 4;
2185  }
2186  return pc;
2187 }
2188 
2189 /* All the ABI's require 16 byte alignment. */
2190 static CORE_ADDR
2191 rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2192 {
2193  return (addr & -16);
2194 }
2195 
2196 /* Return whether handle_inferior_event() should proceed through code
2197  starting at PC in function NAME when stepping.
2198 
2199  The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2200  handle memory references that are too distant to fit in instructions
2201  generated by the compiler. For example, if 'foo' in the following
2202  instruction:
2203 
2204  lwz r9,foo(r2)
2205 
2206  is greater than 32767, the linker might replace the lwz with a branch to
2207  somewhere in @FIX1 that does the load in 2 instructions and then branches
2208  back to where execution should continue.
2209 
2210  GDB should silently step over @FIX code, just like AIX dbx does.
2211  Unfortunately, the linker uses the "b" instruction for the
2212  branches, meaning that the link register doesn't get set.
2213  Therefore, GDB's usual step_over_function () mechanism won't work.
2214 
2215  Instead, use the gdbarch_skip_trampoline_code and
2216  gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2217  @FIX code. */
2218 
2219 static int
2220 rs6000_in_solib_return_trampoline (struct gdbarch *gdbarch,
2221  CORE_ADDR pc, const char *name)
2222 {
2223  return name && startswith (name, "@FIX");
2224 }
2225 
2226 /* Skip code that the user doesn't want to see when stepping:
2227 
2228  1. Indirect function calls use a piece of trampoline code to do context
2229  switching, i.e. to set the new TOC table. Skip such code if we are on
2230  its first instruction (as when we have single-stepped to here).
2231 
2232  2. Skip shared library trampoline code (which is different from
2233  indirect function call trampolines).
2234 
2235  3. Skip bigtoc fixup code.
2236 
2237  Result is desired PC to step until, or NULL if we are not in
2238  code that should be skipped. */
2239 
2240 static CORE_ADDR
2242 {
2243  struct gdbarch *gdbarch = get_frame_arch (frame);
2244  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2245  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2246  unsigned int ii, op;
2247  int rel;
2248  CORE_ADDR solib_target_pc;
2249  struct bound_minimal_symbol msymbol;
2250 
2251  static unsigned trampoline_code[] =
2252  {
2253  0x800b0000, /* l r0,0x0(r11) */
2254  0x90410014, /* st r2,0x14(r1) */
2255  0x7c0903a6, /* mtctr r0 */
2256  0x804b0004, /* l r2,0x4(r11) */
2257  0x816b0008, /* l r11,0x8(r11) */
2258  0x4e800420, /* bctr */
2259  0x4e800020, /* br */
2260  0
2261  };
2262 
2263  /* Check for bigtoc fixup code. */
2264  msymbol = lookup_minimal_symbol_by_pc (pc);
2265  if (msymbol.minsym
2266  && rs6000_in_solib_return_trampoline (gdbarch, pc,
2267  MSYMBOL_LINKAGE_NAME (msymbol.minsym)))
2268  {
2269  /* Double-check that the third instruction from PC is relative "b". */
2270  op = read_memory_integer (pc + 8, 4, byte_order);
2271  if ((op & 0xfc000003) == 0x48000000)
2272  {
2273  /* Extract bits 6-29 as a signed 24-bit relative word address and
2274  add it to the containing PC. */
2275  rel = ((int)(op << 6) >> 6);
2276  return pc + 8 + rel;
2277  }
2278  }
2279 
2280  /* If pc is in a shared library trampoline, return its target. */
2281  solib_target_pc = find_solib_trampoline_target (frame, pc);
2282  if (solib_target_pc)
2283  return solib_target_pc;
2284 
2285  for (ii = 0; trampoline_code[ii]; ++ii)
2286  {
2287  op = read_memory_integer (pc + (ii * 4), 4, byte_order);
2288  if (op != trampoline_code[ii])
2289  return 0;
2290  }
2291  ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination
2292  addr. */
2293  pc = read_memory_unsigned_integer (ii, tdep->wordsize, byte_order);
2294  return pc;
2295 }
2296 
2297 /* ISA-specific vector types. */
2298 
2299 static struct type *
2300 rs6000_builtin_type_vec64 (struct gdbarch *gdbarch)
2301 {
2302  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2303 
2304  if (!tdep->ppc_builtin_type_vec64)
2305  {
2306  const struct builtin_type *bt = builtin_type (gdbarch);
2307 
2308  /* The type we're building is this: */
2309 #if 0
2310  union __gdb_builtin_type_vec64
2311  {
2312  int64_t uint64;
2313  float v2_float[2];
2314  int32_t v2_int32[2];
2315  int16_t v4_int16[4];
2316  int8_t v8_int8[8];
2317  };
2318 #endif
2319 
2320  struct type *t;
2321 
2322  t = arch_composite_type (gdbarch,
2323  "__ppc_builtin_type_vec64", TYPE_CODE_UNION);
2324  append_composite_type_field (t, "uint64", bt->builtin_int64);
2325  append_composite_type_field (t, "v2_float",
2326  init_vector_type (bt->builtin_float, 2));
2327  append_composite_type_field (t, "v2_int32",
2328  init_vector_type (bt->builtin_int32, 2));
2329  append_composite_type_field (t, "v4_int16",
2330  init_vector_type (bt->builtin_int16, 4));
2331  append_composite_type_field (t, "v8_int8",
2332  init_vector_type (bt->builtin_int8, 8));
2333 
2334  TYPE_VECTOR (t) = 1;
2335  TYPE_NAME (t) = "ppc_builtin_type_vec64";
2336  tdep->ppc_builtin_type_vec64 = t;
2337  }
2338 
2339  return tdep->ppc_builtin_type_vec64;
2340 }
2341 
2342 /* Vector 128 type. */
2343 
2344 static struct type *
2345 rs6000_builtin_type_vec128 (struct gdbarch *gdbarch)
2346 {
2347  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2348 
2349  if (!tdep->ppc_builtin_type_vec128)
2350  {
2351  const struct builtin_type *bt = builtin_type (gdbarch);
2352 
2353  /* The type we're building is this
2354 
2355  type = union __ppc_builtin_type_vec128 {
2356  uint128_t uint128;
2357  double v2_double[2];
2358  float v4_float[4];
2359  int32_t v4_int32[4];
2360  int16_t v8_int16[8];
2361  int8_t v16_int8[16];
2362  }
2363  */
2364 
2365  struct type *t;
2366 
2367  t = arch_composite_type (gdbarch,
2368  "__ppc_builtin_type_vec128", TYPE_CODE_UNION);
2369  append_composite_type_field (t, "uint128", bt->builtin_uint128);
2370  append_composite_type_field (t, "v2_double",
2371  init_vector_type (bt->builtin_double, 2));
2372  append_composite_type_field (t, "v4_float",
2373  init_vector_type (bt->builtin_float, 4));
2374  append_composite_type_field (t, "v4_int32",
2375  init_vector_type (bt->builtin_int32, 4));
2376  append_composite_type_field (t, "v8_int16",
2377  init_vector_type (bt->builtin_int16, 8));
2378  append_composite_type_field (t, "v16_int8",
2379  init_vector_type (bt->builtin_int8, 16));
2380 
2381  TYPE_VECTOR (t) = 1;
2382  TYPE_NAME (t) = "ppc_builtin_type_vec128";
2383  tdep->ppc_builtin_type_vec128 = t;
2384  }
2385 
2386  return tdep->ppc_builtin_type_vec128;
2387 }
2388 
2389 /* Return the name of register number REGNO, or the empty string if it
2390  is an anonymous register. */
2391 
2392 static const char *
2393 rs6000_register_name (struct gdbarch *gdbarch, int regno)
2394 {
2395  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2396 
2397  /* The upper half "registers" have names in the XML description,
2398  but we present only the low GPRs and the full 64-bit registers
2399  to the user. */
2400  if (tdep->ppc_ev0_upper_regnum >= 0
2401  && tdep->ppc_ev0_upper_regnum <= regno
2402  && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
2403  return "";
2404 
2405  /* Hide the upper halves of the vs0~vs31 registers. */
2406  if (tdep->ppc_vsr0_regnum >= 0
2407  && tdep->ppc_vsr0_upper_regnum <= regno
2408  && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs)
2409  return "";
2410 
2411  /* Check if the SPE pseudo registers are available. */
2412  if (IS_SPE_PSEUDOREG (tdep, regno))
2413  {
2414  static const char *const spe_regnames[] = {
2415  "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2416  "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2417  "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2418  "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2419  };
2420  return spe_regnames[regno - tdep->ppc_ev0_regnum];
2421  }
2422 
2423  /* Check if the decimal128 pseudo-registers are available. */
2424  if (IS_DFP_PSEUDOREG (tdep, regno))
2425  {
2426  static const char *const dfp128_regnames[] = {
2427  "dl0", "dl1", "dl2", "dl3",
2428  "dl4", "dl5", "dl6", "dl7",
2429  "dl8", "dl9", "dl10", "dl11",
2430  "dl12", "dl13", "dl14", "dl15"
2431  };
2432  return dfp128_regnames[regno - tdep->ppc_dl0_regnum];
2433  }
2434 
2435  /* Check if this is a VSX pseudo-register. */
2436  if (IS_VSX_PSEUDOREG (tdep, regno))
2437  {
2438  static const char *const vsx_regnames[] = {
2439  "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2440  "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2441  "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2442  "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2443  "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2444  "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2445  "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2446  "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2447  "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2448  };
2449  return vsx_regnames[regno - tdep->ppc_vsr0_regnum];
2450  }
2451 
2452  /* Check if the this is a Extended FP pseudo-register. */
2453  if (IS_EFP_PSEUDOREG (tdep, regno))
2454  {
2455  static const char *const efpr_regnames[] = {
2456  "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2457  "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2458  "f46", "f47", "f48", "f49", "f50", "f51",
2459  "f52", "f53", "f54", "f55", "f56", "f57",
2460  "f58", "f59", "f60", "f61", "f62", "f63"
2461  };
2462  return efpr_regnames[regno - tdep->ppc_efpr0_regnum];
2463  }
2464 
2465  return tdesc_register_name (gdbarch, regno);
2466 }
2467 
2468 /* Return the GDB type object for the "standard" data type of data in
2469  register N. */
2470 
2471 static struct type *
2472 rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2473 {
2474  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2475 
2476  /* These are the only pseudo-registers we support. */
2477  gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
2478  || IS_DFP_PSEUDOREG (tdep, regnum)
2479  || IS_VSX_PSEUDOREG (tdep, regnum)
2480  || IS_EFP_PSEUDOREG (tdep, regnum));
2481 
2482  /* These are the e500 pseudo-registers. */
2483  if (IS_SPE_PSEUDOREG (tdep, regnum))
2484  return rs6000_builtin_type_vec64 (gdbarch);
2485  else if (IS_DFP_PSEUDOREG (tdep, regnum))
2486  /* PPC decimal128 pseudo-registers. */
2487  return builtin_type (gdbarch)->builtin_declong;
2488  else if (IS_VSX_PSEUDOREG (tdep, regnum))
2489  /* POWER7 VSX pseudo-registers. */
2490  return rs6000_builtin_type_vec128 (gdbarch);
2491  else
2492  /* POWER7 Extended FP pseudo-registers. */
2493  return builtin_type (gdbarch)->builtin_double;
2494 }
2495 
2496 /* Is REGNUM a member of REGGROUP? */
2497 static int
2498 rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2499  struct reggroup *group)
2500 {
2501  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2502 
2503  /* These are the only pseudo-registers we support. */
2504  gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
2505  || IS_DFP_PSEUDOREG (tdep, regnum)
2506  || IS_VSX_PSEUDOREG (tdep, regnum)
2507  || IS_EFP_PSEUDOREG (tdep, regnum));
2508 
2509  /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2510  if (IS_SPE_PSEUDOREG (tdep, regnum) || IS_VSX_PSEUDOREG (tdep, regnum))
2511  return group == all_reggroup || group == vector_reggroup;
2512  else
2513  /* PPC decimal128 or Extended FP pseudo-registers. */
2514  return group == all_reggroup || group == float_reggroup;
2515 }
2516 
2517 /* The register format for RS/6000 floating point registers is always
2518  double, we need a conversion if the memory format is float. */
2519 
2520 static int
2521 rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum,
2522  struct type *type)
2523 {
2524  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2525 
2526  return (tdep->ppc_fp0_regnum >= 0
2527  && regnum >= tdep->ppc_fp0_regnum
2528  && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs
2529  && TYPE_CODE (type) == TYPE_CODE_FLT
2530  && TYPE_LENGTH (type)
2531  != TYPE_LENGTH (builtin_type (gdbarch)->builtin_double));
2532 }
2533 
2534 static int
2536  int regnum,
2537  struct type *type,
2538  gdb_byte *to,
2539  int *optimizedp, int *unavailablep)
2540 {
2541  struct gdbarch *gdbarch = get_frame_arch (frame);
2543 
2544  gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2545 
2546  if (!get_frame_register_bytes (frame, regnum, 0,
2547  register_size (gdbarch, regnum),
2548  from, optimizedp, unavailablep))
2549  return 0;
2550 
2551  convert_typed_floating (from, builtin_type (gdbarch)->builtin_double,
2552  to, type);
2553  *optimizedp = *unavailablep = 0;
2554  return 1;
2555 }
2556 
2557 static void
2559  int regnum,
2560  struct type *type,
2561  const gdb_byte *from)
2562 {
2563  struct gdbarch *gdbarch = get_frame_arch (frame);
2565 
2566  gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2567 
2568  convert_typed_floating (from, type,
2569  to, builtin_type (gdbarch)->builtin_double);
2570  put_frame_register (frame, regnum, to);
2571 }
2572 
2573  /* The type of a function that moves the value of REG between CACHE
2574  or BUF --- in either direction. */
2576  int, void *);
2577 
2578 /* Move SPE vector register values between a 64-bit buffer and the two
2579  32-bit raw register halves in a regcache. This function handles
2580  both splitting a 64-bit value into two 32-bit halves, and joining
2581  two halves into a whole 64-bit value, depending on the function
2582  passed as the MOVE argument.
2583 
2584  EV_REG must be the number of an SPE evN vector register --- a
2585  pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2586  64-bit buffer.
2587 
2588  Call MOVE once for each 32-bit half of that register, passing
2589  REGCACHE, the number of the raw register corresponding to that
2590  half, and the address of the appropriate half of BUFFER.
2591 
2592  For example, passing 'regcache_raw_read' as the MOVE function will
2593  fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2594  'regcache_raw_supply' will supply the contents of BUFFER to the
2595  appropriate pair of raw registers in REGCACHE.
2596 
2597  You may need to cast away some 'const' qualifiers when passing
2598  MOVE, since this function can't tell at compile-time which of
2599  REGCACHE or BUFFER is acting as the source of the data. If C had
2600  co-variant type qualifiers, ... */
2601 
2602 static enum register_status
2604  struct regcache *regcache, int ev_reg, void *buffer)
2605 {
2606  struct gdbarch *arch = get_regcache_arch (regcache);
2607  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2608  int reg_index;
2609  gdb_byte *byte_buffer = buffer;
2610  enum register_status status;
2611 
2612  gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg));
2613 
2614  reg_index = ev_reg - tdep->ppc_ev0_regnum;
2615 
2616  if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
2617  {
2618  status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index,
2619  byte_buffer);
2620  if (status == REG_VALID)
2621  status = move (regcache, tdep->ppc_gp0_regnum + reg_index,
2622  byte_buffer + 4);
2623  }
2624  else
2625  {
2626  status = move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2627  if (status == REG_VALID)
2628  status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index,
2629  byte_buffer + 4);
2630  }
2631 
2632  return status;
2633 }
2634 
2635 static enum register_status
2637 {
2638  return regcache_raw_read (regcache, regnum, buffer);
2639 }
2640 
2641 static enum register_status
2643 {
2644  regcache_raw_write (regcache, regnum, buffer);
2645 
2646  return REG_VALID;
2647 }
2648 
2649 static enum register_status
2650 e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2651  int reg_nr, gdb_byte *buffer)
2652 {
2653  return e500_move_ev_register (do_regcache_raw_read, regcache, reg_nr, buffer);
2654 }
2655 
2656 static void
2657 e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2658  int reg_nr, const gdb_byte *buffer)
2659 {
2661  reg_nr, (void *) buffer);
2662 }
2663 
2664 /* Read method for DFP pseudo-registers. */
2665 static enum register_status
2666 dfp_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2667  int reg_nr, gdb_byte *buffer)
2668 {
2669  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2670  int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2671  enum register_status status;
2672 
2673  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2674  {
2675  /* Read two FP registers to form a whole dl register. */
2676  status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2677  2 * reg_index, buffer);
2678  if (status == REG_VALID)
2679  status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2680  2 * reg_index + 1, buffer + 8);
2681  }
2682  else
2683  {
2684  status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2685  2 * reg_index + 1, buffer);
2686  if (status == REG_VALID)
2687  status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2688  2 * reg_index, buffer + 8);
2689  }
2690 
2691  return status;
2692 }
2693 
2694 /* Write method for DFP pseudo-registers. */
2695 static void
2696 dfp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2697  int reg_nr, const gdb_byte *buffer)
2698 {
2699  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2700  int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2701 
2702  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2703  {
2704  /* Write each half of the dl register into a separate
2705  FP register. */
2706  regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2707  2 * reg_index, buffer);
2708  regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2709  2 * reg_index + 1, buffer + 8);
2710  }
2711  else
2712  {
2713  regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2714  2 * reg_index + 1, buffer);
2715  regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2716  2 * reg_index, buffer + 8);
2717  }
2718 }
2719 
2720 /* Read method for POWER7 VSX pseudo-registers. */
2721 static enum register_status
2722 vsx_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2723  int reg_nr, gdb_byte *buffer)
2724 {
2725  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2726  int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2727  enum register_status status;
2728 
2729  /* Read the portion that overlaps the VMX registers. */
2730  if (reg_index > 31)
2731  status = regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
2732  reg_index - 32, buffer);
2733  else
2734  /* Read the portion that overlaps the FPR registers. */
2735  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2736  {
2737  status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2738  reg_index, buffer);
2739  if (status == REG_VALID)
2740  status = regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2741  reg_index, buffer + 8);
2742  }
2743  else
2744  {
2745  status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2746  reg_index, buffer + 8);
2747  if (status == REG_VALID)
2748  status = regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2749  reg_index, buffer);
2750  }
2751 
2752  return status;
2753 }
2754 
2755 /* Write method for POWER7 VSX pseudo-registers. */
2756 static void
2757 vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2758  int reg_nr, const gdb_byte *buffer)
2759 {
2760  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2761  int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2762 
2763  /* Write the portion that overlaps the VMX registers. */
2764  if (reg_index > 31)
2765  regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2766  reg_index - 32, buffer);
2767  else
2768  /* Write the portion that overlaps the FPR registers. */
2769  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2770  {
2771  regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2772  reg_index, buffer);
2773  regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2774  reg_index, buffer + 8);
2775  }
2776  else
2777  {
2778  regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2779  reg_index, buffer + 8);
2780  regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2781  reg_index, buffer);
2782  }
2783 }
2784 
2785 /* Read method for POWER7 Extended FP pseudo-registers. */
2786 static enum register_status
2787 efpr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2788  int reg_nr, gdb_byte *buffer)
2789 {
2790  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2791  int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2792  int offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 0 : 8;
2793 
2794  /* Read the portion that overlaps the VMX register. */
2795  return regcache_raw_read_part (regcache, tdep->ppc_vr0_regnum + reg_index,
2796  offset, register_size (gdbarch, reg_nr),
2797  buffer);
2798 }
2799 
2800 /* Write method for POWER7 Extended FP pseudo-registers. */
2801 static void
2802 efpr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2803  int reg_nr, const gdb_byte *buffer)
2804 {
2805  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2806  int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2807  int offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 0 : 8;
2808 
2809  /* Write the portion that overlaps the VMX register. */
2810  regcache_raw_write_part (regcache, tdep->ppc_vr0_regnum + reg_index,
2811  offset, register_size (gdbarch, reg_nr),
2812  buffer);
2813 }
2814 
2815 static enum register_status
2816 rs6000_pseudo_register_read (struct gdbarch *gdbarch,
2817  struct regcache *regcache,
2818  int reg_nr, gdb_byte *buffer)
2819 {
2820  struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2821  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2822 
2823  gdb_assert (regcache_arch == gdbarch);
2824 
2825  if (IS_SPE_PSEUDOREG (tdep, reg_nr))
2826  return e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2827  else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
2828  return dfp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2829  else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2830  return vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2831  else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2832  return efpr_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2833  else
2834  internal_error (__FILE__, __LINE__,
2835  _("rs6000_pseudo_register_read: "
2836  "called on unexpected register '%s' (%d)"),
2837  gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2838 }
2839 
2840 static void
2841 rs6000_pseudo_register_write (struct gdbarch *gdbarch,
2842  struct regcache *regcache,
2843  int reg_nr, const gdb_byte *buffer)
2844 {
2845  struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2846  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2847 
2848  gdb_assert (regcache_arch == gdbarch);
2849 
2850  if (IS_SPE_PSEUDOREG (tdep, reg_nr))
2851  e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2852  else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
2853  dfp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2854  else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2855  vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2856  else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2857  efpr_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2858  else
2859  internal_error (__FILE__, __LINE__,
2860  _("rs6000_pseudo_register_write: "
2861  "called on unexpected register '%s' (%d)"),
2862  gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2863 }
2864 
2865 /* Convert a DBX STABS register number to a GDB register number. */
2866 static int
2867 rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
2868 {
2869  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2870 
2871  if (0 <= num && num <= 31)
2872  return tdep->ppc_gp0_regnum + num;
2873  else if (32 <= num && num <= 63)
2874  /* FIXME: jimb/2004-05-05: What should we do when the debug info
2875  specifies registers the architecture doesn't have? Our
2876  callers don't check the value we return. */
2877  return tdep->ppc_fp0_regnum + (num - 32);
2878  else if (77 <= num && num <= 108)
2879  return tdep->ppc_vr0_regnum + (num - 77);
2880  else if (1200 <= num && num < 1200 + 32)
2881  return tdep->ppc_ev0_upper_regnum + (num - 1200);
2882  else
2883  switch (num)
2884  {
2885  case 64:
2886  return tdep->ppc_mq_regnum;
2887  case 65:
2888  return tdep->ppc_lr_regnum;
2889  case 66:
2890  return tdep->ppc_ctr_regnum;
2891  case 76:
2892  return tdep->ppc_xer_regnum;
2893  case 109:
2894  return tdep->ppc_vrsave_regnum;
2895  case 110:
2896  return tdep->ppc_vrsave_regnum - 1; /* vscr */
2897  case 111:
2898  return tdep->ppc_acc_regnum;
2899  case 112:
2900  return tdep->ppc_spefscr_regnum;
2901  default:
2902  return num;
2903  }
2904 }
2905 
2906 
2907 /* Convert a Dwarf 2 register number to a GDB register number. */
2908 static int
2909 rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
2910 {
2911  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2912 
2913  if (0 <= num && num <= 31)
2914  return tdep->ppc_gp0_regnum + num;
2915  else if (32 <= num && num <= 63)
2916  /* FIXME: jimb/2004-05-05: What should we do when the debug info
2917  specifies registers the architecture doesn't have? Our
2918  callers don't check the value we return. */
2919  return tdep->ppc_fp0_regnum + (num - 32);
2920  else if (1124 <= num && num < 1124 + 32)
2921  return tdep->ppc_vr0_regnum + (num - 1124);
2922  else if (1200 <= num && num < 1200 + 32)
2923  return tdep->ppc_ev0_upper_regnum + (num - 1200);
2924  else
2925  switch (num)
2926  {
2927  case 64:
2928  return tdep->ppc_cr_regnum;
2929  case 67:
2930  return tdep->ppc_vrsave_regnum - 1; /* vscr */
2931  case 99:
2932  return tdep->ppc_acc_regnum;
2933  case 100:
2934  return tdep->ppc_mq_regnum;
2935  case 101:
2936  return tdep->ppc_xer_regnum;
2937  case 108:
2938  return tdep->ppc_lr_regnum;
2939  case 109:
2940  return tdep->ppc_ctr_regnum;
2941  case 356:
2942  return tdep->ppc_vrsave_regnum;
2943  case 612:
2944  return tdep->ppc_spefscr_regnum;
2945  default:
2946  return num;
2947  }
2948 }
2949 
2950 /* Translate a .eh_frame register to DWARF register, or adjust a
2951  .debug_frame register. */
2952 
2953 static int
2954 rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p)
2955 {
2956  /* GCC releases before 3.4 use GCC internal register numbering in
2957  .debug_frame (and .debug_info, et cetera). The numbering is
2958  different from the standard SysV numbering for everything except
2959  for GPRs and FPRs. We can not detect this problem in most cases
2960  - to get accurate debug info for variables living in lr, ctr, v0,
2961  et cetera, use a newer version of GCC. But we must detect
2962  one important case - lr is in column 65 in .debug_frame output,
2963  instead of 108.
2964 
2965  GCC 3.4, and the "hammer" branch, have a related problem. They
2966  record lr register saves in .debug_frame as 108, but still record
2967  the return column as 65. We fix that up too.
2968 
2969  We can do this because 65 is assigned to fpsr, and GCC never
2970  generates debug info referring to it. To add support for
2971  handwritten debug info that restores fpsr, we would need to add a
2972  producer version check to this. */
2973  if (!eh_frame_p)
2974  {
2975  if (num == 65)
2976  return 108;
2977  else
2978  return num;
2979  }
2980 
2981  /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2982  internal register numbering; translate that to the standard DWARF2
2983  register numbering. */
2984  if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */
2985  return num;
2986  else if (68 <= num && num <= 75) /* cr0-cr8 */
2987  return num - 68 + 86;
2988  else if (77 <= num && num <= 108) /* vr0-vr31 */
2989  return num - 77 + 1124;
2990  else
2991  switch (num)
2992  {
2993  case 64: /* mq */
2994  return 100;
2995  case 65: /* lr */
2996  return 108;
2997  case 66: /* ctr */
2998  return 109;
2999  case 76: /* xer */
3000  return 101;
3001  case 109: /* vrsave */
3002  return 356;
3003  case 110: /* vscr */
3004  return 67;
3005  case 111: /* spe_acc */
3006  return 99;
3007  case 112: /* spefscr */
3008  return 612;
3009  default:
3010  return num;
3011  }
3012 }
3013 
3014 
3015 /* Handling the various POWER/PowerPC variants. */
3016 
3017 /* Information about a particular processor variant. */
3018 
3019 struct variant
3020  {
3021  /* Name of this variant. */
3022  char *name;
3023 
3024  /* English description of the variant. */
3026 
3027  /* bfd_arch_info.arch corresponding to variant. */
3028  enum bfd_architecture arch;
3029 
3030  /* bfd_arch_info.mach corresponding to variant. */
3031  unsigned long mach;
3032 
3033  /* Target description for this variant. */
3034  struct target_desc **tdesc;
3035  };
3036 
3037 static struct variant variants[] =
3038 {
3039  {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
3040  bfd_mach_ppc, &tdesc_powerpc_altivec32},
3041  {"power", "POWER user-level", bfd_arch_rs6000,
3042  bfd_mach_rs6k, &tdesc_rs6000},
3043  {"403", "IBM PowerPC 403", bfd_arch_powerpc,
3044  bfd_mach_ppc_403, &tdesc_powerpc_403},
3045  {"405", "IBM PowerPC 405", bfd_arch_powerpc,
3046  bfd_mach_ppc_405, &tdesc_powerpc_405},
3047  {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
3048  bfd_mach_ppc_601, &tdesc_powerpc_601},
3049  {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
3050  bfd_mach_ppc_602, &tdesc_powerpc_602},
3051  {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
3052  bfd_mach_ppc_603, &tdesc_powerpc_603},
3053  {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
3054  604, &tdesc_powerpc_604},
3055  {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
3056  bfd_mach_ppc_403gc, &tdesc_powerpc_403gc},
3057  {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
3058  bfd_mach_ppc_505, &tdesc_powerpc_505},
3059  {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
3060  bfd_mach_ppc_860, &tdesc_powerpc_860},
3061  {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
3062  bfd_mach_ppc_750, &tdesc_powerpc_750},
3063  {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
3064  bfd_mach_ppc_7400, &tdesc_powerpc_7400},
3065  {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
3066  bfd_mach_ppc_e500, &tdesc_powerpc_e500},
3067 
3068  /* 64-bit */
3069  {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
3070  bfd_mach_ppc64, &tdesc_powerpc_altivec64},
3071  {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
3072  bfd_mach_ppc_620, &tdesc_powerpc_64},
3073  {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
3074  bfd_mach_ppc_630, &tdesc_powerpc_64},
3075  {"a35", "PowerPC A35", bfd_arch_powerpc,
3076  bfd_mach_ppc_a35, &tdesc_powerpc_64},
3077  {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
3078  bfd_mach_ppc_rs64ii, &tdesc_powerpc_64},
3079  {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
3080  bfd_mach_ppc_rs64iii, &tdesc_powerpc_64},
3081 
3082  /* FIXME: I haven't checked the register sets of the following. */
3083  {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
3084  bfd_mach_rs6k_rs1, &tdesc_rs6000},
3085  {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
3086  bfd_mach_rs6k_rsc, &tdesc_rs6000},
3087  {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
3088  bfd_mach_rs6k_rs2, &tdesc_rs6000},
3089 
3090  {0, 0, 0, 0, 0}
3091 };
3092 
3093 /* Return the variant corresponding to architecture ARCH and machine number
3094  MACH. If no such variant exists, return null. */
3095 
3096 static const struct variant *
3097 find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
3098 {
3099  const struct variant *v;
3100 
3101  for (v = variants; v->name; v++)
3102  if (arch == v->arch && mach == v->mach)
3103  return v;
3104 
3105  return NULL;
3106 }
3107 
3108 static int
3109 gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
3110 {
3111  if (info->endian == BFD_ENDIAN_BIG)
3112  return print_insn_big_powerpc (memaddr, info);
3113  else
3114  return print_insn_little_powerpc (memaddr, info);
3115 }
3116 
3117 static CORE_ADDR
3118 rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
3119 {
3120  return frame_unwind_register_unsigned (next_frame,
3121  gdbarch_pc_regnum (gdbarch));
3122 }
3123 
3124 static struct frame_id
3125 rs6000_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
3126 {
3128  (this_frame, gdbarch_sp_regnum (gdbarch)),
3129  get_frame_pc (this_frame));
3130 }
3131 
3133 {
3137 };
3138 
3139 static struct rs6000_frame_cache *
3140 rs6000_frame_cache (struct frame_info *this_frame, void **this_cache)
3141 {
3142  struct rs6000_frame_cache *cache;
3143  struct gdbarch *gdbarch = get_frame_arch (this_frame);
3144  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3145  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3146  struct rs6000_framedata fdata;
3147  int wordsize = tdep->wordsize;
3148  CORE_ADDR func, pc;
3149 
3150  if ((*this_cache) != NULL)
3151  return (*this_cache);
3152  cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
3153  (*this_cache) = cache;
3154  cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
3155 
3156  func = get_frame_func (this_frame);
3157  pc = get_frame_pc (this_frame);
3158  skip_prologue (gdbarch, func, pc, &fdata);
3159 
3160  /* Figure out the parent's stack pointer. */
3161 
3162  /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3163  address of the current frame. Things might be easier if the
3164  ->frame pointed to the outer-most address of the frame. In
3165  the mean time, the address of the prev frame is used as the
3166  base address of this frame. */
3168  (this_frame, gdbarch_sp_regnum (gdbarch));
3169 
3170  /* If the function appears to be frameless, check a couple of likely
3171  indicators that we have simply failed to find the frame setup.
3172  Two common cases of this are missing symbols (i.e.
3173  get_frame_func returns the wrong address or 0), and assembly
3174  stubs which have a fast exit path but set up a frame on the slow
3175  path.
3176 
3177  If the LR appears to return to this function, then presume that
3178  we have an ABI compliant frame that we failed to find. */
3179  if (fdata.frameless && fdata.lr_offset == 0)
3180  {
3181  CORE_ADDR saved_lr;
3182  int make_frame = 0;
3183 
3184  saved_lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum);
3185  if (func == 0 && saved_lr == pc)
3186  make_frame = 1;
3187  else if (func != 0)
3188  {
3189  CORE_ADDR saved_func = get_pc_function_start (saved_lr);
3190  if (func == saved_func)
3191  make_frame = 1;
3192  }
3193 
3194  if (make_frame)
3195  {
3196  fdata.frameless = 0;
3197  fdata.lr_offset = tdep->lr_frame_offset;
3198  }
3199  }
3200 
3201  if (!fdata.frameless)
3202  {
3203  /* Frameless really means stackless. */
3204  LONGEST backchain;
3205 
3206  if (safe_read_memory_integer (cache->base, wordsize,
3207  byte_order, &backchain))
3208  cache->base = (CORE_ADDR) backchain;
3209  }
3210 
3212  gdbarch_sp_regnum (gdbarch), cache->base);
3213 
3214  /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3215  All fpr's from saved_fpr to fp31 are saved. */
3216 
3217  if (fdata.saved_fpr >= 0)
3218  {
3219  int i;
3220  CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
3221 
3222  /* If skip_prologue says floating-point registers were saved,
3223  but the current architecture has no floating-point registers,
3224  then that's strange. But we have no indices to even record
3225  the addresses under, so we just ignore it. */
3226  if (ppc_floating_point_unit_p (gdbarch))
3227  for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
3228  {
3229  cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
3230  fpr_addr += 8;
3231  }
3232  }
3233 
3234  /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3235  All gpr's from saved_gpr to gpr31 are saved (except during the
3236  prologue). */
3237 
3238  if (fdata.saved_gpr >= 0)
3239  {
3240  int i;
3241  CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
3242  for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
3243  {
3244  if (fdata.gpr_mask & (1U << i))
3245  cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
3246  gpr_addr += wordsize;
3247  }
3248  }
3249 
3250  /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3251  All vr's from saved_vr to vr31 are saved. */
3252  if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
3253  {
3254  if (fdata.saved_vr >= 0)
3255  {
3256  int i;
3257  CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
3258  for (i = fdata.saved_vr; i < 32; i++)
3259  {
3260  cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
3261  vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
3262  }
3263  }
3264  }
3265 
3266  /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3267  All vr's from saved_ev to ev31 are saved. ????? */
3268  if (tdep->ppc_ev0_regnum != -1)
3269  {
3270  if (fdata.saved_ev >= 0)
3271  {
3272  int i;
3273  CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
3274  CORE_ADDR off = (byte_order == BFD_ENDIAN_BIG ? 4 : 0);
3275 
3276  for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
3277  {
3278  cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
3279  cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + off;
3280  ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
3281  }
3282  }
3283  }
3284 
3285  /* If != 0, fdata.cr_offset is the offset from the frame that
3286  holds the CR. */
3287  if (fdata.cr_offset != 0)
3288  cache->saved_regs[tdep->ppc_cr_regnum].addr
3289  = cache->base + fdata.cr_offset;
3290 
3291  /* If != 0, fdata.lr_offset is the offset from the frame that
3292  holds the LR. */
3293  if (fdata.lr_offset != 0)
3294  cache->saved_regs[tdep->ppc_lr_regnum].addr
3295  = cache->base + fdata.lr_offset;
3296  else if (fdata.lr_register != -1)
3297  cache->saved_regs[tdep->ppc_lr_regnum].realreg = fdata.lr_register;
3298  /* The PC is found in the link register. */
3299  cache->saved_regs[gdbarch_pc_regnum (gdbarch)] =
3300  cache->saved_regs[tdep->ppc_lr_regnum];
3301 
3302  /* If != 0, fdata.vrsave_offset is the offset from the frame that
3303  holds the VRSAVE. */
3304  if (fdata.vrsave_offset != 0)
3305  cache->saved_regs[tdep->ppc_vrsave_regnum].addr
3306  = cache->base + fdata.vrsave_offset;
3307 
3308  if (fdata.alloca_reg < 0)
3309  /* If no alloca register used, then fi->frame is the value of the
3310  %sp for this frame, and it is good enough. */
3311  cache->initial_sp
3312  = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
3313  else
3314  cache->initial_sp
3315  = get_frame_register_unsigned (this_frame, fdata.alloca_reg);
3316 
3317  return cache;
3318 }
3319 
3320 static void
3321 rs6000_frame_this_id (struct frame_info *this_frame, void **this_cache,
3322  struct frame_id *this_id)
3323 {
3324  struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
3325  this_cache);
3326  /* This marks the outermost frame. */
3327  if (info->base == 0)
3328  return;
3329 
3330  (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
3331 }
3332 
3333 static struct value *
3335  void **this_cache, int regnum)
3336 {
3337  struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
3338  this_cache);
3339  return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
3340 }
3341 
3342 static const struct frame_unwind rs6000_frame_unwind =
3343 {
3344  NORMAL_FRAME,
3348  NULL,
3350 };
3351 
3352 /* Allocate and initialize a frame cache for an epilogue frame.
3353  SP is restored and prev-PC is stored in LR. */
3354 
3355 static struct rs6000_frame_cache *
3356 rs6000_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
3357 {
3358  struct rs6000_frame_cache *cache;
3359  struct gdbarch *gdbarch = get_frame_arch (this_frame);
3360  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3361 
3362  if (*this_cache)
3363  return *this_cache;
3364 
3365  cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
3366  (*this_cache) = cache;
3367  cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
3368 
3369  TRY
3370  {
3371  /* At this point the stack looks as if we just entered the
3372  function, and the return address is stored in LR. */
3373  CORE_ADDR sp, lr;
3374 
3375  sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
3376  lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum);
3377 
3378  cache->base = sp;
3379  cache->initial_sp = sp;
3380 
3382  gdbarch_pc_regnum (gdbarch), lr);
3383  }
3384  CATCH (ex, RETURN_MASK_ERROR)
3385  {
3386  if (ex.error != NOT_AVAILABLE_ERROR)
3387  throw_exception (ex);
3388  }
3389  END_CATCH
3390 
3391  return cache;
3392 }
3393 
3394 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3395  Return the frame ID of an epilogue frame. */
3396 
3397 static void
3399  void **this_cache, struct frame_id *this_id)
3400 {
3401  CORE_ADDR pc;
3402  struct rs6000_frame_cache *info =
3403  rs6000_epilogue_frame_cache (this_frame, this_cache);
3404 
3405  pc = get_frame_func (this_frame);
3406  if (info->base == 0)
3407  (*this_id) = frame_id_build_unavailable_stack (pc);
3408  else
3409  (*this_id) = frame_id_build (info->base, pc);
3410 }
3411 
3412 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3413  Return the register value of REGNUM in previous frame. */
3414 
3415 static struct value *
3417  void **this_cache, int regnum)
3418 {
3419  struct rs6000_frame_cache *info =
3420  rs6000_epilogue_frame_cache (this_frame, this_cache);
3421  return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
3422 }
3423 
3424 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3425  Check whether this an epilogue frame. */
3426 
3427 static int
3429  struct frame_info *this_frame,
3430  void **this_prologue_cache)
3431 {
3432  if (frame_relative_level (this_frame) == 0)
3433  return rs6000_in_function_epilogue_frame_p (this_frame,
3434  get_frame_arch (this_frame),
3435  get_frame_pc (this_frame));
3436  else
3437  return 0;
3438 }
3439 
3440 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3441  a function without debug information. */
3442 
3443 static const struct frame_unwind rs6000_epilogue_frame_unwind =
3444 {
3445  NORMAL_FRAME,
3448  NULL,
3450 };
3451 
3452 
3453 static CORE_ADDR
3454 rs6000_frame_base_address (struct frame_info *this_frame, void **this_cache)
3455 {
3456  struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
3457  this_cache);
3458  return info->initial_sp;
3459 }
3460 
3461 static const struct frame_base rs6000_frame_base = {
3465  rs6000_frame_base_address
3466 };
3467 
3468 static const struct frame_base *
3470 {
3471  return &rs6000_frame_base;
3472 }
3473 
3474 /* DWARF-2 frame support. Used to handle the detection of
3475  clobbered registers during function calls. */
3476 
3477 static void
3478 ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3479  struct dwarf2_frame_state_reg *reg,
3480  struct frame_info *this_frame)
3481 {
3482  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3483 
3484  /* PPC32 and PPC64 ABI's are the same regarding volatile and
3485  non-volatile registers. We will use the same code for both. */
3486 
3487  /* Call-saved GP registers. */
3488  if ((regnum >= tdep->ppc_gp0_regnum + 14
3489  && regnum <= tdep->ppc_gp0_regnum + 31)
3490  || (regnum == tdep->ppc_gp0_regnum + 1))
3492 
3493  /* Call-clobbered GP registers. */
3494  if ((regnum >= tdep->ppc_gp0_regnum + 3
3495  && regnum <= tdep->ppc_gp0_regnum + 12)
3496  || (regnum == tdep->ppc_gp0_regnum))
3498 
3499  /* Deal with FP registers, if supported. */
3500  if (tdep->ppc_fp0_regnum >= 0)
3501  {
3502  /* Call-saved FP registers. */
3503  if ((regnum >= tdep->ppc_fp0_regnum + 14
3504  && regnum <= tdep->ppc_fp0_regnum + 31))
3506 
3507  /* Call-clobbered FP registers. */
3508  if ((regnum >= tdep->ppc_fp0_regnum
3509  && regnum <= tdep->ppc_fp0_regnum + 13))
3511  }
3512 
3513  /* Deal with ALTIVEC registers, if supported. */
3514  if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0)
3515  {
3516  /* Call-saved Altivec registers. */
3517  if ((regnum >= tdep->ppc_vr0_regnum + 20
3518  && regnum <= tdep->ppc_vr0_regnum + 31)
3519  || regnum == tdep->ppc_vrsave_regnum)
3521 
3522  /* Call-clobbered Altivec registers. */
3523  if ((regnum >= tdep->ppc_vr0_regnum
3524  && regnum <= tdep->ppc_vr0_regnum + 19))
3526  }
3527 
3528  /* Handle PC register and Stack Pointer correctly. */
3529  if (regnum == gdbarch_pc_regnum (gdbarch))
3530  reg->how = DWARF2_FRAME_REG_RA;
3531  else if (regnum == gdbarch_sp_regnum (gdbarch))
3532  reg->how = DWARF2_FRAME_REG_CFA;
3533 }
3534 
3535 
3536 /* Return true if a .gnu_attributes section exists in BFD and it
3537  indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3538  section exists in BFD and it indicates that SPE extensions are in
3539  use. Check the .gnu.attributes section first, as the binary might be
3540  compiled for SPE, but not actually using SPE instructions. */
3541 
3542 static int
3544 {
3545  asection *sect;
3546  gdb_byte *contents = NULL;
3547  bfd_size_type size;
3548  gdb_byte *ptr;
3549  int success = 0;
3550  int vector_abi;
3551 
3552  if (!abfd)
3553  return 0;
3554 
3555 #ifdef HAVE_ELF
3556  /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3557  could be using the SPE vector abi without actually using any spe
3558  bits whatsoever. But it's close enough for now. */
3559  vector_abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_GNU,
3560  Tag_GNU_Power_ABI_Vector);
3561  if (vector_abi == 3)
3562  return 1;
3563 #endif
3564 
3565  sect = bfd_get_section_by_name (abfd, ".PPC.EMB.apuinfo");
3566  if (!sect)
3567  return 0;
3568 
3569  size = bfd_get_section_size (sect);
3570  contents = xmalloc (size);
3571  if (!bfd_get_section_contents (abfd, sect, contents, 0, size))
3572  {
3573  xfree (contents);
3574  return 0;
3575  }
3576 
3577  /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3578 
3579  struct {
3580  uint32 name_len;
3581  uint32 data_len;
3582  uint32 type;
3583  char name[name_len rounded up to 4-byte alignment];
3584  char data[data_len];
3585  };
3586 
3587  Technically, there's only supposed to be one such structure in a
3588  given apuinfo section, but the linker is not always vigilant about
3589  merging apuinfo sections from input files. Just go ahead and parse
3590  them all, exiting early when we discover the binary uses SPE
3591  insns.
3592 
3593  It's not specified in what endianness the information in this
3594  section is stored. Assume that it's the endianness of the BFD. */
3595  ptr = contents;
3596  while (1)
3597  {
3598  unsigned int name_len;
3599  unsigned int data_len;
3600  unsigned int type;
3601 
3602  /* If we can't read the first three fields, we're done. */
3603  if (size < 12)
3604  break;
3605 
3606  name_len = bfd_get_32 (abfd, ptr);
3607  name_len = (name_len + 3) & ~3U; /* Round to 4 bytes. */
3608  data_len = bfd_get_32 (abfd, ptr + 4);
3609  type = bfd_get_32 (abfd, ptr + 8);
3610  ptr += 12;
3611 
3612  /* The name must be "APUinfo\0". */
3613  if (name_len != 8
3614  && strcmp ((const char *) ptr, "APUinfo") != 0)
3615  break;
3616  ptr += name_len;
3617 
3618  /* The type must be 2. */
3619  if (type != 2)
3620  break;
3621 
3622  /* The data is stored as a series of uint32. The upper half of
3623  each uint32 indicates the particular APU used and the lower
3624  half indicates the revision of that APU. We just care about
3625  the upper half. */
3626 
3627  /* Not 4-byte quantities. */
3628  if (data_len & 3U)
3629  break;
3630 
3631  while (data_len)
3632  {
3633  unsigned int apuinfo = bfd_get_32 (abfd, ptr);
3634  unsigned int apu = apuinfo >> 16;
3635  ptr += 4;
3636  data_len -= 4;
3637 
3638  /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3639  either. */
3640  if (apu == 0x100 || apu == 0x101)
3641  {
3642  success = 1;
3643  data_len = 0;
3644  }
3645  }
3646 
3647  if (success)
3648  break;
3649  }
3650 
3651  xfree (contents);
3652  return success;
3653 }
3654 
3655 /* These are macros for parsing instruction fields (I.1.6.28) */
3656 
3657 #define PPC_FIELD(value, from, len) \
3658  (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
3659 #define PPC_SEXT(v, bs) \
3660  ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
3661  ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
3662  - ((CORE_ADDR) 1 << ((bs) - 1)))
3663 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
3664 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
3665 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
3666 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
3667 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
3668 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
3669 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
3670 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
3671 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
3672 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
3673  | (PPC_FIELD (insn, 16, 5) << 5))
3674 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
3675 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
3676 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
3677 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
3678 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
3679 #define PPC_OE(insn) PPC_BIT (insn, 21)
3680 #define PPC_RC(insn) PPC_BIT (insn, 31)
3681 #define PPC_Rc(insn) PPC_BIT (insn, 21)
3682 #define PPC_LK(insn) PPC_BIT (insn, 31)
3683 #define PPC_TX(insn) PPC_BIT (insn, 31)
3684 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
3685 
3686 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
3687 #define PPC_XER_NB(xer) (xer & 0x7f)
3688 
3689 /* Record Vector-Scalar Registers.
3690  For VSR less than 32, it's represented by an FPR and an VSR-upper register.
3691  Otherwise, it's just a VR register. Record them accordingly. */
3692 
3693 static int
3694 ppc_record_vsr (struct regcache *regcache, struct gdbarch_tdep *tdep, int vsr)
3695 {
3696  if (vsr < 0 || vsr >= 64)
3697  return -1;
3698 
3699  if (vsr >= 32)
3700  {
3701  if (tdep->ppc_vr0_regnum >= 0)
3702  record_full_arch_list_add_reg (regcache, tdep->ppc_vr0_regnum + vsr - 32);
3703  }
3704  else
3705  {
3706  if (tdep->ppc_fp0_regnum >= 0)
3707  record_full_arch_list_add_reg (regcache, tdep->ppc_fp0_regnum + vsr);
3708  if (tdep->ppc_vsr0_upper_regnum >= 0)
3710  tdep->ppc_vsr0_upper_regnum + vsr);
3711  }
3712 
3713  return 0;
3714 }
3715 
3716 /* Parse and record instructions primary opcode-4 at ADDR.
3717  Return 0 if successful. */
3718 
3719 static int
3720 ppc_process_record_op4 (struct gdbarch *gdbarch, struct regcache *regcache,
3721  CORE_ADDR addr, uint32_t insn)
3722 {
3723  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3724  int ext = PPC_FIELD (insn, 21, 11);
3725 
3726  switch (ext & 0x3f)
3727  {
3728  case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
3729  case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
3730  case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
3731  case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
3733  /* FALL-THROUGH */
3734  case 42: /* Vector Select */
3735  case 43: /* Vector Permute */
3736  case 44: /* Vector Shift Left Double by Octet Immediate */
3737  case 45: /* Vector Permute and Exclusive-OR */
3738  case 60: /* Vector Add Extended Unsigned Quadword Modulo */
3739  case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
3740  case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
3741  case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
3742  case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
3743  case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
3744  case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
3745  case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
3746  case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
3747  case 46: /* Vector Multiply-Add Single-Precision */
3748  case 47: /* Vector Negative Multiply-Subtract Single-Precision */
3750  tdep->ppc_vr0_regnum + PPC_VRT (insn));
3751  return 0;
3752  }
3753 
3754  switch ((ext & 0x1ff))
3755  {
3756  /* 5.16 Decimal Integer Arithmetic Instructions */
3757  case 1: /* Decimal Add Modulo */
3758  case 65: /* Decimal Subtract Modulo */
3759 
3760  /* Bit-21 should be set. */
3761  if (!PPC_BIT (insn, 21))
3762  break;
3763 
3765  tdep->ppc_vr0_regnum + PPC_VRT (insn));
3766  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
3767  return 0;
3768  }
3769 
3770  /* Bit-21 is used for RC */
3771  switch (ext & 0x3ff)
3772  {
3773  case 6: /* Vector Compare Equal To Unsigned Byte */
3774  case 70: /* Vector Compare Equal To Unsigned Halfword */
3775  case 134: /* Vector Compare Equal To Unsigned Word */
3776  case 199: /* Vector Compare Equal To Unsigned Doubleword */
3777  case 774: /* Vector Compare Greater Than Signed Byte */
3778  case 838: /* Vector Compare Greater Than Signed Halfword */
3779  case 902: /* Vector Compare Greater Than Signed Word */
3780  case 967: /* Vector Compare Greater Than Signed Doubleword */
3781  case 518: /* Vector Compare Greater Than Unsigned Byte */
3782  case 646: /* Vector Compare Greater Than Unsigned Word */
3783  case 582: /* Vector Compare Greater Than Unsigned Halfword */
3784  case 711: /* Vector Compare Greater Than Unsigned Doubleword */
3785  case 966: /* Vector Compare Bounds Single-Precision */
3786  case 198: /* Vector Compare Equal To Single-Precision */
3787  case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
3788  case 710: /* Vector Compare Greater Than Single-Precision */
3789  if (PPC_Rc (insn))
3790  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
3792  tdep->ppc_vr0_regnum + PPC_VRT (insn));
3793  return 0;
3794  }
3795 
3796  switch (ext)
3797  {
3798  case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
3799  case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
3800  case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
3801  case 334: /* Vector Pack Signed Word Unsigned Saturate */
3802  case 398: /* Vector Pack Signed Halfword Signed Saturate */
3803  case 462: /* Vector Pack Signed Word Signed Saturate */
3804  case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
3805  case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
3806  case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
3807  case 512: /* Vector Add Unsigned Byte Saturate */
3808  case 576: /* Vector Add Unsigned Halfword Saturate */
3809  case 640: /* Vector Add Unsigned Word Saturate */
3810  case 768: /* Vector Add Signed Byte Saturate */
3811  case 832: /* Vector Add Signed Halfword Saturate */
3812  case 896: /* Vector Add Signed Word Saturate */
3813  case 1536: /* Vector Subtract Unsigned Byte Saturate */
3814  case 1600: /* Vector Subtract Unsigned Halfword Saturate */
3815  case 1664: /* Vector Subtract Unsigned Word Saturate */
3816  case 1792: /* Vector Subtract Signed Byte Saturate */
3817  case 1856: /* Vector Subtract Signed Halfword Saturate */
3818  case 1920: /* Vector Subtract Signed Word Saturate */
3819 
3820  case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
3821  case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
3822  case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
3823  case 1672: /* Vector Sum across Half Signed Word Saturate */
3824  case 1928: /* Vector Sum across Signed Word Saturate */
3825  case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
3826  case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
3828  /* FALL-THROUGH */
3829  case 12: /* Vector Merge High Byte */
3830  case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
3831  case 76: /* Vector Merge High Halfword */
3832  case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
3833  case 140: /* Vector Merge High Word */
3834  case 268: /* Vector Merge Low Byte */
3835  case 332: /* Vector Merge Low Halfword */
3836  case 396: /* Vector Merge Low Word */
3837  case 526: /* Vector Unpack High Signed Byte */
3838  case 590: /* Vector Unpack High Signed Halfword */
3839  case 654: /* Vector Unpack Low Signed Byte */
3840  case 718: /* Vector Unpack Low Signed Halfword */
3841  case 782: /* Vector Pack Pixel */
3842  case 846: /* Vector Unpack High Pixel */
3843  case 974: /* Vector Unpack Low Pixel */
3844  case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
3845  case 1614: /* Vector Unpack High Signed Word */
3846  case 1676: /* Vector Merge Odd Word */
3847  case 1742: /* Vector Unpack Low Signed Word */
3848  case 1932: /* Vector Merge Even Word */
3849  case 524: /* Vector Splat Byte */
3850  case 588: /* Vector Splat Halfword */
3851  case 652: /* Vector Splat Word */
3852  case 780: /* Vector Splat Immediate Signed Byte */
3853  case 844: /* Vector Splat Immediate Signed Halfword */
3854  case 908: /* Vector Splat Immediate Signed Word */
3855  case 452: /* Vector Shift Left */
3856  case 708: /* Vector Shift Right */
3857  case 1036: /* Vector Shift Left by Octet */
3858  case 1100: /* Vector Shift Right by Octet */
3859  case 0: /* Vector Add Unsigned Byte Modulo */
3860  case 64: /* Vector Add Unsigned Halfword Modulo */
3861  case 128: /* Vector Add Unsigned Word Modulo */
3862  case 192: /* Vector Add Unsigned Doubleword Modulo */
3863  case 256: /* Vector Add Unsigned Quadword Modulo */
3864  case 320: /* Vector Add & write Carry Unsigned Quadword */
3865  case 384: /* Vector Add and Write Carry-Out Unsigned Word */
3866  case 8: /* Vector Multiply Odd Unsigned Byte */
3867  case 72: /* Vector Multiply Odd Unsigned Halfword */
3868  case 136: /* Vector Multiply Odd Unsigned Word */
3869  case 264: /* Vector Multiply Odd Signed Byte */
3870  case 328: /* Vector Multiply Odd Signed Halfword */
3871  case 392: /* Vector Multiply Odd Signed Word */
3872  case 520: /* Vector Multiply Even Unsigned Byte */
3873  case 584: /* Vector Multiply Even Unsigned Halfword */
3874  case 648: /* Vector Multiply Even Unsigned Word */
3875  case 776: /* Vector Multiply Even Signed Byte */
3876  case 840: /* Vector Multiply Even Signed Halfword */
3877  case 904: /* Vector Multiply Even Signed Word */
3878  case 137: /* Vector Multiply Unsigned Word Modulo */
3879  case 1024: /* Vector Subtract Unsigned Byte Modulo */
3880  case 1088: /* Vector Subtract Unsigned Halfword Modulo */
3881  case 1152: /* Vector Subtract Unsigned Word Modulo */
3882  case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
3883  case 1280: /* Vector Subtract Unsigned Quadword Modulo */
3884  case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
3885  case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
3886  case 1282: /* Vector Average Signed Byte */
3887  case 1346: /* Vector Average Signed Halfword */
3888  case 1410: /* Vector Average Signed Word */
3889  case 1026: /* Vector Average Unsigned Byte */
3890  case 1090: /* Vector Average Unsigned Halfword */
3891  case 1154: /* Vector Average Unsigned Word */
3892  case 258: /* Vector Maximum Signed Byte */
3893  case 322: /* Vector Maximum Signed Halfword */
3894  case 386: /* Vector Maximum Signed Word */
3895  case 450: /* Vector Maximum Signed Doubleword */
3896  case 2: /* Vector Maximum Unsigned Byte */
3897  case 66: /* Vector Maximum Unsigned Halfword */
3898  case 130: /* Vector Maximum Unsigned Word */
3899  case 194: /* Vector Maximum Unsigned Doubleword */
3900  case 770: /* Vector Minimum Signed Byte */
3901  case 834: /* Vector Minimum Signed Halfword */
3902  case 898: /* Vector Minimum Signed Word */
3903  case 962: /* Vector Minimum Signed Doubleword */
3904  case 514: /* Vector Minimum Unsigned Byte */
3905  case 578: /* Vector Minimum Unsigned Halfword */
3906  case 642: /* Vector Minimum Unsigned Word */
3907  case 706: /* Vector Minimum Unsigned Doubleword */
3908  case 1028: /* Vector Logical AND */
3909  case 1668: /* Vector Logical Equivalent */
3910  case 1092: /* Vector Logical AND with Complement */
3911  case 1412: /* Vector Logical NAND */
3912  case 1348: /* Vector Logical OR with Complement */
3913  case 1156: /* Vector Logical OR */
3914  case 1284: /* Vector Logical NOR */
3915  case 1220: /* Vector Logical XOR */
3916  case 4: /* Vector Rotate Left Byte */
3917  case 132: /* Vector Rotate Left Word VX-form */
3918  case 68: /* Vector Rotate Left Halfword */
3919  case 196: /* Vector Rotate Left Doubleword */
3920  case 260: /* Vector Shift Left Byte */
3921  case 388: /* Vector Shift Left Word */
3922  case 324: /* Vector Shift Left Halfword */
3923  case 1476: /* Vector Shift Left Doubleword */
3924  case 516: /* Vector Shift Right Byte */
3925  case 644: /* Vector Shift Right Word */
3926  case 580: /* Vector Shift Right Halfword */
3927  case 1732: /* Vector Shift Right Doubleword */
3928  case 772: /* Vector Shift Right Algebraic Byte */
3929  case 900: /* Vector Shift Right Algebraic Word */
3930  case 836: /* Vector Shift Right Algebraic Halfword */
3931  case 964: /* Vector Shift Right Algebraic Doubleword */
3932  case 10: /* Vector Add Single-Precision */
3933  case 74: /* Vector Subtract Single-Precision */
3934  case 1034: /* Vector Maximum Single-Precision */
3935  case 1098: /* Vector Minimum Single-Precision */
3936  case 842: /* Vector Convert From Signed Fixed-Point Word */
3937  case 778: /* Vector Convert From Unsigned Fixed-Point Word */
3938  case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
3939  case 522: /* Vector Round to Single-Precision Integer Nearest */
3940  case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
3941  case 586: /* Vector Round to Single-Precision Integer toward Zero */
3942  case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
3943  case 458: /* Vector Log Base 2 Estimate Floating-Point */
3944  case 266: /* Vector Reciprocal Estimate Single-Precision */
3945  case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
3946  case 1288: /* Vector AES Cipher */
3947  case 1289: /* Vector AES Cipher Last */
3948  case 1352: /* Vector AES Inverse Cipher */
3949  case 1353: /* Vector AES Inverse Cipher Last */
3950  case 1480: /* Vector AES SubBytes */
3951  case 1730: /* Vector SHA-512 Sigma Doubleword */
3952  case 1666: /* Vector SHA-256 Sigma Word */
3953  case 1032: /* Vector Polynomial Multiply-Sum Byte */
3954  case 1160: /* Vector Polynomial Multiply-Sum Word */
3955  case 1096: /* Vector Polynomial Multiply-Sum Halfword */
3956  case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
3957  case 1292: /* Vector Gather Bits by Bytes by Doubleword */
3958  case 1794: /* Vector Count Leading Zeros Byte */
3959  case 1858: /* Vector Count Leading Zeros Halfword */
3960  case 1922: /* Vector Count Leading Zeros Word */
3961  case 1986: /* Vector Count Leading Zeros Doubleword */
3962  case 1795: /* Vector Population Count Byte */
3963  case 1859: /* Vector Population Count Halfword */
3964  case 1923: /* Vector Population Count Word */
3965  case 1987: /* Vector Population Count Doubleword */
3966  case 1356: /* Vector Bit Permute Quadword */
3968  tdep->ppc_vr0_regnum + PPC_VRT (insn));
3969  return 0;
3970 
3971  case 1604: /* Move To Vector Status and Control Register */
3973  return 0;
3974  case 1540: /* Move From Vector Status and Control Register */
3976  tdep->ppc_vr0_regnum + PPC_VRT (insn));
3977  return 0;
3978  }
3979 
3980  fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
3981  "at %s, 4-%d.\n", insn, paddress (gdbarch, addr), ext);
3982  return -1;
3983 }
3984 
3985 /* Parse and record instructions of primary opcode-19 at ADDR.
3986  Return 0 if successful. */
3987 
3988 static int
3989 ppc_process_record_op19 (struct gdbarch *gdbarch, struct regcache *regcache,
3990  CORE_ADDR addr, uint32_t insn)
3991 {
3992  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3993  int ext = PPC_EXTOP (insn);
3994 
3995  switch (ext)
3996  {
3997  case 0: /* Move Condition Register Field */
3998  case 33: /* Condition Register NOR */
3999  case 129: /* Condition Register AND with Complement */
4000  case 193: /* Condition Register XOR */
4001  case 225: /* Condition Register NAND */
4002  case 257: /* Condition Register AND */
4003  case 289: /* Condition Register Equivalent */
4004  case 417: /* Condition Register OR with Complement */
4005  case 449: /* Condition Register OR */
4006  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4007  return 0;
4008 
4009  case 16: /* Branch Conditional */
4010  case 560: /* Branch Conditional to Branch Target Address Register */
4011  if ((PPC_BO (insn) & 0x4) == 0)
4013  /* FALL-THROUGH */
4014  case 528: /* Branch Conditional to Count Register */
4015  if (PPC_LK (insn))
4016  record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum);
4017  return 0;
4018 
4019  case 150: /* Instruction Synchronize */
4020  /* Do nothing. */
4021  return 0;
4022  }
4023 
4024  fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
4025  "at %s, 19-%d.\n", insn, paddress (gdbarch, addr), ext);
4026  return -1;
4027 }
4028 
4029 /* Parse and record instructions of primary opcode-31 at ADDR.
4030  Return 0 if successful. */
4031 
4032 static int
4033 ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
4034  CORE_ADDR addr, uint32_t insn)
4035 {
4036  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4037  int ext = PPC_EXTOP (insn);
4038  int tmp, nr, nb, i;
4039  CORE_ADDR at_dcsz, ea = 0;
4040  ULONGEST rb, ra, xer;
4041  int size = 0;
4042 
4043  /* These instructions have OE bit. */
4044  switch (ext & 0x1ff)
4045  {
4046  /* These write RT and XER. Update CR if RC is set. */
4047  case 8: /* Subtract from carrying */
4048  case 10: /* Add carrying */
4049  case 136: /* Subtract from extended */
4050  case 138: /* Add extended */
4051  case 200: /* Subtract from zero extended */
4052  case 202: /* Add to zero extended */
4053  case 232: /* Subtract from minus one extended */
4054  case 234: /* Add to minus one extended */
4055  /* CA is always altered, but SO/OV are only altered when OE=1.
4056  In any case, XER is always altered. */
4058  if (PPC_RC (insn))
4059  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4061  tdep->ppc_gp0_regnum + PPC_RT (insn));
4062  return 0;
4063 
4064  /* These write RT. Update CR if RC is set and update XER if OE is set. */
4065  case 40: /* Subtract from */
4066  case 104: /* Negate */
4067  case 233: /* Multiply low doubleword */
4068  case 235: /* Multiply low word */
4069  case 266: /* Add */
4070  case 393: /* Divide Doubleword Extended Unsigned */
4071  case 395: /* Divide Word Extended Unsigned */
4072  case 425: /* Divide Doubleword Extended */
4073  case 427: /* Divide Word Extended */
4074  case 457: /* Divide Doubleword Unsigned */
4075  case 459: /* Divide Word Unsigned */
4076  case 489: /* Divide Doubleword */
4077  case 491: /* Divide Word */
4078  if (PPC_OE (insn))
4080  /* FALL-THROUGH */
4081  case 9: /* Multiply High Doubleword Unsigned */
4082  case 11: /* Multiply High Word Unsigned */
4083  case 73: /* Multiply High Doubleword */
4084  case 75: /* Multiply High Word */
4085  if (PPC_RC (insn))
4086  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4088  tdep->ppc_gp0_regnum + PPC_RT (insn));
4089  return 0;
4090  }
4091 
4092  if ((ext & 0x1f) == 15)
4093  {
4094  /* Integer Select. bit[16:20] is used for BC. */
4096  tdep->ppc_gp0_regnum + PPC_RT (insn));
4097  return 0;
4098  }
4099 
4100  switch (ext)
4101  {
4102  case 78: /* Determine Leftmost Zero Byte */
4103  if (PPC_RC (insn))
4104  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4107  tdep->ppc_gp0_regnum + PPC_RT (insn));
4108  return 0;
4109 
4110  /* These only write RT. */
4111  case 19: /* Move from condition register */
4112  /* Move From One Condition Register Field */
4113  case 74: /* Add and Generate Sixes */
4114  case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4115  case 302: /* Move From Branch History Rolling Buffer */
4116  case 339: /* Move From Special Purpose Register */
4117  case 371: /* Move From Time Base [Phased-Out] */
4119  tdep->ppc_gp0_regnum + PPC_RT (insn));
4120  return 0;
4121 
4122  /* These only write to RA. */
4123  case 51: /* Move From VSR Doubleword */
4124  case 115: /* Move From VSR Word and Zero */
4125  case 122: /* Population count bytes */
4126  case 378: /* Population count words */
4127  case 506: /* Population count doublewords */
4128  case 154: /* Parity Word */
4129  case 186: /* Parity Doubleword */
4130  case 252: /* Bit Permute Doubleword */
4131  case 282: /* Convert Declets To Binary Coded Decimal */
4132  case 314: /* Convert Binary Coded Decimal To Declets */
4133  case 508: /* Compare bytes */
4135  tdep->ppc_gp0_regnum + PPC_RA (insn));
4136  return 0;
4137 
4138  /* These write CR and optional RA. */
4139  case 792: /* Shift Right Algebraic Word */
4140  case 794: /* Shift Right Algebraic Doubleword */
4141  case 824: /* Shift Right Algebraic Word Immediate */
4142  case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
4143  case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
4146  tdep->ppc_gp0_regnum + PPC_RA (insn));
4147  /* FALL-THROUGH */
4148  case 0: /* Compare */
4149  case 32: /* Compare logical */
4150  case 144: /* Move To Condition Register Fields */
4151  /* Move To One Condition Register Field */
4152  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4153  return 0;
4154 
4155  /* These write to RT. Update RA if 'update indexed.' */
4156  case 53: /* Load Doubleword with Update Indexed */
4157  case 119: /* Load Byte and Zero with Update Indexed */
4158  case 311: /* Load Halfword and Zero with Update Indexed */
4159  case 55: /* Load Word and Zero with Update Indexed */
4160  case 375: /* Load Halfword Algebraic with Update Indexed */
4161  case 373: /* Load Word Algebraic with Update Indexed */
4163  tdep->ppc_gp0_regnum + PPC_RA (insn));
4164  /* FALL-THROUGH */
4165  case 21: /* Load Doubleword Indexed */
4166  case 52: /* Load Byte And Reserve Indexed */
4167  case 116: /* Load Halfword And Reserve Indexed */
4168  case 20: /* Load Word And Reserve Indexed */
4169  case 84: /* Load Doubleword And Reserve Indexed */
4170  case 87: /* Load Byte and Zero Indexed */
4171  case 279: /* Load Halfword and Zero Indexed */
4172  case 23: /* Load Word and Zero Indexed */
4173  case 343: /* Load Halfword Algebraic Indexed */
4174  case 341: /* Load Word Algebraic Indexed */
4175  case 790: /* Load Halfword Byte-Reverse Indexed */
4176  case 534: /* Load Word Byte-Reverse Indexed */
4177  case 532: /* Load Doubleword Byte-Reverse Indexed */
4179  tdep->ppc_gp0_regnum + PPC_RT (insn));
4180  return 0;
4181 
4182  case 597: /* Load String Word Immediate */
4183  case 533: /* Load String Word Indexed */
4184  if (ext == 597)
4185  {
4186  nr = PPC_NB (insn);
4187  if (nr == 0)
4188  nr = 32;
4189  }
4190  else
4191  {
4192  regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &xer);
4193  nr = PPC_XER_NB (xer);
4194  }
4195 
4196  nr = (nr + 3) >> 2;
4197 
4198  /* If n=0, the contents of register RT are undefined. */
4199  if (nr == 0)
4200  nr = 1;
4201 
4202  for (i = 0; i < nr; i++)
4204  tdep->ppc_gp0_regnum
4205  + ((PPC_RT (insn) + i) & 0x1f));
4206  return 0;
4207 
4208  case 276: /* Load Quadword And Reserve Indexed */
4209  tmp = tdep->ppc_gp0_regnum + (PPC_RT (insn) & ~1);
4210  record_full_arch_list_add_reg (regcache, tmp);
4211  record_full_arch_list_add_reg (regcache, tmp + 1);
4212  return 0;
4213 
4214  /* These write VRT. */
4215  case 6: /* Load Vector for Shift Left Indexed */
4216  case 38: /* Load Vector for Shift Right Indexed */
4217  case 7: /* Load Vector Element Byte Indexed */
4218  case 39: /* Load Vector Element Halfword Indexed */
4219  case 71: /* Load Vector Element Word Indexed */
4220  case 103: /* Load Vector Indexed */
4221  case 359: /* Load Vector Indexed LRU */
4223  tdep->ppc_vr0_regnum + PPC_VRT (insn));
4224  return 0;
4225 
4226  /* These write FRT. Update RA if 'update indexed.' */
4227  case 567: /* Load Floating-Point Single with Update Indexed */
4228  case 631: /* Load Floating-Point Double with Update Indexed */
4230  tdep->ppc_gp0_regnum + PPC_RA (insn));
4231  /* FALL-THROUGH */
4232  case 535: /* Load Floating-Point Single Indexed */
4233  case 599: /* Load Floating-Point Double Indexed */
4234  case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
4235  case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
4237  tdep->ppc_fp0_regnum + PPC_FRT (insn));
4238  return 0;
4239 
4240  case 791: /* Load Floating-Point Double Pair Indexed */
4241  tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1);
4242  record_full_arch_list_add_reg (regcache, tmp);
4243  record_full_arch_list_add_reg (regcache, tmp + 1);
4244  return 0;
4245 
4246  case 179: /* Move To VSR Doubleword */
4247  case 211: /* Move To VSR Word Algebraic */
4248  case 243: /* Move To VSR Word and Zero */
4249  case 588: /* Load VSX Scalar Doubleword Indexed */
4250  case 524: /* Load VSX Scalar Single-Precision Indexed */
4251  case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
4252  case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
4253  case 844: /* Load VSX Vector Doubleword*2 Indexed */
4254  case 332: /* Load VSX Vector Doubleword & Splat Indexed */
4255  case 780: /* Load VSX Vector Word*4 Indexed */
4256  ppc_record_vsr (regcache, tdep, PPC_XT (insn));
4257  return 0;
4258 
4259  /* These write RA. Update CR if RC is set. */
4260  case 24: /* Shift Left Word */
4261  case 26: /* Count Leading Zeros Word */
4262  case 27: /* Shift Left Doubleword */
4263  case 28: /* AND */
4264  case 58: /* Count Leading Zeros Doubleword */
4265  case 60: /* AND with Complement */
4266  case 124: /* NOR */
4267  case 284: /* Equivalent */
4268  case 316: /* XOR */
4269  case 476: /* NAND */
4270  case 412: /* OR with Complement */
4271  case 444: /* OR */
4272  case 536: /* Shift Right Word */
4273  case 539: /* Shift Right Doubleword */
4274  case 922: /* Extend Sign Halfword */
4275  case 954: /* Extend Sign Byte */
4276  case 986: /* Extend Sign Word */
4277  if (PPC_RC (insn))
4278  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4280  tdep->ppc_gp0_regnum + PPC_RA (insn));
4281  return 0;
4282 
4283  /* Store memory. */
4284  case 181: /* Store Doubleword with Update Indexed */
4285  case 183: /* Store Word with Update Indexed */
4286  case 247: /* Store Byte with Update Indexed */
4287  case 439: /* Store Half Word with Update Indexed */
4288  case 695: /* Store Floating-Point Single with Update Indexed */
4289  case 759: /* Store Floating-Point Double with Update Indexed */
4291  tdep->ppc_gp0_regnum + PPC_RA (insn));
4292  /* FALL-THROUGH */
4293  case 135: /* Store Vector Element Byte Indexed */
4294  case 167: /* Store Vector Element Halfword Indexed */
4295  case 199: /* Store Vector Element Word Indexed */
4296  case 231: /* Store Vector Indexed */
4297  case 487: /* Store Vector Indexed LRU */
4298  case 716: /* Store VSX Scalar Doubleword Indexed */
4299  case 140: /* Store VSX Scalar as Integer Word Indexed */
4300  case 652: /* Store VSX Scalar Single-Precision Indexed */
4301  case 972: /* Store VSX Vector Doubleword*2 Indexed */
4302  case 908: /* Store VSX Vector Word*4 Indexed */
4303  case 149: /* Store Doubleword Indexed */
4304  case 151: /* Store Word Indexed */
4305  case 215: /* Store Byte Indexed */
4306  case 407: /* Store Half Word Indexed */
4307  case 694: /* Store Byte Conditional Indexed */
4308  case 726: /* Store Halfword Conditional Indexed */
4309  case 150: /* Store Word Conditional Indexed */
4310  case 214: /* Store Doubleword Conditional Indexed */
4311  case 182: /* Store Quadword Conditional Indexed */
4312  case 662: /* Store Word Byte-Reverse Indexed */
4313  case 918: /* Store Halfword Byte-Reverse Indexed */
4314  case 660: /* Store Doubleword Byte-Reverse Indexed */
4315  case 663: /* Store Floating-Point Single Indexed */
4316  case 727: /* Store Floating-Point Double Indexed */
4317  case 919: /* Store Floating-Point Double Pair Indexed */
4318  case 983: /* Store Floating-Point as Integer Word Indexed */
4319  if (ext == 694 || ext == 726 || ext == 150 || ext == 214 || ext == 182)
4320  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4321 
4322  ra = 0;
4323  if (PPC_RA (insn) != 0)
4324  regcache_raw_read_unsigned (regcache,
4325  tdep->ppc_gp0_regnum + PPC_RA (insn), &ra);
4326  regcache_raw_read_unsigned (regcache,
4327  tdep->ppc_gp0_regnum + PPC_RB (insn), &rb);
4328  ea = ra + rb;
4329 
4330  switch (ext)
4331  {
4332  case 183: /* Store Word with Update Indexed */
4333  case 199: /* Store Vector Element Word Indexed */
4334  case 140: /* Store VSX Scalar as Integer Word Indexed */
4335  case 652: /* Store VSX Scalar Single-Precision Indexed */
4336  case 151: /* Store Word Indexed */
4337  case 150: /* Store Word Conditional Indexed */
4338  case 662: /* Store Word Byte-Reverse Indexed */
4339  case 663: /* Store Floating-Point Single Indexed */
4340  case 695: /* Store Floating-Point Single with Update Indexed */
4341  case 983: /* Store Floating-Point as Integer Word Indexed */
4342  size = 4;
4343  break;
4344  case 247: /* Store Byte with Update Indexed */
4345  case 135: /* Store Vector Element Byte Indexed */
4346  case 215: /* Store Byte Indexed */
4347  case 694: /* Store Byte Conditional Indexed */
4348  size = 1;
4349  break;
4350  case 439: /* Store Halfword with Update Indexed */
4351  case 167: /* Store Vector Element Halfword Indexed */
4352  case 407: /* Store Halfword Indexed */
4353  case 726: /* Store Halfword Conditional Indexed */
4354  case 918: /* Store Halfword Byte-Reverse Indexed */
4355  size = 2;
4356  break;
4357  case 181: /* Store Doubleword with Update Indexed */
4358  case 716: /* Store VSX Scalar Doubleword Indexed */
4359  case 149: /* Store Doubleword Indexed */
4360  case 214: /* Store Doubleword Conditional Indexed */
4361  case 660: /* Store Doubleword Byte-Reverse Indexed */
4362  case 727: /* Store Floating-Point Double Indexed */
4363  case 759: /* Store Floating-Point Double with Update Indexed */
4364  size = 8;
4365  break;
4366  case 972: /* Store VSX Vector Doubleword*2 Indexed */
4367  case 908: /* Store VSX Vector Word*4 Indexed */
4368  case 182: /* Store Quadword Conditional Indexed */
4369  case 231: /* Store Vector Indexed */
4370  case 487: /* Store Vector Indexed LRU */
4371  case 919: /* Store Floating-Point Double Pair Indexed */
4372  size = 16;
4373  break;
4374  default:
4375  gdb_assert (0);
4376  }
4377 
4378  /* Align address for Store Vector instructions. */
4379  switch (ext)
4380  {
4381  case 167: /* Store Vector Element Halfword Indexed */
4382  addr = addr & ~0x1ULL;
4383  break;
4384 
4385  case 199: /* Store Vector Element Word Indexed */
4386  addr = addr & ~0x3ULL;
4387  break;
4388 
4389  case 231: /* Store Vector Indexed */
4390  case 487: /* Store Vector Indexed LRU */
4391  addr = addr & ~0xfULL;
4392  break;
4393  }
4394 
4395  record_full_arch_list_add_mem (addr, size);
4396  return 0;
4397 
4398  case 725: /* Store String Word Immediate */
4399  ra = 0;
4400  if (PPC_RA (insn) != 0)
4401  regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &ra);
4402  ea += ra;
4403 
4404  nb = PPC_NB (insn);
4405  if (nb == 0)
4406  nb = 32;
4407 
4409 
4410  return 0;
4411 
4412  case 661: /* Store String Word Indexed */
4413  ra = 0;
4414  if (PPC_RA (insn) != 0)
4415  regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &ra);
4416  ea += ra;
4417 
4418  regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &xer);
4419  nb = PPC_XER_NB (xer);
4420 
4421  if (nb != 0)
4422  {
4423  regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &rb);
4424  ea += rb;
4426  }
4427 
4428  return 0;
4429 
4430  case 467: /* Move To Special Purpose Register */
4431  switch (PPC_SPR (insn))
4432  {
4433  case 1: /* XER */
4435  return 0;
4436  case 8: /* LR */
4437  record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum);
4438  return 0;
4439  case 9: /* CTR */
4441  return 0;
4442  case 256: /* VRSAVE */
4444  return 0;
4445  }
4446 
4447  goto UNKNOWN_OP;
4448 
4449  case 147: /* Move To Split Little Endian */
4450  record_full_arch_list_add_reg (regcache, tdep->ppc_ps_regnum);
4451  return 0;
4452 
4453  case 512: /* Move to Condition Register from XER */
4454  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4456  return 0;
4457 
4458  case 4: /* Trap Word */
4459  case 68: /* Trap Doubleword */
4460  case 430: /* Clear BHRB */
4461  case 598: /* Synchronize */
4462  case 62: /* Wait for Interrupt */
4463  case 22: /* Instruction Cache Block Touch */
4464  case 854: /* Enforce In-order Execution of I/O */
4465  case 246: /* Data Cache Block Touch for Store */
4466  case 54: /* Data Cache Block Store */
4467  case 86: /* Data Cache Block Flush */
4468  case 278: /* Data Cache Block Touch */
4469  case 758: /* Data Cache Block Allocate */
4470  case 982: /* Instruction Cache Block Invalidate */
4471  return 0;
4472 
4473  case 654: /* Transaction Begin */
4474  case 686: /* Transaction End */
4475  case 718: /* Transaction Check */
4476  case 750: /* Transaction Suspend or Resume */
4477  case 782: /* Transaction Abort Word Conditional */
4478  case 814: /* Transaction Abort Doubleword Conditional */
4479  case 846: /* Transaction Abort Word Conditional Immediate */
4480  case 878: /* Transaction Abort Doubleword Conditional Immediate */
4481  case 910: /* Transaction Abort */
4482  fprintf_unfiltered (gdb_stdlog, "Cannot record Transaction instructions. "
4483  "%08x at %s, 31-%d.\n",
4484  insn, paddress (gdbarch, addr), ext);
4485  return -1;
4486 
4487  case 1014: /* Data Cache Block set to Zero */
4488  if (target_auxv_search (&current_target, AT_DCACHEBSIZE, &at_dcsz) <= 0
4489  || at_dcsz == 0)
4490  at_dcsz = 128; /* Assume 128-byte cache line size (POWER8) */
4491 
4492  if (PPC_RA (insn) != 0)
4493  regcache_raw_read_unsigned (regcache,
4494  tdep->ppc_gp0_regnum + PPC_RA (insn), &ra);
4495  regcache_raw_read_unsigned (regcache,
4496  tdep->ppc_gp0_regnum + PPC_RB (insn), &rb);
4497  ea = (ra + rb) & ~((ULONGEST) (at_dcsz - 1));
4498  record_full_arch_list_add_mem (ea, at_dcsz);
4499  return 0;
4500  }
4501 
4502 UNKNOWN_OP:
4503  fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
4504  "at %s, 31-%d.\n", insn, paddress (gdbarch, addr), ext);
4505  return -1;
4506 }
4507 
4508 /* Parse and record instructions of primary opcode-59 at ADDR.
4509  Return 0 if successful. */
4510 
4511 static int
4512 ppc_process_record_op59 (struct gdbarch *gdbarch, struct regcache *regcache,
4513  CORE_ADDR addr, uint32_t insn)
4514 {
4515  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4516  int ext = PPC_EXTOP (insn);
4517 
4518  switch (ext & 0x1f)
4519  {
4520  case 18: /* Floating Divide */
4521  case 20: /* Floating Subtract */
4522  case 21: /* Floating Add */
4523  case 22: /* Floating Square Root */
4524  case 24: /* Floating Reciprocal Estimate */
4525  case 25: /* Floating Multiply */
4526  case 26: /* Floating Reciprocal Square Root Estimate */
4527  case 28: /* Floating Multiply-Subtract */
4528  case 29: /* Floating Multiply-Add */
4529  case 30: /* Floating Negative Multiply-Subtract */
4530  case 31: /* Floating Negative Multiply-Add */
4532  tdep->ppc_fp0_regnum + PPC_FRT (insn));
4533  if (PPC_RC (insn))
4534  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4536 
4537  return 0;
4538  }
4539 
4540  switch (ext)
4541  {
4542  case 2: /* DFP Add */
4543  case 3: /* DFP Quantize */
4544  case 34: /* DFP Multiply */
4545  case 35: /* DFP Reround */
4546  case 67: /* DFP Quantize Immediate */
4547  case 99: /* DFP Round To FP Integer With Inexact */
4548  case 227: /* DFP Round To FP Integer Without Inexact */
4549  case 258: /* DFP Convert To DFP Long! */
4550  case 290: /* DFP Convert To Fixed */
4551  case 514: /* DFP Subtract */
4552  case 546: /* DFP Divide */
4553  case 770: /* DFP Round To DFP Short! */
4554  case 802: /* DFP Convert From Fixed */
4555  case 834: /* DFP Encode BCD To DPD */
4556  if (PPC_RC (insn))
4557  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4559  tdep->ppc_fp0_regnum + PPC_FRT (insn));
4561  return 0;
4562 
4563  case 130: /* DFP Compare Ordered */
4564  case 162: /* DFP Test Exponent */
4565  case 194: /* DFP Test Data Class */
4566  case 226: /* DFP Test Data Group */
4567  case 642: /* DFP Compare Unordered */
4568  case 674: /* DFP Test Significance */
4569  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4571  return 0;
4572 
4573  case 66: /* DFP Shift Significand Left Immediate */
4574  case 98: /* DFP Shift Significand Right Immediate */
4575  case 322: /* DFP Decode DPD To BCD */
4576  case 354: /* DFP Extract Biased Exponent */
4577  case 866: /* DFP Insert Biased Exponent */
4579  tdep->ppc_fp0_regnum + PPC_FRT (insn));
4580  if (PPC_RC (insn))
4581  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4582  return 0;
4583 
4584  case 846: /* Floating Convert From Integer Doubleword Single */
4585  case 974: /* Floating Convert From Integer Doubleword Unsigned
4586  Single */
4588  tdep->ppc_fp0_regnum + PPC_FRT (insn));
4589  if (PPC_RC (insn))
4590  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4592 
4593  return 0;
4594  }
4595 
4596  fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
4597  "at %s, 59-%d.\n", insn, paddress (gdbarch, addr), ext);
4598  return -1;
4599 }
4600 
4601 /* Parse and record instructions of primary opcode-60 at ADDR.
4602  Return 0 if successful. */
4603 
4604 static int
4605 ppc_process_record_op60 (struct gdbarch *gdbarch, struct regcache *regcache,
4606  CORE_ADDR addr, uint32_t insn)
4607 {
4608  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4609  int ext = PPC_EXTOP (insn);
4610 
4611  switch (ext >> 2)
4612  {
4613  case 0: /* VSX Scalar Add Single-Precision */
4614  case 32: /* VSX Scalar Add Double-Precision */
4615  case 24: /* VSX Scalar Divide Single-Precision */
4616  case 56: /* VSX Scalar Divide Double-Precision */
4617  case 176: /* VSX Scalar Copy Sign Double-Precision */
4618  case 33: /* VSX Scalar Multiply-Add Double-Precision */
4619  case 41: /* ditto */
4620  case 1: /* VSX Scalar Multiply-Add Single-Precision */
4621  case 9: /* ditto */
4622  case 160: /* VSX Scalar Maximum Double-Precision */
4623  case 168: /* VSX Scalar Minimum Double-Precision */
4624  case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
4625  case 57: /* ditto */
4626  case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
4627  case 25: /* ditto */
4628  case 48: /* VSX Scalar Multiply Double-Precision */
4629  case 16: /* VSX Scalar Multiply Single-Precision */
4630  case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
4631  case 169: /* ditto */
4632  case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
4633  case 137: /* ditto */
4634  case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
4635  case 185: /* ditto */
4636  case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
4637  case 153: /* ditto */
4638  case 40: /* VSX Scalar Subtract Double-Precision */
4639  case 8: /* VSX Scalar Subtract Single-Precision */
4640  case 96: /* VSX Vector Add Double-Precision */
4641  case 64: /* VSX Vector Add Single-Precision */
4642  case 120: /* VSX Vector Divide Double-Precision */
4643  case 88: /* VSX Vector Divide Single-Precision */
4644  case 97: /* VSX Vector Multiply-Add Double-Precision */
4645  case 105: /* ditto */
4646  case 65: /* VSX Vector Multiply-Add Single-Precision */
4647  case 73: /* ditto */
4648  case 224: /* VSX Vector Maximum Double-Precision */
4649  case 192: /* VSX Vector Maximum Single-Precision */
4650  case 232: /* VSX Vector Minimum Double-Precision */
4651  case 200: /* VSX Vector Minimum Single-Precision */
4652  case 113: /* VSX Vector Multiply-Subtract Double-Precision */
4653  case 121: /* ditto */
4654  case 81: /* VSX Vector Multiply-Subtract Single-Precision */
4655  case 89: /* ditto */
4656  case 112: /* VSX Vector Multiply Double-Precision */
4657  case 80: /* VSX Vector Multiply Single-Precision */
4658  case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
4659  case 233: /* ditto */
4660  case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
4661  case 201: /* ditto */
4662  case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
4663  case 249: /* ditto */
4664  case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
4665  case 217: /* ditto */
4666  case 104: /* VSX Vector Subtract Double-Precision */
4667  case 72: /* VSX Vector Subtract Single-Precision */
4669  case 240: /* VSX Vector Copy Sign Double-Precision */
4670  case 208: /* VSX Vector Copy Sign Single-Precision */
4671  case 130: /* VSX Logical AND */
4672  case 138: /* VSX Logical AND with Complement */
4673  case 186: /* VSX Logical Equivalence */
4674  case 178: /* VSX Logical NAND */
4675  case 170: /* VSX Logical OR with Complement */
4676  case 162: /* VSX Logical NOR */
4677  case 146: /* VSX Logical OR */
4678  case 154: /* VSX Logical XOR */
4679  case 18: /* VSX Merge High Word */
4680  case 50: /* VSX Merge Low Word */
4681  case 10: /* VSX Permute Doubleword Immediate (DM=0) */
4682  case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
4683  case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
4684  case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
4685  case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
4686  case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
4687  case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
4688  case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
4689  ppc_record_vsr (regcache, tdep, PPC_XT (insn));
4690  return 0;
4691 
4692  case 61: /* VSX Scalar Test for software Divide Double-Precision */
4693  case 125: /* VSX Vector Test for software Divide Double-Precision */
4694  case 93: /* VSX Vector Test for software Divide Single-Precision */
4695  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4696  return 0;
4697 
4698  case 35: /* VSX Scalar Compare Unordered Double-Precision */
4699  case 43: /* VSX Scalar Compare Ordered Double-Precision */
4700  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4702  return 0;
4703  }
4704 
4705  switch ((ext >> 2) & 0x7f) /* Mask out Rc-bit. */
4706  {
4707  case 99: /* VSX Vector Compare Equal To Double-Precision */
4708  case 67: /* VSX Vector Compare Equal To Single-Precision */
4709  case 115: /* VSX Vector Compare Greater Than or
4710  Equal To Double-Precision */
4711  case 83: /* VSX Vector Compare Greater Than or
4712  Equal To Single-Precision */
4713  case 107: /* VSX Vector Compare Greater Than Double-Precision */
4714  case 75: /* VSX Vector Compare Greater Than Single-Precision */
4715  if (PPC_Rc (insn))
4716  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4718  ppc_record_vsr (regcache, tdep, PPC_XT (insn));
4719  return 0;
4720  }
4721 
4722  switch (ext >> 1)
4723  {
4724  case 265: /* VSX Scalar round Double-Precision to
4725  Single-Precision and Convert to
4726  Single-Precision format */
4727  case 344: /* VSX Scalar truncate Double-Precision to
4728  Integer and Convert to Signed Integer
4729  Doubleword format with Saturate */
4730  case 88: /* VSX Scalar truncate Double-Precision to
4731  Integer and Convert to Signed Integer Word
4732  Format with Saturate */
4733  case 328: /* VSX Scalar truncate Double-Precision integer
4734  and Convert to Unsigned Integer Doubleword
4735  Format with Saturate */
4736  case 72: /* VSX Scalar truncate Double-Precision to
4737  Integer and Convert to Unsigned Integer Word
4738  Format with Saturate */
4739  case 329: /* VSX Scalar Convert Single-Precision to
4740  Double-Precision format */
4741  case 376: /* VSX Scalar Convert Signed Integer
4742  Doubleword to floating-point format and
4743  Round to Double-Precision format */
4744  case 312: /* VSX Scalar Convert Signed Integer
4745  Doubleword to floating-point format and
4746  round to Single-Precision */
4747  case 360: /* VSX Scalar Convert Unsigned Integer
4748  Doubleword to floating-point format and
4749  Round to Double-Precision format */
4750  case 296: /* VSX Scalar Convert Unsigned Integer
4751  Doubleword to floating-point format and
4752  Round to Single-Precision */
4753  case 73: /* VSX Scalar Round to Double-Precision Integer
4754  Using Round to Nearest Away */
4755  case 107: /* VSX Scalar Round to Double-Precision Integer
4756  Exact using Current rounding mode */
4757  case 121: /* VSX Scalar Round to Double-Precision Integer
4758  Using Round toward -Infinity */
4759  case 105: /* VSX Scalar Round to Double-Precision Integer
4760  Using Round toward +Infinity */
4761  case 89: /* VSX Scalar Round to Double-Precision Integer
4762  Using Round toward Zero */
4763  case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
4764  case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
4765  case 281: /* VSX Scalar Round to Single-Precision */
4766  case 74: /* VSX Scalar Reciprocal Square Root Estimate
4767  Double-Precision */
4768  case 10: /* VSX Scalar Reciprocal Square Root Estimate
4769  Single-Precision */
4770  case 75: /* VSX Scalar Square Root Double-Precision */
4771  case 11: /* VSX Scalar Square Root Single-Precision */
4772  case 393: /* VSX Vector round Double-Precision to
4773  Single-Precision and Convert to
4774  Single-Precision format */
4775  case 472: /* VSX Vector truncate Double-Precision to
4776  Integer and Convert to Signed Integer
4777  Doubleword format with Saturate */
4778  case 216: /* VSX Vector truncate Double-Precision to
4779  Integer and Convert to Signed Integer Word
4780  Format with Saturate */
4781  case 456: /* VSX Vector truncate Double-Precision to
4782  Integer and Convert to Unsigned Integer
4783  Doubleword format with Saturate */
4784  case 200: /* VSX Vector truncate Double-Precision to
4785  Integer and Convert to Unsigned Integer Word
4786  Format with Saturate */
4787  case 457: /* VSX Vector Convert Single-Precision to
4788  Double-Precision format */
4789  case 408: /* VSX Vector truncate Single-Precision to
4790  Integer and Convert to Signed Integer
4791  Doubleword format with Saturate */
4792  case 152: /* VSX Vector truncate Single-Precision to
4793  Integer and Convert to Signed Integer Word
4794  Format with Saturate */
4795  case 392: /* VSX Vector truncate Single-Precision to
4796  Integer and Convert to Unsigned Integer
4797  Doubleword format with Saturate */
4798  case 136: /* VSX Vector truncate Single-Precision to
4799  Integer and Convert to Unsigned Integer Word
4800  Format with Saturate */
4801  case 504: /* VSX Vector Convert and round Signed Integer
4802  Doubleword to Double-Precision format */
4803  case 440: /* VSX Vector Convert and round Signed Integer
4804  Doubleword to Single-Precision format */
4805  case 248: /* VSX Vector Convert Signed Integer Word to
4806  Double-Precision format */
4807  case 184: /* VSX Vector Convert and round Signed Integer
4808  Word to Single-Precision format */
4809  case 488: /* VSX Vector Convert and round Unsigned
4810  Integer Doubleword to Double-Precision format */
4811  case 424: /* VSX Vector Convert and round Unsigned
4812  Integer Doubleword to Single-Precision format */
4813  case 232: /* VSX Vector Convert and round Unsigned
4814  Integer Word to Double-Precision format */
4815  case 168: /* VSX Vector Convert and round Unsigned
4816  Integer Word to Single-Precision format */
4817  case 201: /* VSX Vector Round to Double-Precision
4818  Integer using round to Nearest Away */
4819  case 235: /* VSX Vector Round to Double-Precision
4820  Integer Exact using Current rounding mode */
4821  case 249: /* VSX Vector Round to Double-Precision
4822  Integer using round toward -Infinity */
4823  case 233: /* VSX Vector Round to Double-Precision
4824  Integer using round toward +Infinity */
4825  case 217: /* VSX Vector Round to Double-Precision
4826  Integer using round toward Zero */
4827  case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
4828  case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
4829  case 137: /* VSX Vector Round to Single-Precision Integer
4830  Using Round to Nearest Away */
4831  case 171: /* VSX Vector Round to Single-Precision Integer
4832  Exact Using Current rounding mode */
4833  case 185: /* VSX Vector Round to Single-Precision Integer
4834  Using Round toward -Infinity */
4835  case 169: /* VSX Vector Round to Single-Precision Integer
4836  Using Round toward +Infinity */
4837  case 153: /* VSX Vector Round to Single-Precision Integer
4838  Using round toward Zero */
4839  case 202: /* VSX Vector Reciprocal Square Root Estimate
4840  Double-Precision */
4841  case 138: /* VSX Vector Reciprocal Square Root Estimate
4842  Single-Precision */
4843  case 203: /* VSX Vector Square Root Double-Precision */
4844  case 139: /* VSX Vector Square Root Single-Precision */
4846  case 345: /* VSX Scalar Absolute Value Double-Precision */
4847  case 267: /* VSX Scalar Convert Scalar Single-Precision to
4848  Vector Single-Precision format Non-signalling */
4849  case 331: /* VSX Scalar Convert Single-Precision to
4850  Double-Precision format Non-signalling */
4851  case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
4852  case 377: /* VSX Scalar Negate Double-Precision */
4853  case 473: /* VSX Vector Absolute Value Double-Precision */
4854  case 409: /* VSX Vector Absolute Value Single-Precision */
4855  case 489: /* VSX Vector Negative Absolute Value Double-Precision */
4856  case 425: /* VSX Vector Negative Absolute Value Single-Precision */
4857  case 505: /* VSX Vector Negate Double-Precision */
4858  case 441: /* VSX Vector Negate Single-Precision */
4859  case 164: /* VSX Splat Word */
4860  ppc_record_vsr (regcache, tdep, PPC_XT (insn));
4861  return 0;
4862 
4863  case 106: /* VSX Scalar Test for software Square Root
4864  Double-Precision */
4865  case 234: /* VSX Vector Test for software Square Root
4866  Double-Precision */
4867  case 170: /* VSX Vector Test for software Square Root
4868  Single-Precision */
4869  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4870  return 0;
4871  }
4872 
4873  if (((ext >> 3) & 0x3) == 3) /* VSX Select */
4874  {
4875  ppc_record_vsr (regcache, tdep, PPC_XT (insn));
4876  return 0;
4877  }
4878 
4879  fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
4880  "at %s, 60-%d.\n", insn, paddress (gdbarch, addr), ext);
4881  return -1;
4882 }
4883 
4884 /* Parse and record instructions of primary opcode-63 at ADDR.
4885  Return 0 if successful. */
4886 
4887 static int
4888 ppc_process_record_op63 (struct gdbarch *gdbarch, struct regcache *regcache,
4889  CORE_ADDR addr, uint32_t insn)
4890 {
4891  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4892  int ext = PPC_EXTOP (insn);
4893  int tmp;
4894 
4895  switch (ext & 0x1f)
4896  {
4897  case 18: /* Floating Divide */
4898  case 20: /* Floating Subtract */
4899  case 21: /* Floating Add */
4900  case 22: /* Floating Square Root */
4901  case 24: /* Floating Reciprocal Estimate */
4902  case 25: /* Floating Multiply */
4903  case 26: /* Floating Reciprocal Square Root Estimate */
4904  case 28: /* Floating Multiply-Subtract */
4905  case 29: /* Floating Multiply-Add */
4906  case 30: /* Floating Negative Multiply-Subtract */
4907  case 31: /* Floating Negative Multiply-Add */
4909  tdep->ppc_fp0_regnum + PPC_FRT (insn));
4910  if (PPC_RC (insn))
4911  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4913  return 0;
4914 
4915  case 23: /* Floating Select */
4917  tdep->ppc_fp0_regnum + PPC_FRT (insn));
4918  if (PPC_RC (insn))
4919  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4920  }
4921 
4922  switch (ext)
4923  {
4924  case 2: /* DFP Add Quad */
4925  case 3: /* DFP Quantize Quad */
4926  case 34: /* DFP Multiply Quad */
4927  case 35: /* DFP Reround Quad */
4928  case 67: /* DFP Quantize Immediate Quad */
4929  case 99: /* DFP Round To FP Integer With Inexact Quad */
4930  case 227: /* DFP Round To FP Integer Without Inexact Quad */
4931  case 258: /* DFP Convert To DFP Extended Quad */
4932  case 514: /* DFP Subtract Quad */
4933  case 546: /* DFP Divide Quad */
4934  case 770: /* DFP Round To DFP Long Quad */
4935  case 802: /* DFP Convert From Fixed Quad */
4936  case 834: /* DFP Encode BCD To DPD Quad */
4937  if (PPC_RC (insn))
4938  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4939  tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1);
4940  record_full_arch_list_add_reg (regcache, tmp);
4941  record_full_arch_list_add_reg (regcache, tmp + 1);
4943  return 0;
4944 
4945  case 130: /* DFP Compare Ordered Quad */
4946  case 162: /* DFP Test Exponent Quad */
4947  case 194: /* DFP Test Data Class Quad */
4948  case 226: /* DFP Test Data Group Quad */
4949  case 642: /* DFP Compare Unordered Quad */
4950  case 674: /* DFP Test Significance Quad */
4951  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4953  return 0;
4954 
4955  case 66: /* DFP Shift Significand Left Immediate Quad */
4956  case 98: /* DFP Shift Significand Right Immediate Quad */
4957  case 322: /* DFP Decode DPD To BCD Quad */
4958  case 866: /* DFP Insert Biased Exponent Quad */
4959  tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1);
4960  record_full_arch_list_add_reg (regcache, tmp);
4961  record_full_arch_list_add_reg (regcache, tmp + 1);
4962  if (PPC_RC (insn))
4963  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4964  return 0;
4965 
4966  case 290: /* DFP Convert To Fixed Quad */
4968  tdep->ppc_fp0_regnum + PPC_FRT (insn));
4969  if (PPC_RC (insn))
4970  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4972  break;
4973 
4974  case 354: /* DFP Extract Biased Exponent Quad */
4976  tdep->ppc_fp0_regnum + PPC_FRT (insn));
4977  if (PPC_RC (insn))
4978  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4979  return 0;
4980 
4981  case 12: /* Floating Round to Single-Precision */
4982  case 14: /* Floating Convert To Integer Word */
4983  case 15: /* Floating Convert To Integer Word
4984  with round toward Zero */
4985  case 142: /* Floating Convert To Integer Word Unsigned */
4986  case 143: /* Floating Convert To Integer Word Unsigned
4987  with round toward Zero */
4988  case 392: /* Floating Round to Integer Nearest */
4989  case 424: /* Floating Round to Integer Toward Zero */
4990  case 456: /* Floating Round to Integer Plus */
4991  case 488: /* Floating Round to Integer Minus */
4992  case 814: /* Floating Convert To Integer Doubleword */
4993  case 815: /* Floating Convert To Integer Doubleword
4994  with round toward Zero */
4995  case 846: /* Floating Convert From Integer Doubleword */
4996  case 942: /* Floating Convert To Integer Doubleword Unsigned */
4997  case 943: /* Floating Convert To Integer Doubleword Unsigned
4998  with round toward Zero */
4999  case 974: /* Floating Convert From Integer Doubleword Unsigned */
5001  tdep->ppc_fp0_regnum + PPC_FRT (insn));
5002  if (PPC_RC (insn))
5003  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5005  return 0;
5006 
5007  case 583: /* Move From FPSCR */
5008  case 8: /* Floating Copy Sign */
5009  case 40: /* Floating Negate */
5010  case 72: /* Floating Move Register */
5011  case 136: /* Floating Negative Absolute Value */
5012  case 264: /* Floating Absolute Value */
5014  tdep->ppc_fp0_regnum + PPC_FRT (insn));
5015  if (PPC_RC (insn))
5016  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5017  return 0;
5018 
5019  case 838: /* Floating Merge Odd Word */
5020  case 966: /* Floating Merge Even Word */
5022  tdep->ppc_fp0_regnum + PPC_FRT (insn));
5023  return 0;
5024 
5025  case 38: /* Move To FPSCR Bit 1 */
5026  case 70: /* Move To FPSCR Bit 0 */
5027  case 134: /* Move To FPSCR Field Immediate */
5028  case 711: /* Move To FPSCR Fields */
5029  if (PPC_RC (insn))
5030  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5032  break;
5033 
5034  case 0: /* Floating Compare Unordered */
5035  case 32: /* Floating Compare Ordered */
5036  case 64: /* Move to Condition Register from FPSCR */
5038  /* FALL-THROUGH */
5039  case 128: /* Floating Test for software Divide */
5040  case 160: /* Floating Test for software Square Root */
5041  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5042  return 0;
5043 
5044  }
5045 
5046  fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
5047  "at %s, 59-%d.\n", insn, paddress (gdbarch, addr), ext);
5048  return -1;
5049 }
5050 
5051 /* Parse the current instruction and record the values of the registers and
5052  memory that will be changed in current instruction to "record_arch_list".
5053  Return -1 if something wrong. */
5054 
5055 int
5056 ppc_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
5057  CORE_ADDR addr)
5058 {
5059  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5060  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5061  uint32_t insn;
5062  int op6, tmp, i;
5063 
5064  insn = read_memory_unsigned_integer (addr, 4, byte_order);
5065  op6 = PPC_OP6 (insn);
5066 
5067  switch (op6)
5068  {
5069  case 2: /* Trap Doubleword Immediate */
5070  case 3: /* Trap Word Immediate */
5071  /* Do nothing. */
5072  break;
5073 
5074  case 4:
5075  if (ppc_process_record_op4 (gdbarch, regcache, addr, insn) != 0)
5076  return -1;
5077  break;
5078 
5079  case 17: /* System call */
5080  if (PPC_LEV (insn) != 0)
5081  goto UNKNOWN_OP;
5082 
5083  if (tdep->ppc_syscall_record != NULL)
5084  {
5085  if (tdep->ppc_syscall_record (regcache) != 0)
5086  return -1;
5087  }
5088  else
5089  {
5090  printf_unfiltered (_("no syscall record support\n"));
5091  return -1;
5092  }
5093  break;
5094 
5095  case 7: /* Multiply Low Immediate */
5097  tdep->ppc_gp0_regnum + PPC_RT (insn));
5098  break;
5099 
5100  case 8: /* Subtract From Immediate Carrying */
5103  tdep->ppc_gp0_regnum + PPC_RT (insn));
5104  break;
5105 
5106  case 10: /* Compare Logical Immediate */
5107  case 11: /* Compare Immediate */
5108  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5109  break;
5110 
5111  case 13: /* Add Immediate Carrying and Record */
5112  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5113  /* FALL-THROUGH */
5114  case 12: /* Add Immediate Carrying */
5116  /* FALL-THROUGH */
5117  case 14: /* Add Immediate */
5118  case 15: /* Add Immediate Shifted */
5120  tdep->ppc_gp0_regnum + PPC_RT (insn));
5121  break;
5122 
5123  case 16: /* Branch Conditional */
5124  if ((PPC_BO (insn) & 0x4) == 0)
5126  /* FALL-THROUGH */
5127  case 18: /* Branch */
5128  if (PPC_LK (insn))
5129  record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum);
5130  break;
5131 
5132  case 19:
5133  if (ppc_process_record_op19 (gdbarch, regcache, addr, insn) != 0)
5134  return -1;
5135  break;
5136 
5137  case 20: /* Rotate Left Word Immediate then Mask Insert */
5138  case 21: /* Rotate Left Word Immediate then AND with Mask */
5139  case 23: /* Rotate Left Word then AND with Mask */
5140  case 30: /* Rotate Left Doubleword Immediate then Clear Left */
5141  /* Rotate Left Doubleword Immediate then Clear Right */
5142  /* Rotate Left Doubleword Immediate then Clear */
5143  /* Rotate Left Doubleword then Clear Left */
5144  /* Rotate Left Doubleword then Clear Right */
5145  /* Rotate Left Doubleword Immediate then Mask Insert */
5146  if (PPC_RC (insn))
5147  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5149  tdep->ppc_gp0_regnum + PPC_RA (insn));
5150  break;
5151 
5152  case 28: /* AND Immediate */
5153  case 29: /* AND Immediate Shifted */
5154  record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5155  /* FALL-THROUGH */
5156  case 24: /* OR Immediate */
5157  case 25: /* OR Immediate Shifted */
5158  case 26: /* XOR Immediate */
5159  case 27: /* XOR Immediate Shifted */
5161  tdep->ppc_gp0_regnum + PPC_RA (insn));
5162  break;
5163 
5164  case 31:
5165  if (ppc_process_record_op31 (gdbarch, regcache, addr, insn) != 0)
5166  return -1;
5167  break;
5168 
5169  case 33: /* Load Word and Zero with Update */
5170  case 35: /* Load Byte and Zero with Update */
5171  case 41: /* Load Halfword and Zero with Update */
5172  case 43: /* Load Halfword Algebraic with Update */
5174  tdep->ppc_gp0_regnum + PPC_RA (insn));
5175  /* FALL-THROUGH */
5176  case 32: /* Load Word and Zero */
5177  case 34: /* Load Byte and Zero */
5178  case 40: /* Load Halfword and Zero */
5179  case 42: /* Load Halfword Algebraic */
5181  tdep->ppc_gp0_regnum + PPC_RT (insn));
5182  break;
5183 
5184  case 46: /* Load Multiple Word */
5185  for (i = PPC_RT (insn); i < 32; i++)
5186  record_full_arch_list_add_reg (regcache, tdep->ppc_gp0_regnum + i);
5187  break;
5188 
5189  case 56: /* Load Quadword */
5190  tmp = tdep->ppc_gp0_regnum + (PPC_RT (insn) & ~1);
5191  record_full_arch_list_add_reg (regcache, tmp);
5192  record_full_arch_list_add_reg (regcache, tmp + 1);
5193  break;
5194 
5195  case 49: /* Load Floating-Point Single with Update */
5196  case 51: /* Load Floating-Point Double with Update */
5198  tdep->ppc_gp0_regnum + PPC_RA (insn));
5199  /* FALL-THROUGH */
5200  case 48: /* Load Floating-Point Single */
5201  case 50: /* Load Floating-Point Double */
5203  tdep->ppc_fp0_regnum + PPC_FRT (insn));
5204  break;
5205 
5206  case 47: /* Store Multiple Word */
5207  {
5208  ULONGEST addr = 0;
5209 
5210  if (PPC_RA (insn) != 0)
5211  regcache_raw_read_unsigned (regcache,
5212  tdep->ppc_gp0_regnum + PPC_RA (insn),
5213  &addr);
5214 
5215  addr += PPC_D (insn);
5216  record_full_arch_list_add_mem (addr, 4 * (32 - PPC_RS (insn)));
5217  }
5218  break;
5219 
5220  case 37: /* Store Word with Update */
5221  case 39: /* Store Byte with Update */
5222  case 45: /* Store Halfword with Update */
5223  case 53: /* Store Floating-Point Single with Update */
5224  case 55: /* Store Floating-Point Double with Update */
5226  tdep->ppc_gp0_regnum + PPC_RA (insn));
5227  /* FALL-THROUGH */
5228  case 36: /* Store Word */
5229  case 38: /* Store Byte */
5230  case 44: /* Store Halfword */
5231  case 52: /* Store Floating-Point Single */
5232  case 54: /* Store Floating-Point Double */
5233  {
5234  ULONGEST addr = 0;
5235  int size = -1;
5236 
5237  if (PPC_RA (insn) != 0)
5238  regcache_raw_read_unsigned (regcache,
5239  tdep->ppc_gp0_regnum + PPC_RA (insn),
5240  &addr);
5241  addr += PPC_D (insn);
5242 
5243  if (op6 == 36 || op6 == 37 || op6 == 52 || op6 == 53)
5244  size = 4;
5245  else if (op6 == 54 || op6 == 55)
5246  size = 8;
5247  else if (op6 == 44 || op6 == 45)
5248  size = 2;
5249  else if (op6 == 38 || op6 == 39)
5250  size = 1;
5251  else
5252  gdb_assert (0);
5253 
5254  record_full_arch_list_add_mem (addr, size);
5255  }
5256  break;
5257 
5258  case 57: /* Load Floating-Point Double Pair */
5259  if (PPC_FIELD (insn, 30, 2) != 0)
5260  goto UNKNOWN_OP;
5261  tmp = tdep->ppc_fp0_regnum + (PPC_RT (insn) & ~1);
5262  record_full_arch_list_add_reg (regcache, tmp);
5263  record_full_arch_list_add_reg (regcache, tmp + 1);
5264  break;
5265 
5266  case 58: /* Load Doubleword */
5267  /* Load Doubleword with Update */
5268  /* Load Word Algebraic */
5269  if (PPC_FIELD (insn, 30, 2) > 2)
5270  goto UNKNOWN_OP;
5271 
5273  tdep->ppc_gp0_regnum + PPC_RT (insn));
5274  if (PPC_BIT (insn, 31))
5276  tdep->ppc_gp0_regnum + PPC_RA (insn));
5277  break;
5278 
5279  case 59:
5280  if (ppc_process_record_op59 (gdbarch, regcache, addr, insn) != 0)
5281  return -1;
5282  break;
5283 
5284  case 60:
5285  if (ppc_process_record_op60 (gdbarch, regcache, addr, insn) != 0)
5286  return -1;
5287  break;
5288 
5289  case 61: /* Store Floating-Point Double Pair */
5290  case 62: /* Store Doubleword */
5291  /* Store Doubleword with Update */
5292  /* Store Quadword with Update */
5293  {
5294  ULONGEST addr = 0;
5295  int size;
5296  int sub2 = PPC_FIELD (insn, 30, 2);
5297 
5298  if ((op6 == 61 && sub2 != 0) || (op6 == 62 && sub2 > 2))
5299  goto UNKNOWN_OP;
5300 
5301  if (PPC_RA (insn) != 0)
5302  regcache_raw_read_unsigned (regcache,
5303  tdep->ppc_gp0_regnum + PPC_RA (insn),
5304  &addr);
5305 
5306  size = ((op6 == 61) || sub2 == 2) ? 16 : 8;
5307 
5308  addr += PPC_DS (insn) << 2;
5309  record_full_arch_list_add_mem (addr, size);
5310 
5311  if (op6 == 62 && sub2 == 1)
5313  tdep->ppc_gp0_regnum +
5314  PPC_RA (insn));
5315 
5316  break;
5317  }
5318 
5319  case 63:
5320  if (ppc_process_record_op63 (gdbarch, regcache, addr, insn) != 0)
5321  return -1;
5322  break;
5323 
5324  default:
5325 UNKNOWN_OP:
5326  fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
5327  "at %s, %d.\n", insn, paddress (gdbarch, addr), op6);
5328  return -1;
5329  }
5330 
5332  return -1;
5334  return -1;
5335  return 0;
5336 }
5337 
5338 /* Initialize the current architecture based on INFO. If possible, re-use an
5339  architecture from ARCHES, which is a list of architectures already created
5340  during this debugging session.
5341 
5342  Called e.g. at program startup, when reading a core file, and when reading
5343  a binary file. */
5344 
5345 static struct gdbarch *
5346 rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
5347 {
5348  struct gdbarch *gdbarch;
5349  struct gdbarch_tdep *tdep;
5350  int wordsize, from_xcoff_exec, from_elf_exec;
5351  enum bfd_architecture arch;
5352  unsigned long mach;
5353  bfd abfd;
5354  enum auto_boolean soft_float_flag = powerpc_soft_float_global;
5355  int soft_float;
5358  int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0,
5359  have_vsx = 0;
5360  int tdesc_wordsize = -1;
5361  const struct target_desc *tdesc = info.target_desc;
5362  struct tdesc_arch_data *tdesc_data = NULL;
5363  int num_pseudoregs = 0;
5364  int cur_reg;
5365 
5366  /* INFO may refer to a binary that is not of the PowerPC architecture,
5367  e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
5368  In this case, we must not attempt to infer properties of the (PowerPC
5369  side) of the target system from properties of that executable. Trust
5370  the target description instead. */
5371  if (info.abfd
5372  && bfd_get_arch (info.abfd) != bfd_arch_powerpc
5373  && bfd_get_arch (info.abfd) != bfd_arch_rs6000)
5374  info.abfd = NULL;
5375 
5376  from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
5377  bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
5378 
5379  from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
5380  bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
5381 
5382  /* Check word size. If INFO is from a binary file, infer it from
5383  that, else choose a likely default. */
5384  if (from_xcoff_exec)
5385  {
5386  if (bfd_xcoff_is_xcoff64 (info.abfd))
5387  wordsize = 8;
5388  else
5389  wordsize = 4;
5390  }
5391  else if (from_elf_exec)
5392  {
5393  if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5394  wordsize = 8;
5395  else
5396  wordsize = 4;
5397  }
5398  else if (tdesc_has_registers (tdesc))
5399  wordsize = -1;
5400  else
5401  {
5402  if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
5403  wordsize = (info.bfd_arch_info->bits_per_word
5404  / info.bfd_arch_info->bits_per_byte);
5405  else
5406  wordsize = 4;
5407  }
5408 
5409  /* Get the architecture and machine from the BFD. */
5410  arch = info.bfd_arch_info->arch;
5411  mach = info.bfd_arch_info->mach;
5412 
5413  /* For e500 executables, the apuinfo section is of help here. Such
5414  section contains the identifier and revision number of each
5415  Application-specific Processing Unit that is present on the
5416  chip. The content of the section is determined by the assembler
5417  which looks at each instruction and determines which unit (and
5418  which version of it) can execute it. Grovel through the section
5419  looking for relevant e500 APUs. */
5420 
5421  if (bfd_uses_spe_extensions (info.abfd))
5422  {
5423  arch = info.bfd_arch_info->arch;
5424  mach = bfd_mach_ppc_e500;
5425  bfd_default_set_arch_mach (&abfd, arch, mach);
5426  info.bfd_arch_info = bfd_get_arch_info (&abfd);
5427  }
5428 
5429  /* Find a default target description which describes our register
5430  layout, if we do not already have one. */
5431  if (! tdesc_has_registers (tdesc))
5432  {
5433  const struct variant *v;
5434 
5435  /* Choose variant. */
5436  v = find_variant_by_arch (arch, mach);
5437  if (!v)
5438  return NULL;
5439 
5440  tdesc = *v->tdesc;
5441  }
5442 
5443  gdb_assert (tdesc_has_registers (tdesc));
5444 
5445  /* Check any target description for validity. */
5446  if (tdesc_has_registers (tdesc))
5447  {
5448  static const char *const gprs[] = {
5449  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5450  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5451  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5452  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5453  };
5454  const struct tdesc_feature *feature;
5455  int i, valid_p;
5456  static const char *const msr_names[] = { "msr", "ps" };
5457  static const char *const cr_names[] = { "cr", "cnd" };
5458  static const char *const ctr_names[] = { "ctr", "cnt" };
5459 
5460  feature = tdesc_find_feature (tdesc,
5461  "org.gnu.gdb.power.core");
5462  if (feature == NULL)
5463  return NULL;
5464 
5465  tdesc_data = tdesc_data_alloc ();
5466 
5467  valid_p = 1;
5468  for (i = 0; i < ppc_num_gprs; i++)
5469  valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]);
5470  valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM,
5471  "pc");
5472  valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM,
5473  "lr");
5474  valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM,
5475  "xer");
5476 
5477  /* Allow alternate names for these registers, to accomodate GDB's
5478  historic naming. */
5479  valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
5480  PPC_MSR_REGNUM, msr_names);
5481  valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
5482  PPC_CR_REGNUM, cr_names);
5483  valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
5484  PPC_CTR_REGNUM, ctr_names);
5485 
5486  if (!valid_p)
5487  {
5488  tdesc_data_cleanup (tdesc_data);
5489  return NULL;
5490  }
5491 
5492  have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM,
5493  "mq");
5494 
5495  tdesc_wordsize = tdesc_register_size (feature, "pc") / 8;
5496  if (wordsize == -1)
5497  wordsize = tdesc_wordsize;
5498 
5499  feature = tdesc_find_feature (tdesc,
5500  "org.gnu.gdb.power.fpu");
5501  if (feature != NULL)
5502  {
5503  static const char *const fprs[] = {
5504  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5505  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5506  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5507  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
5508  };
5509  valid_p = 1;
5510  for (i = 0; i < ppc_num_fprs; i++)
5511  valid_p &= tdesc_numbered_register (feature, tdesc_data,
5512  PPC_F0_REGNUM + i, fprs[i]);
5513  valid_p &= tdesc_numbered_register (feature, tdesc_data,
5514  PPC_FPSCR_REGNUM, "fpscr");
5515 
5516  if (!valid_p)
5517  {
5518  tdesc_data_cleanup (tdesc_data);
5519  return NULL;
5520  }
5521  have_fpu = 1;
5522  }
5523  else
5524  have_fpu = 0;
5525 
5526  /* The DFP pseudo-registers will be available when there are floating
5527  point registers. */
5528  have_dfp = have_fpu;
5529 
5530  feature = tdesc_find_feature (tdesc,
5531  "org.gnu.gdb.power.altivec");
5532  if (feature != NULL)
5533  {
5534  static const char *const vector_regs[] = {
5535  "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
5536  "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
5537  "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
5538  "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
5539  };
5540 
5541  valid_p = 1;
5542  for (i = 0; i < ppc_num_gprs; i++)
5543  valid_p &= tdesc_numbered_register (feature, tdesc_data,
5544  PPC_VR0_REGNUM + i,
5545  vector_regs[i]);
5546  valid_p &= tdesc_numbered_register (feature, tdesc_data,
5547  PPC_VSCR_REGNUM, "vscr");
5548  valid_p &= tdesc_numbered_register (feature, tdesc_data,
5549  PPC_VRSAVE_REGNUM, "vrsave");
5550 
5551  if (have_spe || !valid_p)
5552  {
5553  tdesc_data_cleanup (tdesc_data);
5554  return NULL;
5555  }
5556  have_altivec = 1;
5557  }
5558  else
5559  have_altivec = 0;
5560 
5561  /* Check for POWER7 VSX registers support. */
5562  feature = tdesc_find_feature (tdesc,
5563  "org.gnu.gdb.power.vsx");
5564 
5565  if (feature != NULL)
5566  {
5567  static const char *const vsx_regs[] = {
5568  "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
5569  "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
5570  "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
5571  "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
5572  "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
5573  "vs30h", "vs31h"
5574  };
5575 
5576  valid_p = 1;
5577 
5578  for (i = 0; i < ppc_num_vshrs; i++)
5579  valid_p &= tdesc_numbered_register (feature, tdesc_data,
5581  vsx_regs[i]);
5582  if (!valid_p)
5583  {
5584  tdesc_data_cleanup (tdesc_data);
5585  return NULL;
5586  }
5587 
5588  have_vsx = 1;
5589  }
5590  else
5591  have_vsx = 0;
5592 
5593  /* On machines supporting the SPE APU, the general-purpose registers
5594  are 64 bits long. There are SIMD vector instructions to treat them
5595  as pairs of floats, but the rest of the instruction set treats them
5596  as 32-bit registers, and only operates on their lower halves.
5597 
5598  In the GDB regcache, we treat their high and low halves as separate
5599  registers. The low halves we present as the general-purpose
5600  registers, and then we have pseudo-registers that stitch together
5601  the upper and lower halves and present them as pseudo-registers.
5602 
5603  Thus, the target description is expected to supply the upper
5604  halves separately. */
5605 
5606  feature = tdesc_find_feature (tdesc,
5607  "org.gnu.gdb.power.spe");
5608  if (feature != NULL)
5609  {
5610  static const char *const upper_spe[] = {
5611  "ev0h", "ev1h", "ev2h", "ev3h",
5612  "ev4h", "ev5h", "ev6h", "ev7h",
5613  "ev8h", "ev9h", "ev10h", "ev11h",
5614  "ev12h", "ev13h", "ev14h", "ev15h",
5615  "ev16h", "ev17h", "ev18h", "ev19h",
5616  "ev20h", "ev21h", "ev22h", "ev23h",
5617  "ev24h", "ev25h", "ev26h", "ev27h",
5618  "ev28h", "ev29h", "ev30h", "ev31h"
5619  };
5620 
5621  valid_p = 1;
5622  for (i = 0; i < ppc_num_gprs; i++)
5623  valid_p &= tdesc_numbered_register (feature, tdesc_data,
5625  upper_spe[i]);
5626  valid_p &= tdesc_numbered_register (feature, tdesc_data,
5627  PPC_SPE_ACC_REGNUM, "acc");
5628  valid_p &= tdesc_numbered_register (feature, tdesc_data,
5629  PPC_SPE_FSCR_REGNUM, "spefscr");
5630 
5631  if (have_mq || have_fpu || !valid_p)
5632  {
5633  tdesc_data_cleanup (tdesc_data);
5634  return NULL;
5635  }
5636  have_spe = 1;
5637  }
5638  else
5639  have_spe = 0;
5640  }
5641 
5642  /* If we have a 64-bit binary on a 32-bit target, complain. Also
5643  complain for a 32-bit binary on a 64-bit target; we do not yet
5644  support that. For instance, the 32-bit ABI routines expect
5645  32-bit GPRs.
5646 
5647  As long as there isn't an explicit target description, we'll
5648  choose one based on the BFD architecture and get a word size
5649  matching the binary (probably powerpc:common or
5650  powerpc:common64). So there is only trouble if a 64-bit target
5651  supplies a 64-bit description while debugging a 32-bit
5652  binary. */
5653  if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize)
5654  {
5655  tdesc_data_cleanup (tdesc_data);
5656  return NULL;
5657  }
5658 
5659 #ifdef HAVE_ELF
5660  if (from_elf_exec)
5661  {
5662  switch (elf_elfheader (info.abfd)->e_flags & EF_PPC64_ABI)
5663  {
5664  case 1:
5665  elf_abi = POWERPC_ELF_V1;
5666  break;
5667  case 2:
5668  elf_abi = POWERPC_ELF_V2;
5669  break;
5670  default:
5671  break;
5672  }
5673  }
5674 
5675  if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec)
5676  {
5677  switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
5678  Tag_GNU_Power_ABI_FP))
5679  {
5680  case 1:
5681  soft_float_flag = AUTO_BOOLEAN_FALSE;
5682  break;
5683  case 2:
5684  soft_float_flag = AUTO_BOOLEAN_TRUE;
5685  break;
5686  default:
5687  break;
5688  }
5689  }
5690 
5691  if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec)
5692  {
5693  switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
5694  Tag_GNU_Power_ABI_Vector))
5695  {
5696  case 1:
5697  vector_abi = POWERPC_VEC_GENERIC;
5698  break;
5699  case 2:
5700  vector_abi = POWERPC_VEC_ALTIVEC;
5701  break;
5702  case 3:
5703  vector_abi = POWERPC_VEC_SPE;
5704  break;
5705  default:
5706  break;
5707  }
5708  }
5709 #endif
5710 
5711  /* At this point, the only supported ELF-based 64-bit little-endian
5712  operating system is GNU/Linux, and this uses the ELFv2 ABI by
5713  default. All other supported ELF-based operating systems use the
5714  ELFv1 ABI by default. Therefore, if the ABI marker is missing,
5715  e.g. because we run a legacy binary, or have attached to a process
5716  and have not found any associated binary file, set the default
5717  according to this heuristic. */
5718  if (elf_abi == POWERPC_ELF_AUTO)
5719  {
5720  if (wordsize == 8 && info.byte_order == BFD_ENDIAN_LITTLE)
5721  elf_abi = POWERPC_ELF_V2;
5722  else
5723  elf_abi = POWERPC_ELF_V1;
5724  }
5725 
5726  if (soft_float_flag == AUTO_BOOLEAN_TRUE)
5727  soft_float = 1;
5728  else if (soft_float_flag == AUTO_BOOLEAN_FALSE)
5729  soft_float = 0;
5730  else
5731  soft_float = !have_fpu;
5732 
5733  /* If we have a hard float binary or setting but no floating point
5734  registers, downgrade to soft float anyway. We're still somewhat
5735  useful in this scenario. */
5736  if (!soft_float && !have_fpu)
5737  soft_float = 1;
5738 
5739  /* Similarly for vector registers. */
5740  if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec)
5741  vector_abi = POWERPC_VEC_GENERIC;
5742 
5743  if (vector_abi == POWERPC_VEC_SPE && !have_spe)
5744  vector_abi = POWERPC_VEC_GENERIC;
5745 
5746  if (vector_abi == POWERPC_VEC_AUTO)
5747  {
5748  if (have_altivec)
5749  vector_abi = POWERPC_VEC_ALTIVEC;
5750  else if (have_spe)
5751  vector_abi = POWERPC_VEC_SPE;
5752  else
5753  vector_abi = POWERPC_VEC_GENERIC;
5754  }
5755 
5756  /* Do not limit the vector ABI based on available hardware, since we
5757  do not yet know what hardware we'll decide we have. Yuck! FIXME! */
5758 
5759  /* Find a candidate among extant architectures. */
5760  for (arches = gdbarch_list_lookup_by_info (arches, &info);
5761  arches != NULL;
5762  arches = gdbarch_list_lookup_by_info (arches->next, &info))
5763  {
5764  /* Word size in the various PowerPC bfd_arch_info structs isn't
5765  meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
5766  separate word size check. */
5767  tdep = gdbarch_tdep (arches->gdbarch);
5768  if (tdep && tdep->elf_abi != elf_abi)
5769  continue;
5770  if (tdep && tdep->soft_float != soft_float)
5771  continue;
5772  if (tdep && tdep->vector_abi != vector_abi)
5773  continue;
5774  if (tdep && tdep->wordsize == wordsize)
5775  {
5776  if (tdesc_data != NULL)
5777  tdesc_data_cleanup (tdesc_data);
5778  return arches->gdbarch;
5779  }
5780  }
5781 
5782  /* None found, create a new architecture from INFO, whose bfd_arch_info
5783  validity depends on the source:
5784  - executable useless
5785  - rs6000_host_arch() good
5786  - core file good
5787  - "set arch" trust blindly
5788  - GDB startup useless but harmless */
5789 
5790  tdep = XCNEW (struct gdbarch_tdep);
5791  tdep->wordsize = wordsize;
5792  tdep->elf_abi = elf_abi;
5793  tdep->soft_float = soft_float;
5794  tdep->vector_abi = vector_abi;
5795 
5796  gdbarch = gdbarch_alloc (&info, tdep);
5797 
5798  tdep->ppc_gp0_regnum = PPC_R0_REGNUM;
5799  tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2;
5800  tdep->ppc_ps_regnum = PPC_MSR_REGNUM;
5801  tdep->ppc_cr_regnum = PPC_CR_REGNUM;
5802  tdep->ppc_lr_regnum = PPC_LR_REGNUM;
5805  tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1;
5806 
5807  tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1;
5808  tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1;
5809  tdep->ppc_vsr0_upper_regnum = have_vsx ? PPC_VSR0_UPPER_REGNUM : -1;
5810  tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1;
5811  tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1;
5812  tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1;
5813  tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1;
5814  tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1;
5815 
5817  set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
5819  set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum);
5821 
5822  /* The XML specification for PowerPC sensibly calls the MSR "msr".
5823  GDB traditionally called it "ps", though, so let GDB add an
5824  alias. */
5825  set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum);
5826 
5827  if (wordsize == 8)
5829  else
5831 
5832  /* Set lr_frame_offset. */
5833  if (wordsize == 8)
5834  tdep->lr_frame_offset = 16;
5835  else
5836  tdep->lr_frame_offset = 4;
5837 
5838  if (have_spe || have_dfp || have_vsx)
5839  {
5843  }
5844 
5846 
5847  /* Select instruction printer. */
5848  if (arch == bfd_arch_rs6000)
5849  set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
5850  else
5852 
5854 
5855  if (have_spe)
5856  num_pseudoregs += 32;
5857  if (have_dfp)
5858  num_pseudoregs += 16;
5859  if (have_vsx)
5860  /* Include both VSX and Extended FP registers. */
5861  num_pseudoregs += 96;
5862 
5863  set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs);
5864 
5865  set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
5866  set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
5867  set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
5868  set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
5869  set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
5870  set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
5871  set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
5872  set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
5873  set_gdbarch_char_signed (gdbarch, 0);
5874 
5876  if (wordsize == 8)
5877  /* PPC64 SYSV. */
5878  set_gdbarch_frame_red_zone_size (gdbarch, 288);
5879 
5883 
5886 
5887  if (wordsize == 4)
5889  else if (wordsize == 8)
5891 
5895 
5898 
5899  /* The value of symbols of type N_SO and N_FUN maybe null when
5900  it shouldn't be. */
5902 
5903  /* Handles single stepping of atomic sequences. */
5905 
5906  /* Not sure on this. FIXMEmgo */
5907  set_gdbarch_frame_args_skip (gdbarch, 8);
5908 
5909  /* Helpers for function argument information. */
5911 
5912  /* Trampoline. */
5916 
5917  /* Hook in the DWARF CFI frame unwinder. */
5918  dwarf2_append_unwinders (gdbarch);
5920 
5921  /* Frame handling. */
5923 
5924  /* Setup displaced stepping. */
5934 
5936 
5937  /* Hook in ABI-specific overrides, if they have been registered. */
5938  info.target_desc = tdesc;
5939  info.tdep_info = (void *) tdesc_data;
5940  gdbarch_init_osabi (info, gdbarch);
5941 
5942  switch (info.osabi)
5943  {
5944  case GDB_OSABI_LINUX:
5945  case GDB_OSABI_NETBSD_AOUT:
5946  case GDB_OSABI_NETBSD_ELF:
5947  case GDB_OSABI_UNKNOWN:
5949  frame_unwind_append_unwinder (gdbarch, &rs6000_epilogue_frame_unwind);
5950  frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
5953  break;
5954  default:
5955  set_gdbarch_believe_pcc_promotion (gdbarch, 1);
5956 
5958  frame_unwind_append_unwinder (gdbarch, &rs6000_epilogue_frame_unwind);
5959  frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
5962  }
5963 
5967  tdesc_use_registers (gdbarch, tdesc, tdesc_data);
5968 
5969  /* Override the normal target description method to make the SPE upper
5970  halves anonymous. */
5972 
5973  /* Choose register numbers for all supported pseudo-registers. */
5974  tdep->ppc_ev0_regnum = -1;
5975  tdep->ppc_dl0_regnum = -1;
5976  tdep->ppc_vsr0_regnum = -1;
5977  tdep->ppc_efpr0_regnum = -1;
5978 
5979  cur_reg = gdbarch_num_regs (gdbarch);
5980 
5981  if (have_spe)
5982  {
5983  tdep->ppc_ev0_regnum = cur_reg;
5984  cur_reg += 32;
5985  }
5986  if (have_dfp)
5987  {
5988  tdep->ppc_dl0_regnum = cur_reg;
5989  cur_reg += 16;
5990  }
5991  if (have_vsx)
5992  {
5993  tdep->ppc_vsr0_regnum = cur_reg;
5994  cur_reg += 64;
5995  tdep->ppc_efpr0_regnum = cur_reg;
5996  cur_reg += 32;
5997  }
5998 
5999  gdb_assert (gdbarch_num_regs (gdbarch)
6000  + gdbarch_num_pseudo_regs (gdbarch) == cur_reg);
6001 
6002  /* Register the ravenscar_arch_ops. */
6003  if (mach == bfd_mach_ppc_e500)
6004  register_e500_ravenscar_ops (gdbarch);
6005  else
6006  register_ppc_ravenscar_ops (gdbarch);
6007 
6008  return gdbarch;
6009 }
6010 
6011 static void
6012 rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
6013 {
6014  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
6015 
6016  if (tdep == NULL)
6017  return;
6018 
6019  /* FIXME: Dump gdbarch_tdep. */
6020 }
6021 
6022 /* PowerPC-specific commands. */
6023 
6024 static void
6025 set_powerpc_command (char *args, int from_tty)
6026 {
6027  printf_unfiltered (_("\
6028 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
6029  help_list (setpowerpccmdlist, "set powerpc ", all_commands, gdb_stdout);
6030 }
6031 
6032 static void
6033 show_powerpc_command (char *args, int from_tty)
6034 {
6035  cmd_show_list (showpowerpccmdlist, from_tty, "");
6036 }
6037 
6038 static void
6039 powerpc_set_soft_float (char *args, int from_tty,
6040  struct cmd_list_element *c)
6041 {
6042  struct gdbarch_info info;
6043 
6044  /* Update the architecture. */
6045  gdbarch_info_init (&info);
6046  if (!gdbarch_update_p (info))
6047  internal_error (__FILE__, __LINE__, _("could not update architecture"));
6048 }
6049 
6050 static void
6051 powerpc_set_vector_abi (char *args, int from_tty,
6052  struct cmd_list_element *c)
6053 {
6054  struct gdbarch_info info;
6055  int vector_abi;
6056 
6057  for (vector_abi = POWERPC_VEC_AUTO;
6058  vector_abi != POWERPC_VEC_LAST;
6059  vector_abi++)
6060  if (strcmp (powerpc_vector_abi_string,
6061  powerpc_vector_strings[vector_abi]) == 0)
6062  {
6063  powerpc_vector_abi_global = vector_abi;
6064  break;
6065  }
6066 
6067  if (vector_abi == POWERPC_VEC_LAST)
6068  internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."),
6070 
6071  /* Update the architecture. */
6072  gdbarch_info_init (&info);
6073  if (!gdbarch_update_p (info))
6074  internal_error (__FILE__, __LINE__, _("could not update architecture"));
6075 }
6076 
6077 /* Show the current setting of the exact watchpoints flag. */
6078 
6079 static void
6080 show_powerpc_exact_watchpoints (struct ui_file *file, int from_tty,
6081  struct cmd_list_element *c,
6082  const char *value)
6083 {
6084  fprintf_filtered (file, _("Use of exact watchpoints is %s.\n"), value);
6085 }
6086 
6087 /* Read a PPC instruction from memory. */
6088 
6089 static unsigned int
6090 read_insn (struct frame_info *frame, CORE_ADDR pc)
6091 {
6092  struct gdbarch *gdbarch = get_frame_arch (frame);
6093  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6094 
6095  return read_memory_unsigned_integer (pc, 4, byte_order);
6096 }
6097 
6098 /* Return non-zero if the instructions at PC match the series
6099  described in PATTERN, or zero otherwise. PATTERN is an array of
6100  'struct ppc_insn_pattern' objects, terminated by an entry whose
6101  mask is zero.
6102 
6103  When the match is successful, fill INSN[i] with what PATTERN[i]
6104  matched. If PATTERN[i] is optional, and the instruction wasn't
6105  present, set INSN[i] to 0 (which is not a valid PPC instruction).
6106  INSN should have as many elements as PATTERN. Note that, if
6107  PATTERN contains optional instructions which aren't present in
6108  memory, then INSN will have holes, so INSN[i] isn't necessarily the
6109  i'th instruction in memory. */
6110 
6111 int
6113  struct ppc_insn_pattern *pattern,
6114  unsigned int *insns)
6115 {
6116  int i;
6117  unsigned int insn;
6118 
6119  for (i = 0, insn = 0; pattern[i].mask; i++)
6120  {
6121  if (insn == 0)
6122  insn = read_insn (frame, pc);
6123  insns[i] = 0;
6124  if ((insn & pattern[i].mask) == pattern[i].data)
6125  {
6126  insns[i] = insn;
6127  pc += 4;
6128  insn = 0;
6129  }
6130  else if (!pattern[i].optional)
6131  return 0;
6132  }
6133 
6134  return 1;
6135 }
6136 
6137 /* Return the 'd' field of the d-form instruction INSN, properly
6138  sign-extended. */
6139 
6140 CORE_ADDR
6141 ppc_insn_d_field (unsigned int insn)
6142 {
6143  return ((((CORE_ADDR) insn & 0xffff) ^ 0x8000) - 0x8000);
6144 }
6145 
6146 /* Return the 'ds' field of the ds-form instruction INSN, with the two
6147  zero bits concatenated at the right, and properly
6148  sign-extended. */
6149 
6150 CORE_ADDR
6151 ppc_insn_ds_field (unsigned int insn)
6152 {
6153  return ((((CORE_ADDR) insn & 0xfffc) ^ 0x8000) - 0x8000);
6154 }
6155 
6156 /* Initialization code. */
6157 
6158 /* -Wmissing-prototypes */
6160 
6161 void
6163 {
6166 
6167  /* Initialize the standard target descriptions. */
6187 
6188  /* Add root prefix command for all "set powerpc"/"show powerpc"
6189  commands. */
6191  _("Various PowerPC-specific commands."),
6192  &setpowerpccmdlist, "set powerpc ", 0, &setlist);
6193 
6195  _("Various PowerPC-specific commands."),
6196  &showpowerpccmdlist, "show powerpc ", 0, &showlist);
6197 
6198  /* Add a command to allow the user to force the ABI. */
6201  _("Set whether to use a soft-float ABI."),
6202  _("Show whether to use a soft-float ABI."),
6203  NULL,
6204  powerpc_set_soft_float, NULL,
6205  &setpowerpccmdlist, &showpowerpccmdlist);
6206 
6209  _("Set the vector ABI."),
6210  _("Show the vector ABI."),
6211  NULL, powerpc_set_vector_abi, NULL,
6212  &setpowerpccmdlist, &showpowerpccmdlist);
6213 
6214  add_setshow_boolean_cmd ("exact-watchpoints", class_support,
6216  _("\
6217 Set whether to use just one debug register for watchpoints on scalars."),
6218  _("\
6219 Show whether to use just one debug register for watchpoints on scalars."),
6220  _("\
6221 If true, GDB will use only one debug register when watching a variable of\n\
6222 scalar type, thus assuming that the variable is accessed through the address\n\
6223 of its first byte."),
6225  &setpowerpccmdlist, &showpowerpccmdlist);
6226 }
static void initialize_tdesc_powerpc_602(void)
Definition: powerpc-602.c:10
void set_gdbarch_num_regs(struct gdbarch *gdbarch, int num_regs)
Definition: gdbarch.c:1909
#define PPC_DS(insn)
Definition: rs6000-tdep.c:3677
struct target_desc * tdesc_powerpc_603
Definition: powerpc-603.c:8
void set_gdbarch_double_bit(struct gdbarch *gdbarch, int double_bit)
Definition: gdbarch.c:1634
void set_gdbarch_frame_align(struct gdbarch *gdbarch, gdbarch_frame_align_ftype frame_align)
Definition: gdbarch.c:2935
void set_gdbarch_have_nonsteppable_watchpoint(struct gdbarch *gdbarch, int have_nonsteppable_watchpoint)
Definition: gdbarch.c:3261
void set_gdbarch_value_to_register(struct gdbarch *gdbarch, gdbarch_value_to_register_ftype value_to_register)
Definition: gdbarch.c:2457
void ppc_collect_vsxregset(const struct regset *regset, const struct regcache *regcache, int regnum, void *vsxregs, size_t len)
Definition: rs6000-tdep.c:749
static void show_powerpc_exact_watchpoints(struct ui_file *file, int from_tty, struct cmd_list_element *c, const char *value)
Definition: rs6000-tdep.c:6080
ULONGEST extract_unsigned_integer(const gdb_byte *, int, enum bfd_endian)
Definition: findvar.c:84
char * main_name(void)
Definition: symtab.c:6015
struct cmd_list_element * add_prefix_cmd(const char *name, enum command_class theclass, cmd_cfunc_ftype *fun, const char *doc, struct cmd_list_element **prefixlist, const char *prefixname, int allow_unknown, struct cmd_list_element **list)
Definition: cli-decode.c:338
static const struct variant * find_variant_by_arch(enum bfd_architecture arch, unsigned long mach)
Definition: rs6000-tdep.c:3097
struct type * builtin_declong
Definition: gdbtypes.h:1501
void set_gdbarch_skip_main_prologue(struct gdbarch *gdbarch, gdbarch_skip_main_prologue_ftype skip_main_prologue)
Definition: gdbarch.c:2614
void set_gdbarch_ps_regnum(struct gdbarch *gdbarch, int ps_regnum)
Definition: gdbarch.c:2025
powerpc_vector_abi
Definition: ppc-tdep.h:195
struct frame_id frame_id_build(CORE_ADDR stack_addr, CORE_ADDR code_addr)
Definition: frame.c:554
#define B_INSN
Definition: rs6000-tdep.c:972
#define PPC_XT(insn)
Definition: rs6000-tdep.c:3686
#define LWARX_MASK
Definition: rs6000-tdep.c:1081
int ppc_vsr0_regnum
Definition: ppc-tdep.h:234
#define BP_INSN
Definition: rs6000-tdep.c:975
int ppc_ev0_regnum
Definition: ppc-tdep.h:244
void ppc_supply_gregset(const struct regset *regset, struct regcache *regcache, int regnum, const void *gregs, size_t len)
Definition: rs6000-tdep.c:505
static void rs6000_frame_this_id(struct frame_info *this_frame, void **this_cache, struct frame_id *this_id)
Definition: rs6000-tdep.c:3321
static void initialize_tdesc_powerpc_403gc(void)
Definition: powerpc-403gc.c:10
void set_gdbarch_float_bit(struct gdbarch *gdbarch, int float_bit)
Definition: gdbarch.c:1601
void set_gdbarch_displaced_step_fixup(struct gdbarch *gdbarch, gdbarch_displaced_step_fixup_ftype displaced_step_fixup)
Definition: gdbarch.c:3709
static int store_param_on_stack_p(unsigned long op, int framep, int *r0_contains_arg)
Definition: rs6000-tdep.c:1193
CORE_ADDR get_frame_pc(struct frame_info *frame)
Definition: frame.c:2217
void set_gdbarch_fp0_regnum(struct gdbarch *gdbarch, int fp0_regnum)
Definition: gdbarch.c:2042
#define MSYMBOL_LINKAGE_NAME(symbol)
Definition: symtab.h:409
static const char * powerpc_vector_abi_string
Definition: rs6000-tdep.c:125
struct frame_info * get_current_frame(void)
Definition: frame.c:1461
int * sim_regno
Definition: ppc-tdep.h:257
bfd_vma CORE_ADDR
Definition: common-types.h:41
void gdbarch_init_osabi(struct gdbarch_info info, struct gdbarch *gdbarch)
Definition: osabi.c:341
enum register_status(* move_ev_register_func)(struct regcache *, int, void *)
Definition: rs6000-tdep.c:2575
static void ppc_dwarf2_frame_init_reg(struct gdbarch *gdbarch, int regnum, struct dwarf2_frame_state_reg *reg, struct frame_info *this_frame)
Definition: rs6000-tdep.c:3478
static int rs6000_in_solib_return_trampoline(struct gdbarch *gdbarch, CORE_ADDR pc, const char *name)
Definition: rs6000-tdep.c:2220
void ppc_supply_vrregset(const struct regset *regset, struct regcache *regcache, int regnum, const void *vrregs, size_t len)
Definition: rs6000-tdep.c:618
static int ppc_vrreg_offset(struct gdbarch_tdep *tdep, const struct ppc_reg_offsets *offsets, int regnum)
Definition: rs6000-tdep.c:483
static const struct frame_base rs6000_frame_base
Definition: rs6000-tdep.c:3461
static void set_sim_regno(int *table, int gdb_regno, int sim_regno)
Definition: rs6000-tdep.c:249
struct value * trad_frame_get_prev_register(struct frame_info *this_frame, struct trad_frame_saved_reg this_saved_regs[], int regnum)
Definition: trad-frame.c:135
#define BL_DISPLACEMENT_MASK
Definition: rs6000-tdep.c:1299
void xfree(void *)
Definition: common-utils.c:97
static CORE_ADDR rs6000_skip_stack_check(struct gdbarch *gdbarch, const CORE_ADDR start_pc)
Definition: rs6000-tdep.c:1322
static void initialize_tdesc_powerpc_750(void)
Definition: powerpc-750.c:10
#define GDBARCH_OBSTACK_CALLOC(GDBARCH, NR, TYPE)
Definition: gdbarch.h:1614
int record_full_arch_list_add_reg(struct regcache *regcache, int regnum)
Definition: record-full.c:466
int ppc_lr_regnum
Definition: ppc-tdep.h:218
struct gdbarch * get_regcache_arch(const struct regcache *regcache)
Definition: regcache.c:297
void(* func)(char *)
void add_setshow_enum_cmd(const char *name, enum command_class theclass, const char *const *enumlist, const char **var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_sfunc_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
Definition: cli-decode.c:487
void set_tdesc_pseudo_register_type(struct gdbarch *gdbarch, gdbarch_register_type_ftype *pseudo_type)
static int ppc_fpreg_offset(struct gdbarch_tdep *tdep, const struct ppc_reg_offsets *offsets, int regnum)
Definition: rs6000-tdep.c:468
void set_gdbarch_skip_trampoline_code(struct gdbarch *gdbarch, gdbarch_skip_trampoline_code_ftype skip_trampoline_code)
Definition: gdbarch.c:3084
#define PPC_BO(insn)
Definition: rs6000-tdep.c:3674
void trad_frame_set_value(struct trad_frame_saved_reg this_saved_regs[], int regnum, LONGEST val)
Definition: trad-frame.c:92
static int rs6000_dwarf2_reg_to_regnum(struct gdbarch *gdbarch, int num)
Definition: rs6000-tdep.c:2909
struct gdbarch_tdep * tdep
Definition: gdbarch.c:134
static void initialize_tdesc_powerpc_altivec32(void)
static enum register_status vsx_pseudo_register_read(struct gdbarch *gdbarch, struct regcache *regcache, int reg_nr, gdb_byte *buffer)
Definition: rs6000-tdep.c:2722
int ppc_efpr0_regnum
Definition: ppc-tdep.h:236
void set_gdbarch_stab_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_stab_reg_to_regnum_ftype stab_reg_to_regnum)
Definition: gdbarch.c:2059
#define TYPE_NAME(thistype)
Definition: gdbtypes.h:1227
struct target_desc * tdesc_powerpc_altivec32
void set_gdbarch_displaced_step_location(struct gdbarch *gdbarch, gdbarch_displaced_step_location_ftype displaced_step_location)
Definition: gdbarch.c:3743
static void initialize_tdesc_powerpc_405(void)
Definition: powerpc-405.c:10
static CORE_ADDR skip_prologue(struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata)
Definition: rs6000-tdep.c:1504
static struct type * rs6000_builtin_type_vec64(struct gdbarch *gdbarch)
Definition: rs6000-tdep.c:2300
static int ppc_record_vsr(struct regcache *regcache, struct gdbarch_tdep *tdep, int vsr)
Definition: rs6000-tdep.c:3694
void convert_typed_floating(const void *from, const struct type *from_type, void *to, const struct type *to_type)
Definition: doublest.c:862
ULONGEST frame_unwind_register_unsigned(struct frame_info *frame, int regnum)
Definition: frame.c:1182
void set_gdbarch_short_bit(struct gdbarch *gdbarch, int short_bit)
Definition: gdbarch.c:1483
struct ui_file * gdb_stdout
Definition: main.c:71
static int max_skip_non_prologue_insns
Definition: rs6000-tdep.c:1185
int ppc_fpscr_regnum
Definition: ppc-tdep.h:228
const struct builtin_type * builtin_type(struct gdbarch *gdbarch)
Definition: gdbtypes.c:4766
struct frame_id frame_id_build_unavailable_stack(CORE_ADDR code_addr)
Definition: frame.c:527
static int ppc_process_record_op60(struct gdbarch *gdbarch, struct regcache *regcache, CORE_ADDR addr, uint32_t insn)
Definition: rs6000-tdep.c:4605
static int rs6000_stab_reg_to_regnum(struct gdbarch *gdbarch, int num)
Definition: rs6000-tdep.c:2867
void set_gdbarch_frame_red_zone_size(struct gdbarch *gdbarch, int frame_red_zone_size)
Definition: gdbarch.c:2968
void internal_error(const char *file, int line, const char *fmt,...)
Definition: errors.c:50
int lr_frame_offset
Definition: ppc-tdep.h:252
int gdbarch_update_p(struct gdbarch_info info)
Definition: arch-utils.c:508
const char * tdesc_register_name(struct gdbarch *gdbarch, int regno)
struct m32c_reg * pc
Definition: m32c-tdep.c:111
static unsigned int read_insn(struct frame_info *frame, CORE_ADDR pc)
Definition: rs6000-tdep.c:6090
static void initialize_tdesc_powerpc_603(void)
Definition: powerpc-603.c:10
int tdesc_register_size(const struct tdesc_feature *feature, const char *name)
int safe_read_memory_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order, LONGEST *return_value)
Definition: corefile.c:297
struct displaced_step_closure * simple_displaced_step_copy_insn(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
Definition: arch-utils.c:42
static enum register_status do_regcache_raw_write(struct regcache *regcache, int regnum, void *buffer)
Definition: rs6000-tdep.c:2642
int ppc_spefscr_regnum
Definition: ppc-tdep.h:246
#define PPC_MAX_EPILOGUE_INSTRUCTIONS
Definition: ppc-tdep.h:330
struct type * arch_composite_type(struct gdbarch *gdbarch, char *name, enum type_code code)
Definition: gdbtypes.c:4682
#define BC_INSN
Definition: rs6000-tdep.c:973
struct gdbarch_list * gdbarch_list_lookup_by_info(struct gdbarch_list *arches, const struct gdbarch_info *info)
Definition: gdbarch.c:4985
void set_gdbarch_deprecated_fp_regnum(struct gdbarch *gdbarch, int deprecated_fp_regnum)
Definition: gdbarch.c:2192
CORE_ADDR skip_prologue_using_sal(struct gdbarch *gdbarch, CORE_ADDR func_addr)
Definition: symtab.c:3882
struct gdbarch_list * next
Definition: gdbarch.h:1543
int vsx_register_p(struct gdbarch *gdbarch, int regno)
Definition: rs6000-tdep.c:156
struct address_space * get_frame_address_space(struct frame_info *frame)
Definition: frame.c:2490
int gdbarch_num_regs(struct gdbarch *gdbarch)
Definition: gdbarch.c:1898
struct reggroup *const all_reggroup
Definition: reggroups.c:296
#define _(String)
Definition: gdb_locale.h:40
const struct bfd_arch_info * bfd_arch_info
Definition: gdbarch.h:1549
struct target_desc * tdesc_rs6000
Definition: rs6000.c:8
int ppc_process_record(struct gdbarch *gdbarch, struct regcache *regcache, CORE_ADDR addr)
Definition: rs6000-tdep.c:5056
static struct value * rs6000_frame_prev_register(struct frame_info *this_frame, void **this_cache, int regnum)
Definition: rs6000-tdep.c:3334
void set_gdbarch_dwarf2_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_dwarf2_reg_to_regnum_ftype dwarf2_reg_to_regnum)
Definition: gdbarch.c:2110
struct gdbarch_tdep_info * tdep_info
Definition: gdbarch.h:1560
int ppc_deal_with_atomic_sequence(struct frame_info *frame)
Definition: rs6000-tdep.c:1094
int ppc_cr_regnum
Definition: ppc-tdep.h:217
struct gdbarch_tdep * gdbarch_tdep(struct gdbarch *gdbarch)
Definition: gdbarch.c:1402
static int rs6000_in_function_epilogue_frame_p(struct frame_info *curfrm, struct gdbarch *gdbarch, CORE_ADDR pc)
Definition: rs6000-tdep.c:877
void tdesc_data_cleanup(void *data_untyped)
#define END_CATCH
void set_gdbarch_displaced_step_hw_singlestep(struct gdbarch *gdbarch, gdbarch_displaced_step_hw_singlestep_ftype displaced_step_hw_singlestep)
Definition: gdbarch.c:3684
void frame_unwind_append_unwinder(struct gdbarch *gdbarch, const struct frame_unwind *unwinder)
Definition: frame-unwind.c:78
static int rs6000_pseudo_register_reggroup_p(struct gdbarch *gdbarch, int regnum, struct reggroup *group)
Definition: rs6000-tdep.c:2498
static const struct frame_unwind rs6000_frame_unwind
Definition: rs6000-tdep.c:3342
struct target_desc * tdesc_powerpc_604
Definition: powerpc-604.c:8
static CORE_ADDR rs6000_skip_prologue(struct gdbarch *gdbarch, CORE_ADDR pc)
Definition: rs6000-tdep.c:2117
struct type * builtin_int32
Definition: gdbtypes.h:1518
static const unsigned char * rs6000_breakpoint_from_pc(struct gdbarch *gdbarch, CORE_ADDR *bp_addr, int *bp_size)
Definition: rs6000-tdep.c:957
struct target_desc * tdesc_powerpc_7400
Definition: powerpc-7400.c:8
#define FRAME_OBSTACK_ZALLOC(TYPE)
Definition: frame.h:660
static void ppc_displaced_step_fixup(struct gdbarch *gdbarch, struct displaced_step_closure *closure, CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
Definition: rs6000-tdep.c:980
const char * paddress(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: utils.c:2743
enum powerpc_vector_abi vector_abi
Definition: ppc-tdep.h:212
static const char * rs6000_register_name(struct gdbarch *gdbarch, int regno)
Definition: rs6000-tdep.c:2393
struct target_desc * tdesc_powerpc_403gc
Definition: powerpc-403gc.c:8
int ppc_altivec_support_p(struct gdbarch *gdbarch)
Definition: rs6000-tdep.c:233
static void dfp_pseudo_register_write(struct gdbarch *gdbarch, struct regcache *regcache, int reg_nr, const gdb_byte *buffer)
Definition: rs6000-tdep.c:2696
void gdbarch_register(enum bfd_architecture bfd_architecture, gdbarch_init_ftype *init, gdbarch_dump_tdep_ftype *dump_tdep)
Definition: gdbarch.c:4933
void ppc_collect_gregset(const struct regset *regset, const struct regcache *regcache, int regnum, void *gregs, size_t len)
Definition: rs6000-tdep.c:663
Definition: regset.h:34
#define STDCX_INSTRUCTION
Definition: rs6000-tdep.c:1086
int gdbarch_num_pseudo_regs(struct gdbarch *gdbarch)
Definition: gdbarch.c:1916
#define TRY
#define PPC_RA(insn)
Definition: rs6000-tdep.c:3667
struct reggroup *const float_reggroup
Definition: reggroups.c:293
int tdesc_numbered_register(const struct tdesc_feature *feature, struct tdesc_arch_data *data, int regno, const char *name)
struct cmd_list_element * setlist
Definition: cli-cmds.c:135
#define PPC_Rc(insn)
Definition: rs6000-tdep.c:3681
const char *const name
Definition: aarch64-tdep.c:68
void add_setshow_auto_boolean_cmd(const char *name, enum command_class theclass, enum auto_boolean *var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_sfunc_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
Definition: cli-decode.c:516
int * from
Definition: varobj.h:282
void set_gdbarch_pseudo_register_write(struct gdbarch *gdbarch, gdbarch_pseudo_register_write_ftype pseudo_register_write)
Definition: gdbarch.c:1891
static void init_sim_regno_table(struct gdbarch *arch)
Definition: rs6000-tdep.c:262
#define PPC_XER_NB(xer)
Definition: rs6000-tdep.c:3687
LONGEST read_memory_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition: corefile.c:311
unsigned int gpr_mask
Definition: rs6000-tdep.c:135
#define CATCH(EXCEPTION, MASK)
static CORE_ADDR rs6000_unwind_pc(struct gdbarch *gdbarch, struct frame_info *next_frame)
Definition: rs6000-tdep.c:3118
static void rs6000_value_to_register(struct frame_info *frame, int regnum, struct type *type, const gdb_byte *from)
Definition: rs6000-tdep.c:2558
int tdesc_numbered_register_choices(const struct tdesc_feature *feature, struct tdesc_arch_data *data, int regno, const char *const names[])
int ppc_vsr0_upper_regnum
Definition: ppc-tdep.h:235
enum register_status regcache_raw_read_part(struct regcache *regcache, int regnum, int offset, int len, gdb_byte *buf)
Definition: regcache.c:995
struct target_desc * tdesc_powerpc_602
Definition: powerpc-602.c:8
static CORE_ADDR rs6000_frame_align(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: rs6000-tdep.c:2191
static enum auto_boolean powerpc_soft_float_global
Definition: rs6000-tdep.c:111
static int rs6000_stack_frame_destroyed_p(struct gdbarch *gdbarch, CORE_ADDR pc)
Definition: rs6000-tdep.c:940
CORE_ADDR ppc64_sysv_abi_push_dummy_call(struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr)
int ppc_toc_regnum
Definition: ppc-tdep.h:215
void dwarf2_frame_set_init_reg(struct gdbarch *gdbarch, void(*init_reg)(struct gdbarch *, int, struct dwarf2_frame_state_reg *, struct frame_info *))
Definition: dwarf2-frame.c:780
struct target_ops current_target
void initialize_file_ftype(void)
Definition: defs.h:281
struct symtab_and_line find_pc_line(CORE_ADDR pc, int notcurrent)
Definition: symtab.c:3315
int gdbarch_sp_regnum(struct gdbarch *gdbarch)
Definition: gdbarch.c:1981
static const char *const powerpc_vector_strings[]
Definition: rs6000-tdep.c:114
int ppc_vrsave_regnum
Definition: ppc-tdep.h:240
#define PPC_RC(insn)
Definition: rs6000-tdep.c:3680
static struct rs6000_frame_cache * rs6000_epilogue_frame_cache(struct frame_info *this_frame, void **this_cache)
Definition: rs6000-tdep.c:3356
static int ppc_process_record_op59(struct gdbarch *gdbarch, struct regcache *regcache, CORE_ADDR addr, uint32_t insn)
Definition: rs6000-tdep.c:4512
void fprintf_filtered(struct ui_file *stream, const char *format,...)
Definition: utils.c:2351
#define PPC_BIT(insn, n)
Definition: rs6000-tdep.c:3678
register_status
Definition: regcache.h:50
static void initialize_tdesc_powerpc_e500(void)
Definition: powerpc-e500.c:10
CORE_ADDR find_solib_trampoline_target(struct frame_info *frame, CORE_ADDR pc)
Definition: minsyms.c:1394
static struct type * rs6000_builtin_type_vec128(struct gdbarch *gdbarch)
Definition: rs6000-tdep.c:2345
void set_gdbarch_stack_frame_destroyed_p(struct gdbarch *gdbarch, gdbarch_stack_frame_destroyed_p_ftype stack_frame_destroyed_p)
Definition: gdbarch.c:3135
static int rs6000_adjust_frame_regnum(struct gdbarch *gdbarch, int num, int eh_frame_p)
Definition: rs6000-tdep.c:2954
struct target_desc * tdesc_powerpc_403
Definition: powerpc-403.c:8
enum register_status regcache_cooked_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition: regcache.c:837
int safe_frame_unwind_memory(struct frame_info *this_frame, CORE_ADDR addr, gdb_byte *buf, int len)
Definition: frame.c:2525
#define PPC_FIELD(value, from, len)
Definition: rs6000-tdep.c:3657
void set_gdbarch_sp_regnum(struct gdbarch *gdbarch, int sp_regnum)
Definition: gdbarch.c:1991
#define PPC_NB(insn)
Definition: rs6000-tdep.c:3669
#define PPC_INSN_SIZE
Definition: ppc-tdep.h:327
#define BL_INSTRUCTION
Definition: rs6000-tdep.c:1298
int debug_displaced
Definition: infrun.c:132
bfd * abfd
Definition: gdbarch.h:1557
void register_e500_ravenscar_ops(struct gdbarch *gdbarch)
struct target_desc * tdesc_powerpc_405
Definition: powerpc-405.c:8
#define PPC_RS(insn)
Definition: rs6000-tdep.c:3666
void set_gdbarch_dummy_id(struct gdbarch *gdbarch, gdbarch_dummy_id_ftype dummy_id)
Definition: gdbarch.c:2175
void fprintf_unfiltered(struct ui_file *stream, const char *format,...)
Definition: utils.c:2361
mach_port_t mach_port_t name mach_port_t mach_port_t name error_t int status
Definition: gnu-nat.c:1816
static int bfd_uses_spe_extensions(bfd *abfd)
Definition: rs6000-tdep.c:3543
void set_gdbarch_in_solib_return_trampoline(struct gdbarch *gdbarch, gdbarch_in_solib_return_trampoline_ftype in_solib_return_trampoline)
Definition: gdbarch.c:3118
int ppc_gp0_regnum
Definition: ppc-tdep.h:214
int target_auxv_search(struct target_ops *ops, CORE_ADDR match, CORE_ADDR *valp)
Definition: auxv.c:375
struct cmd_list_element * showlist
Definition: cli-cmds.c:143
int ppc_acc_regnum
Definition: ppc-tdep.h:245
void set_gdbarch_believe_pcc_promotion(struct gdbarch *gdbarch, int believe_pcc_promotion)
Definition: gdbarch.c:2406
static const struct frame_base * rs6000_frame_base_sniffer(struct frame_info *this_frame)
Definition: rs6000-tdep.c:3469
#define TYPE_VECTOR(t)
Definition: gdbtypes.h:287
static void initialize_tdesc_rs6000(void)
Definition: rs6000.c:10
void insert_single_step_breakpoint(struct gdbarch *gdbarch, struct address_space *aspace, CORE_ADDR next_pc)
Definition: breakpoint.c:14816
static CORE_ADDR rs6000_fetch_pointer_argument(struct frame_info *frame, int argi, struct type *type)
Definition: rs6000-tdep.c:948
struct type * builtin_int16
Definition: gdbtypes.h:1516
enum bfd_endian gdbarch_byte_order(struct gdbarch *gdbarch)
Definition: gdbarch.c:1420
void set_gdbarch_register_sim_regno(struct gdbarch *gdbarch, gdbarch_register_sim_regno_ftype register_sim_regno)
Definition: gdbarch.c:2332
static int ppc_greg_offset(struct gdbarch *gdbarch, struct gdbarch_tdep *tdep, const struct ppc_reg_offsets *offsets, int regnum, int *regsize)
Definition: rs6000-tdep.c:430
static void initialize_tdesc_powerpc_601(void)
Definition: powerpc-601.c:10
static int bl_to_blrl_insn_p(CORE_ADDR pc, int insn, enum bfd_endian byte_order)
Definition: rs6000-tdep.c:1266
#define TARGET_CHAR_BIT
Definition: host-defs.h:29
enum gdb_osabi osabi
Definition: gdbarch.h:1563
Definition: gdbtypes.h:749
int find_pc_partial_function(CORE_ADDR pc, const char **name, CORE_ADDR *address, CORE_ADDR *endaddr)
Definition: blockframe.c:321
struct type * init_vector_type(struct type *elt_type, int n)
Definition: gdbtypes.c:1229
void set_gdbarch_register_to_value(struct gdbarch *gdbarch, gdbarch_register_to_value_ftype register_to_value)
Definition: gdbarch.c:2440
#define PPC_RT(insn)
Definition: rs6000-tdep.c:3665
void set_gdbarch_unwind_pc(struct gdbarch *gdbarch, gdbarch_unwind_pc_ftype unwind_pc)
Definition: gdbarch.c:2863
void set_gdbarch_breakpoint_from_pc(struct gdbarch *gdbarch, gdbarch_breakpoint_from_pc_ftype breakpoint_from_pc)
Definition: gdbarch.c:2672
int ppc_dl0_regnum
Definition: ppc-tdep.h:249
static CORE_ADDR rs6000_skip_main_prologue(struct gdbarch *gdbarch, CORE_ADDR pc)
Definition: rs6000-tdep.c:2161
int default_frame_sniffer(const struct frame_unwind *self, struct frame_info *this_frame, void **this_prologue_cache)
Definition: frame-unwind.c:170
static const char * type
Definition: language.c:103
static void powerpc_set_soft_float(char *args, int from_tty, struct cmd_list_element *c)
Definition: rs6000-tdep.c:6039
#define PPC_SPR(insn)
Definition: rs6000-tdep.c:3672
#define gdb_assert(expr)
Definition: gdb_assert.h:33
int(* ppc_syscall_record)(struct regcache *regcache)
Definition: ppc-tdep.h:263
static void set_powerpc_command(char *args, int from_tty)
Definition: rs6000-tdep.c:6025
const char * gdbarch_register_name(struct gdbarch *gdbarch, int regnr)
Definition: gdbarch.c:2117
static int startswith(const char *string, const char *pattern)
Definition: common-utils.h:75
static void initialize_tdesc_powerpc_64(void)
Definition: powerpc-64.c:10
enum register_status regcache_raw_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition: regcache.c:690
static struct frame_id rs6000_dummy_id(struct gdbarch *gdbarch, struct frame_info *this_frame)
Definition: rs6000-tdep.c:3125
void ppc_supply_fpregset(const struct regset *regset, struct regcache *regcache, int regnum, const void *fpregs, size_t len)
Definition: rs6000-tdep.c:550
int altivec_register_p(struct gdbarch *gdbarch, int regno)
Definition: rs6000-tdep.c:168
int soft_float
Definition: ppc-tdep.h:207
int target_exact_watchpoints
Definition: breakpoint.c:551
struct gdbarch * gdbarch
Definition: gdbarch.h:1542
int regnum
Definition: aarch64-tdep.c:69
void printf_unfiltered(const char *format,...)
Definition: utils.c:2399
static void initialize_tdesc_powerpc_vsx32(void)
Definition: powerpc-vsx32.c:10
static struct type * rs6000_pseudo_register_type(struct gdbarch *gdbarch, int regnum)
Definition: rs6000-tdep.c:2472
int user_reg_map_name_to_regnum(struct gdbarch *gdbarch, const char *name, int len)
Definition: user-regs.c:129
struct reggroup *const vector_reggroup
Definition: reggroups.c:295
CORE_ADDR displaced_step_at_entry_point(struct gdbarch *gdbarch)
Definition: arch-utils.c:78
CORE_ADDR ppc_sysv_abi_push_dummy_call(struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr)
Definition: ppc-sysv-tdep.c:60
static struct rs6000_frame_cache * rs6000_frame_cache(struct frame_info *this_frame, void **this_cache)
Definition: rs6000-tdep.c:3140
ULONGEST get_frame_register_unsigned(struct frame_info *frame, int regnum)
Definition: frame.c:1194
static int ppc_displaced_step_hw_singlestep(struct gdbarch *gdbarch, struct displaced_step_closure *closure)
Definition: rs6000-tdep.c:1074
void * xmalloc(YYSIZE_T)
struct ui_file * gdb_stdlog
Definition: main.c:73
void set_gdbarch_sofun_address_maybe_missing(struct gdbarch *gdbarch, int sofun_address_maybe_missing)
Definition: gdbarch.c:3857
static int insn_changes_sp_or_jumps(unsigned long insn)
Definition: rs6000-tdep.c:825
struct type * builtin_uint128
Definition: gdbtypes.h:1523
static int ppc_process_record_op31(struct gdbarch *gdbarch, struct regcache *regcache, CORE_ADDR addr, uint32_t insn)
Definition: rs6000-tdep.c:4033
void set_gdbarch_frame_args_skip(struct gdbarch *gdbarch, CORE_ADDR frame_args_skip)
Definition: gdbarch.c:2839
struct target_desc * tdesc_powerpc_64
Definition: powerpc-64.c:8
void set_gdbarch_long_long_bit(struct gdbarch *gdbarch, int long_long_bit)
Definition: gdbarch.c:1534
char * name
Definition: rs6000-tdep.c:3022
void cmd_show_list(struct cmd_list_element *list, int from_tty, const char *prefix)
Definition: cli-setshow.c:672
static void rs6000_pseudo_register_write(struct gdbarch *gdbarch, struct regcache *regcache, int reg_nr, const gdb_byte *buffer)
Definition: rs6000-tdep.c:2841
CORE_ADDR initial_sp
Definition: rs6000-tdep.c:3135
#define PPC_LEV(insn)
Definition: rs6000-tdep.c:3684
void ppc_collect_reg(const struct regcache *regcache, int regnum, gdb_byte *regs, size_t offset, int regsize)
Definition: rs6000-tdep.c:404
Definition: regdef.h:22
void put_frame_register(struct frame_info *frame, int regnum, const gdb_byte *buf)
Definition: frame.c:1220
int ppc_floating_point_unit_p(struct gdbarch *gdbarch)
Definition: rs6000-tdep.c:212
int record_full_arch_list_add_mem(CORE_ADDR addr, int len)
Definition: record-full.c:489
const struct target_desc * target_desc
Definition: gdbarch.h:1566
Definition: value.c:172
void set_gdbarch_software_single_step(struct gdbarch *gdbarch, gdbarch_software_single_step_ftype software_single_step)
Definition: gdbarch.c:3026
static void show_powerpc_command(char *args, int from_tty)
Definition: rs6000-tdep.c:6033
static enum register_status e500_pseudo_register_read(struct gdbarch *gdbarch, struct regcache *regcache, int reg_nr, gdb_byte *buffer)
Definition: rs6000-tdep.c:2650
CORE_ADDR ppc_insn_d_field(unsigned int insn)
Definition: rs6000-tdep.c:6141
static void initialize_tdesc_powerpc_altivec64(void)
#define SIGNED_SHORT(x)
Definition: rs6000-tdep.c:1176
#define LDARX_INSTRUCTION
Definition: rs6000-tdep.c:1083
static void initialize_tdesc_powerpc_505(void)
Definition: powerpc-505.c:10
struct type * ppc_builtin_type_vec128
Definition: ppc-tdep.h:261
void regcache_raw_write_part(struct regcache *regcache, int regnum, int offset, int len, const gdb_byte *buf)
Definition: regcache.c:1006
static int ppc_process_record_op63(struct gdbarch *gdbarch, struct regcache *regcache, CORE_ADDR addr, uint32_t insn)
Definition: rs6000-tdep.c:4888
struct trad_frame_saved_reg * trad_frame_alloc_saved_regs(struct frame_info *this_frame)
Definition: trad-frame.c:52
#define BRANCH_MASK
Definition: rs6000-tdep.c:970
void throw_exception(struct gdb_exception exception)
void tdesc_use_registers(struct gdbarch *gdbarch, const struct target_desc *target_desc, struct tdesc_arch_data *early_data)
const char const char int
Definition: command.h:229
int core_addr_lessthan(CORE_ADDR lhs, CORE_ADDR rhs)
Definition: arch-utils.c:138
bfd_byte gdb_byte
Definition: common-types.h:38
int ppc_ctr_regnum
Definition: ppc-tdep.h:219
struct target_desc * tdesc_powerpc_e500
Definition: powerpc-e500.c:8
int ppc_vr0_regnum
Definition: ppc-tdep.h:239
void append_composite_type_field(struct type *t, char *name, struct type *field)
Definition: gdbtypes.c:4757
static void initialize_tdesc_powerpc_vsx64(void)
Definition: powerpc-vsx64.c:10
void help_list(struct cmd_list_element *list, const char *cmdtype, enum command_class theclass, struct ui_file *stream)
Definition: cli-decode.c:1023
#define PPC_EXTOP(insn)
Definition: rs6000-tdep.c:3664
static void initialize_tdesc_powerpc_32(void)
Definition: powerpc-32.c:10
struct target_desc * tdesc_powerpc_altivec64
struct target_desc * tdesc_powerpc_505
Definition: powerpc-505.c:8
#define BP_MASK
Definition: rs6000-tdep.c:971
void set_gdbarch_displaced_step_copy_insn(struct gdbarch *gdbarch, gdbarch_displaced_step_copy_insn_ftype displaced_step_copy_insn)
Definition: gdbarch.c:3667
void set_gdbarch_pseudo_register_read(struct gdbarch *gdbarch, gdbarch_pseudo_register_read_ftype pseudo_register_read)
Definition: gdbarch.c:1843
void set_gdbarch_char_signed(struct gdbarch *gdbarch, int char_signed)
Definition: gdbarch.c:1754
static CORE_ADDR rs6000_frame_base_address(struct frame_info *this_frame, void **this_cache)
Definition: rs6000-tdep.c:3454
sim_regno
Definition: sim-regno.h:30
static void efpr_pseudo_register_write(struct gdbarch *gdbarch, struct regcache *regcache, int reg_nr, const gdb_byte *buffer)
Definition: rs6000-tdep.c:2802
struct type * builtin_double
Definition: gdbtypes.h:1491
struct bound_minimal_symbol lookup_minimal_symbol_by_pc(CORE_ADDR pc)
Definition: minsyms.c:801
#define max(a, b)
Definition: defs.h:109
void set_gdbarch_convert_register_p(struct gdbarch *gdbarch, gdbarch_convert_register_p_ftype convert_register_p)
Definition: gdbarch.c:2423
void ppc_collect_fpregset(const struct regset *regset, const struct regcache *regcache, int regnum, void *fpregs, size_t len)
Definition: rs6000-tdep.c:710
static int rs6000_register_to_value(struct frame_info *frame, int regnum, struct type *type, gdb_byte *to, int *optimizedp, int *unavailablep)
Definition: rs6000-tdep.c:2535
static void e500_pseudo_register_write(struct gdbarch *gdbarch, struct regcache *regcache, int reg_nr, const gdb_byte *buffer)
Definition: rs6000-tdep.c:2657
static struct value * rs6000_epilogue_frame_prev_register(struct frame_info *this_frame, void **this_cache, int regnum)
Definition: rs6000-tdep.c:3416
#define GET_SRC_REG(x)
Definition: rs6000-tdep.c:1181
#define BL_MASK
Definition: rs6000-tdep.c:1297
int frame_relative_level(struct frame_info *fi)
Definition: frame.c:2454
initialize_file_ftype _initialize_rs6000_tdep
#define TYPE_CODE(thistype)
Definition: gdbtypes.h:1240
enum register_status regcache_raw_read(struct regcache *regcache, int regnum, gdb_byte *buf)
Definition: regcache.c:637
void regcache_cooked_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
Definition: regcache.c:871
#define IS_EFP_PSEUDOREG(tdep, regnum)
Definition: rs6000-tdep.c:102
int target_read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition: target.c:1393
int wordsize
Definition: ppc-tdep.h:206
void gdbarch_info_init(struct gdbarch_info *info)
Definition: arch-utils.c:708
static void initialize_tdesc_powerpc_860(void)
Definition: powerpc-860.c:10
#define IS_VSX_PSEUDOREG(tdep, regnum)
Definition: rs6000-tdep.c:97
void set_gdbarch_int_bit(struct gdbarch *gdbarch, int int_bit)
Definition: gdbarch.c:1500
static enum register_status e500_move_ev_register(move_ev_register_func move, struct regcache *regcache, int ev_reg, void *buffer)
Definition: rs6000-tdep.c:2603
int ppc_ev0_upper_regnum
Definition: ppc-tdep.h:243
struct minimal_symbol * minsym
Definition: minsyms.h:32
int ppc_ps_regnum
Definition: ppc-tdep.h:216
#define PPC_FRT(insn)
Definition: rs6000-tdep.c:3671
enum bfd_architecture arch
Definition: rs6000-tdep.c:3028
int offset
Definition: agent.c:65
static CORE_ADDR rs6000_skip_trampoline_code(struct frame_info *frame, CORE_ADDR pc)
Definition: rs6000-tdep.c:2241
Definition: buffer.h:23
void set_gdbarch_num_pseudo_regs(struct gdbarch *gdbarch, int num_pseudo_regs)
Definition: gdbarch.c:1926
int ppc_xer_regnum
Definition: ppc-tdep.h:220
static void rs6000_dump_tdep(struct gdbarch *gdbarch, struct ui_file *file)
Definition: rs6000-tdep.c:6012
void dwarf2_append_unwinders(struct gdbarch *gdbarch)
#define PPC_OP6(insn)
Definition: rs6000-tdep.c:3663
void set_gdbarch_fetch_pointer_argument(struct gdbarch *gdbarch, gdbarch_fetch_pointer_argument_ftype fetch_pointer_argument)
Definition: gdbarch.c:3374
enum return_value_convention ppc64_sysv_abi_return_value(struct gdbarch *gdbarch, struct value *function, struct type *valtype, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf)
struct type * ppc_builtin_type_vec64
Definition: ppc-tdep.h:260
int ppc_mq_regnum
Definition: ppc-tdep.h:231
CORE_ADDR pc
Definition: symtab.h:1376
struct target_desc * tdesc_powerpc_860
Definition: powerpc-860.c:8
CORE_ADDR ppc_insn_ds_field(unsigned int insn)
Definition: rs6000-tdep.c:6151
struct m32c_reg regs[M32C_MAX_NUM_REGS]
Definition: m32c-tdep.c:105
#define STWCX_MASK
Definition: rs6000-tdep.c:1084
char * description
Definition: rs6000-tdep.c:3025
void ** data
Definition: gdbarch.c:139
struct m32c_reg * sp
Definition: m32c-tdep.c:114
static int gdb_print_insn_powerpc(bfd_vma memaddr, disassemble_info *info)
Definition: rs6000-tdep.c:3109
#define STWCX_INSTRUCTION
Definition: rs6000-tdep.c:1085
struct tdesc_arch_data * tdesc_data_alloc(void)
void regcache_raw_supply(struct regcache *regcache, int regnum, const void *buf)
Definition: regcache.c:1041
void frame_base_append_sniffer(struct gdbarch *gdbarch, frame_base_sniffer_ftype *sniffer)
Definition: frame-base.c:82
int get_frame_register_bytes(struct frame_info *frame, int regnum, CORE_ADDR offset, int len, gdb_byte *myaddr, int *optimizedp, int *unavailablep)
Definition: frame.c:1274
auto_boolean
Definition: defs.h:196
#define PPC_OE(insn)
Definition: rs6000-tdep.c:3679
static enum register_status efpr_pseudo_register_read(struct gdbarch *gdbarch, struct regcache *regcache, int reg_nr, gdb_byte *buffer)
Definition: rs6000-tdep.c:2787
const void * regmap
Definition: regset.h:39
unsigned long long ULONGEST
Definition: common-types.h:53
enum unwind_stop_reason default_frame_unwind_stop_reason(struct frame_info *this_frame, void **this_cache)
Definition: frame-unwind.c:180
static unsigned long rs6000_fetch_instruction(struct gdbarch *gdbarch, const CORE_ADDR pc)
Definition: rs6000-tdep.c:1302
static int ppc_process_record_op4(struct gdbarch *gdbarch, struct regcache *regcache, CORE_ADDR addr, uint32_t insn)
Definition: rs6000-tdep.c:3720
const struct tdesc_feature * tdesc_find_feature(const struct target_desc *target_desc, const char *name)
int register_size(struct gdbarch *gdbarch, int regnum)
Definition: regcache.c:169
powerpc_elf_abi
Definition: ppc-tdep.h:186
int spe_register_p(struct gdbarch *gdbarch, int regno)
Definition: rs6000-tdep.c:180
void set_gdbarch_long_double_bit(struct gdbarch *gdbarch, int long_double_bit)
Definition: gdbarch.c:1667
void register_ppc_ravenscar_ops(struct gdbarch *gdbarch)
struct type * builtin_int64
Definition: gdbtypes.h:1520
static int rs6000_convert_register_p(struct gdbarch *gdbarch, int regnum, struct type *type)
Definition: rs6000-tdep.c:2521
void set_gdbarch_long_bit(struct gdbarch *gdbarch, int long_bit)
Definition: gdbarch.c:1517
void set_gdbarch_return_value(struct gdbarch *gdbarch, gdbarch_return_value_ftype return_value)
Definition: gdbarch.c:2556
const struct bfd_arch_info * gdbarch_bfd_arch_info(struct gdbarch *gdbarch)
Definition: gdbarch.c:1411
static struct gdbarch * rs6000_gdbarch_init(struct gdbarch_info info, struct gdbarch_list *arches)
Definition: rs6000-tdep.c:5346
void regcache_raw_collect(const struct regcache *regcache, int regnum, void *buf)
Definition: regcache.c:1071
void ppc_supply_reg(struct regcache *regcache, int regnum, const gdb_byte *regs, size_t offset, int regsize)
Definition: rs6000-tdep.c:383
int gdbarch_pc_regnum(struct gdbarch *gdbarch)
Definition: gdbarch.c:1998
static void initialize_tdesc_powerpc_403(void)
Definition: powerpc-403.c:10
void set_gdbarch_displaced_step_free_closure(struct gdbarch *gdbarch, gdbarch_displaced_step_free_closure_ftype displaced_step_free_closure)
Definition: gdbarch.c:3726
#define LWARX_INSTRUCTION
Definition: rs6000-tdep.c:1082
void ppc_collect_vrregset(const struct regset *regset, const struct regcache *regcache, int regnum, void *vrregs, size_t len)
Definition: rs6000-tdep.c:783
void set_tdesc_pseudo_register_reggroup_p(struct gdbarch *gdbarch, gdbarch_register_reggroup_p_ftype *pseudo_reggroup_p)
struct target_desc * tdesc_powerpc_601
Definition: powerpc-601.c:8
int ppc_insns_match_pattern(struct frame_info *frame, CORE_ADDR pc, struct ppc_insn_pattern *pattern, unsigned int *insns)
Definition: rs6000-tdep.c:6112
static void vsx_pseudo_register_write(struct gdbarch *gdbarch, struct regcache *regcache, int reg_nr, const gdb_byte *buffer)
Definition: rs6000-tdep.c:2757
static int ppc_process_record_op19(struct gdbarch *gdbarch, struct regcache *regcache, CORE_ADDR addr, uint32_t insn)
Definition: rs6000-tdep.c:3989
#define TYPE_LENGTH(thistype)
Definition: gdbtypes.h:1237
int int * to
Definition: varobj.h:282
void set_gdbarch_ptr_bit(struct gdbarch *gdbarch, int ptr_bit)
Definition: gdbarch.c:1700
unsigned int mask
Definition: ppc-tdep.h:311
enum powerpc_elf_abi elf_abi
Definition: ppc-tdep.h:209
void set_gdbarch_push_dummy_call(struct gdbarch *gdbarch, gdbarch_push_dummy_call_ftype push_dummy_call)
Definition: gdbarch.c:2216
struct trad_frame_saved_reg * saved_regs
Definition: rs6000-tdep.c:3136
CORE_ADDR get_pc_function_start(CORE_ADDR pc)
Definition: blockframe.c:86
ULONGEST read_memory_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition: corefile.c:321
#define PPC_VRT(insn)
Definition: rs6000-tdep.c:3670
unsigned long mach
Definition: rs6000-tdep.c:3031
#define PPC_RB(insn)
Definition: rs6000-tdep.c:3668
void set_gdbarch_skip_prologue(struct gdbarch *gdbarch, gdbarch_skip_prologue_ftype skip_prologue)
Definition: gdbarch.c:2590
#define BXL_INSN
Definition: rs6000-tdep.c:974
struct type * builtin_int8
Definition: gdbtypes.h:1514
static void initialize_tdesc_powerpc_604(void)
Definition: powerpc-604.c:10
static struct gdbarch_data * tdesc_data
enum bfd_endian byte_order
Definition: gdbarch.h:1552
static void powerpc_set_vector_abi(char *args, int from_tty, struct cmd_list_element *c)
Definition: rs6000-tdep.c:6051
enum bfd_endian byte_order
Definition: gdbarch.c:128
static enum register_status do_regcache_raw_read(struct regcache *regcache, int regnum, void *buffer)
Definition: rs6000-tdep.c:2636
void set_gdbarch_pc_regnum(struct gdbarch *gdbarch, int pc_regnum)
Definition: gdbarch.c:2008
void set_gdbarch_max_insn_length(struct gdbarch *gdbarch, ULONGEST max_insn_length)
Definition: gdbarch.c:3643
void ppc_supply_vsxregset(const struct regset *regset, struct regcache *regcache, int regnum, const void *vsxregs, size_t len)
Definition: rs6000-tdep.c:587
int record_full_arch_list_add_end(void)
Definition: record-full.c:520
int tdesc_has_registers(const struct target_desc *target_desc)
void set_gdbarch_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype register_name)
Definition: gdbarch.c:2127
CORE_ADDR get_frame_func(struct frame_info *this_frame)
Definition: frame.c:920
struct target_desc ** tdesc
Definition: rs6000-tdep.c:3034
static void initialize_tdesc_powerpc_7400(void)
Definition: powerpc-7400.c:10
static enum powerpc_vector_abi powerpc_vector_abi_global
Definition: rs6000-tdep.c:124
enum return_value_convention ppc_sysv_abi_return_value(struct gdbarch *gdbarch, struct value *function, struct type *valtype, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf)
enum dwarf2_frame_reg_rule how
Definition: dwarf2-frame.h:82
int ppc_fp0_regnum
Definition: ppc-tdep.h:227
size_t size
Definition: go32-nat.c:242
struct gdbarch * gdbarch_alloc(const struct gdbarch_info *info, struct gdbarch_tdep *tdep)
Definition: gdbarch.c:339
void set_gdbarch_inner_than(struct gdbarch *gdbarch, gdbarch_inner_than_ftype inner_than)
Definition: gdbarch.c:2655
#define PPC_D(insn)
Definition: rs6000-tdep.c:3676
static enum register_status rs6000_pseudo_register_read(struct gdbarch *gdbarch, struct regcache *regcache, int reg_nr, gdb_byte *buffer)
Definition: rs6000-tdep.c:2816
struct gdbarch * get_frame_arch(struct frame_info *this_frame)
Definition: frame.c:2535
long long LONGEST
Definition: common-types.h:52
#define wordsize
void add_setshow_boolean_cmd(const char *name, enum command_class theclass, int *var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_sfunc_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
Definition: cli-decode.c:541
struct target_desc * tdesc_powerpc_750
Definition: powerpc-750.c:8
void set_gdbarch_print_insn(struct gdbarch *gdbarch, gdbarch_print_insn_ftype print_insn)
Definition: gdbarch.c:3067
static int ppc_vsx_support_p(struct gdbarch *gdbarch)
Definition: rs6000-tdep.c:223
#define IS_SPE_PSEUDOREG(tdep, regnum)
Definition: rs6000-tdep.c:87
struct type * builtin_float
Definition: gdbtypes.h:1490
void dwarf2_frame_set_adjust_regnum(struct gdbarch *gdbarch, int(*adjust_regnum)(struct gdbarch *, int, int))
Definition: dwarf2-frame.c:833
void regcache_raw_write(struct regcache *regcache, int regnum, const gdb_byte *buf)
Definition: regcache.c:885
#define PPC_LK(insn)
Definition: rs6000-tdep.c:3682
const ULONGEST const LONGEST len
Definition: target.h:309
void simple_displaced_step_free_closure(struct gdbarch *gdbarch, struct displaced_step_closure *closure)
Definition: arch-utils.c:64
static enum register_status dfp_pseudo_register_read(struct gdbarch *gdbarch, struct regcache *regcache, int reg_nr, gdb_byte *buffer)
Definition: rs6000-tdep.c:2666
#define IS_DFP_PSEUDOREG(tdep, regnum)
Definition: rs6000-tdep.c:92
static int rs6000_register_sim_regno(struct gdbarch *gdbarch, int reg)
Definition: rs6000-tdep.c:356
static int rs6000_epilogue_frame_sniffer(const struct frame_unwind *self, struct frame_info *this_frame, void **this_prologue_cache)
Definition: rs6000-tdep.c:3428
static void rs6000_epilogue_frame_this_id(struct frame_info *this_frame, void **this_cache, struct frame_id *this_id)
Definition: rs6000-tdep.c:3398