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/tmp/gdb-7.10/gdb/i386-tdep.c
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1 /* Intel 386 target-dependent stuff.
2 
3  Copyright (C) 1988-2015 Free Software Foundation, Inc.
4 
5  This file is part of GDB.
6 
7  This program is free software; you can redistribute it and/or modify
8  it under the terms of the GNU General Public License as published by
9  the Free Software Foundation; either version 3 of the License, or
10  (at your option) any later version.
11 
12  This program is distributed in the hope that it will be useful,
13  but WITHOUT ANY WARRANTY; without even the implied warranty of
14  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  GNU General Public License for more details.
16 
17  You should have received a copy of the GNU General Public License
18  along with this program. If not, see <http://www.gnu.org/licenses/>. */
19 
20 #include "defs.h"
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
23 #include "command.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
26 #include "doublest.h"
27 #include "frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
30 #include "inferior.h"
31 #include "infrun.h"
32 #include "gdbcmd.h"
33 #include "gdbcore.h"
34 #include "gdbtypes.h"
35 #include "objfiles.h"
36 #include "osabi.h"
37 #include "regcache.h"
38 #include "reggroups.h"
39 #include "regset.h"
40 #include "symfile.h"
41 #include "symtab.h"
42 #include "target.h"
43 #include "value.h"
44 #include "dis-asm.h"
45 #include "disasm.h"
46 #include "remote.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "x86-xstate.h"
50 
51 #include "record.h"
52 #include "record-full.h"
53 #include "features/i386/i386.c"
54 #include "features/i386/i386-avx.c"
55 #include "features/i386/i386-mpx.c"
57 #include "features/i386/i386-mmx.c"
58 
59 #include "ax.h"
60 #include "ax-gdb.h"
61 
62 #include "stap-probe.h"
63 #include "user-regs.h"
64 #include "cli/cli-utils.h"
65 #include "expression.h"
66 #include "parser-defs.h"
67 #include <ctype.h>
68 
69 /* Register names. */
70 
71 static const char *i386_register_names[] =
72 {
73  "eax", "ecx", "edx", "ebx",
74  "esp", "ebp", "esi", "edi",
75  "eip", "eflags", "cs", "ss",
76  "ds", "es", "fs", "gs",
77  "st0", "st1", "st2", "st3",
78  "st4", "st5", "st6", "st7",
79  "fctrl", "fstat", "ftag", "fiseg",
80  "fioff", "foseg", "fooff", "fop",
81  "xmm0", "xmm1", "xmm2", "xmm3",
82  "xmm4", "xmm5", "xmm6", "xmm7",
83  "mxcsr"
84 };
85 
86 static const char *i386_zmm_names[] =
87 {
88  "zmm0", "zmm1", "zmm2", "zmm3",
89  "zmm4", "zmm5", "zmm6", "zmm7"
90 };
91 
92 static const char *i386_zmmh_names[] =
93 {
94  "zmm0h", "zmm1h", "zmm2h", "zmm3h",
95  "zmm4h", "zmm5h", "zmm6h", "zmm7h"
96 };
97 
98 static const char *i386_k_names[] =
99 {
100  "k0", "k1", "k2", "k3",
101  "k4", "k5", "k6", "k7"
102 };
103 
104 static const char *i386_ymm_names[] =
105 {
106  "ymm0", "ymm1", "ymm2", "ymm3",
107  "ymm4", "ymm5", "ymm6", "ymm7",
108 };
109 
110 static const char *i386_ymmh_names[] =
111 {
112  "ymm0h", "ymm1h", "ymm2h", "ymm3h",
113  "ymm4h", "ymm5h", "ymm6h", "ymm7h",
114 };
115 
116 static const char *i386_mpx_names[] =
117 {
118  "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
119 };
120 
121 /* Register names for MPX pseudo-registers. */
122 
123 static const char *i386_bnd_names[] =
124 {
125  "bnd0", "bnd1", "bnd2", "bnd3"
126 };
127 
128 /* Register names for MMX pseudo-registers. */
129 
130 static const char *i386_mmx_names[] =
131 {
132  "mm0", "mm1", "mm2", "mm3",
133  "mm4", "mm5", "mm6", "mm7"
134 };
135 
136 /* Register names for byte pseudo-registers. */
137 
138 static const char *i386_byte_names[] =
139 {
140  "al", "cl", "dl", "bl",
141  "ah", "ch", "dh", "bh"
142 };
143 
144 /* Register names for word pseudo-registers. */
145 
146 static const char *i386_word_names[] =
147 {
148  "ax", "cx", "dx", "bx",
149  "", "bp", "si", "di"
150 };
151 
152 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
153  16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
154  we have 16 upper ZMM regs that have to be handled differently. */
155 
156 const int num_lower_zmm_regs = 16;
157 
158 /* MMX register? */
159 
160 static int
161 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
162 {
163  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
164  int mm0_regnum = tdep->mm0_regnum;
165 
166  if (mm0_regnum < 0)
167  return 0;
168 
169  regnum -= mm0_regnum;
170  return regnum >= 0 && regnum < tdep->num_mmx_regs;
171 }
172 
173 /* Byte register? */
174 
175 int
176 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
177 {
178  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
179 
180  regnum -= tdep->al_regnum;
181  return regnum >= 0 && regnum < tdep->num_byte_regs;
182 }
183 
184 /* Word register? */
185 
186 int
187 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
188 {
189  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
190 
191  regnum -= tdep->ax_regnum;
192  return regnum >= 0 && regnum < tdep->num_word_regs;
193 }
194 
195 /* Dword register? */
196 
197 int
198 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
199 {
200  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
201  int eax_regnum = tdep->eax_regnum;
202 
203  if (eax_regnum < 0)
204  return 0;
205 
206  regnum -= eax_regnum;
207  return regnum >= 0 && regnum < tdep->num_dword_regs;
208 }
209 
210 /* AVX512 register? */
211 
212 int
213 i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum)
214 {
215  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
216  int zmm0h_regnum = tdep->zmm0h_regnum;
217 
218  if (zmm0h_regnum < 0)
219  return 0;
220 
221  regnum -= zmm0h_regnum;
222  return regnum >= 0 && regnum < tdep->num_zmm_regs;
223 }
224 
225 int
226 i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum)
227 {
228  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
229  int zmm0_regnum = tdep->zmm0_regnum;
230 
231  if (zmm0_regnum < 0)
232  return 0;
233 
234  regnum -= zmm0_regnum;
235  return regnum >= 0 && regnum < tdep->num_zmm_regs;
236 }
237 
238 int
239 i386_k_regnum_p (struct gdbarch *gdbarch, int regnum)
240 {
241  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
242  int k0_regnum = tdep->k0_regnum;
243 
244  if (k0_regnum < 0)
245  return 0;
246 
247  regnum -= k0_regnum;
248  return regnum >= 0 && regnum < I387_NUM_K_REGS;
249 }
250 
251 static int
252 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
253 {
254  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
255  int ymm0h_regnum = tdep->ymm0h_regnum;
256 
257  if (ymm0h_regnum < 0)
258  return 0;
259 
260  regnum -= ymm0h_regnum;
261  return regnum >= 0 && regnum < tdep->num_ymm_regs;
262 }
263 
264 /* AVX register? */
265 
266 int
267 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
268 {
269  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
270  int ymm0_regnum = tdep->ymm0_regnum;
271 
272  if (ymm0_regnum < 0)
273  return 0;
274 
275  regnum -= ymm0_regnum;
276  return regnum >= 0 && regnum < tdep->num_ymm_regs;
277 }
278 
279 static int
280 i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
281 {
282  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
283  int ymm16h_regnum = tdep->ymm16h_regnum;
284 
285  if (ymm16h_regnum < 0)
286  return 0;
287 
288  regnum -= ymm16h_regnum;
289  return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
290 }
291 
292 int
293 i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
294 {
295  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
296  int ymm16_regnum = tdep->ymm16_regnum;
297 
298  if (ymm16_regnum < 0)
299  return 0;
300 
301  regnum -= ymm16_regnum;
302  return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
303 }
304 
305 /* BND register? */
306 
307 int
308 i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum)
309 {
310  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
311  int bnd0_regnum = tdep->bnd0_regnum;
312 
313  if (bnd0_regnum < 0)
314  return 0;
315 
316  regnum -= bnd0_regnum;
317  return regnum >= 0 && regnum < I387_NUM_BND_REGS;
318 }
319 
320 /* SSE register? */
321 
322 int
323 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
324 {
325  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
326  int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
327 
328  if (num_xmm_regs == 0)
329  return 0;
330 
331  regnum -= I387_XMM0_REGNUM (tdep);
332  return regnum >= 0 && regnum < num_xmm_regs;
333 }
334 
335 /* XMM_512 register? */
336 
337 int
338 i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
339 {
340  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
342 
343  if (num_xmm_avx512_regs == 0)
344  return 0;
345 
346  regnum -= I387_XMM16_REGNUM (tdep);
347  return regnum >= 0 && regnum < num_xmm_avx512_regs;
348 }
349 
350 static int
351 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
352 {
353  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
354 
355  if (I387_NUM_XMM_REGS (tdep) == 0)
356  return 0;
357 
358  return (regnum == I387_MXCSR_REGNUM (tdep));
359 }
360 
361 /* FP register? */
362 
363 int
364 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
365 {
366  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
367 
368  if (I387_ST0_REGNUM (tdep) < 0)
369  return 0;
370 
371  return (I387_ST0_REGNUM (tdep) <= regnum
372  && regnum < I387_FCTRL_REGNUM (tdep));
373 }
374 
375 int
376 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
377 {
378  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
379 
380  if (I387_ST0_REGNUM (tdep) < 0)
381  return 0;
382 
383  return (I387_FCTRL_REGNUM (tdep) <= regnum
384  && regnum < I387_XMM0_REGNUM (tdep));
385 }
386 
387 /* BNDr (raw) register? */
388 
389 static int
390 i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum)
391 {
392  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
393 
394  if (I387_BND0R_REGNUM (tdep) < 0)
395  return 0;
396 
397  regnum -= tdep->bnd0r_regnum;
398  return regnum >= 0 && regnum < I387_NUM_BND_REGS;
399 }
400 
401 /* BND control register? */
402 
403 static int
404 i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum)
405 {
406  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
407 
408  if (I387_BNDCFGU_REGNUM (tdep) < 0)
409  return 0;
410 
411  regnum -= I387_BNDCFGU_REGNUM (tdep);
412  return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS;
413 }
414 
415 /* Return the name of register REGNUM, or the empty string if it is
416  an anonymous register. */
417 
418 static const char *
419 i386_register_name (struct gdbarch *gdbarch, int regnum)
420 {
421  /* Hide the upper YMM registers. */
422  if (i386_ymmh_regnum_p (gdbarch, regnum))
423  return "";
424 
425  /* Hide the upper YMM16-31 registers. */
426  if (i386_ymmh_avx512_regnum_p (gdbarch, regnum))
427  return "";
428 
429  /* Hide the upper ZMM registers. */
430  if (i386_zmmh_regnum_p (gdbarch, regnum))
431  return "";
432 
433  return tdesc_register_name (gdbarch, regnum);
434 }
435 
436 /* Return the name of register REGNUM. */
437 
438 const char *
439 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
440 {
441  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
442  if (i386_bnd_regnum_p (gdbarch, regnum))
443  return i386_bnd_names[regnum - tdep->bnd0_regnum];
444  if (i386_mmx_regnum_p (gdbarch, regnum))
445  return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
446  else if (i386_ymm_regnum_p (gdbarch, regnum))
447  return i386_ymm_names[regnum - tdep->ymm0_regnum];
448  else if (i386_zmm_regnum_p (gdbarch, regnum))
449  return i386_zmm_names[regnum - tdep->zmm0_regnum];
450  else if (i386_byte_regnum_p (gdbarch, regnum))
451  return i386_byte_names[regnum - tdep->al_regnum];
452  else if (i386_word_regnum_p (gdbarch, regnum))
453  return i386_word_names[regnum - tdep->ax_regnum];
454 
455  internal_error (__FILE__, __LINE__, _("invalid regnum"));
456 }
457 
458 /* Convert a dbx register number REG to the appropriate register
459  number used by GDB. */
460 
461 static int
462 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
463 {
464  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
465 
466  /* This implements what GCC calls the "default" register map
467  (dbx_register_map[]). */
468 
469  if (reg >= 0 && reg <= 7)
470  {
471  /* General-purpose registers. The debug info calls %ebp
472  register 4, and %esp register 5. */
473  if (reg == 4)
474  return 5;
475  else if (reg == 5)
476  return 4;
477  else return reg;
478  }
479  else if (reg >= 12 && reg <= 19)
480  {
481  /* Floating-point registers. */
482  return reg - 12 + I387_ST0_REGNUM (tdep);
483  }
484  else if (reg >= 21 && reg <= 28)
485  {
486  /* SSE registers. */
487  int ymm0_regnum = tdep->ymm0_regnum;
488 
489  if (ymm0_regnum >= 0
490  && i386_xmm_regnum_p (gdbarch, reg))
491  return reg - 21 + ymm0_regnum;
492  else
493  return reg - 21 + I387_XMM0_REGNUM (tdep);
494  }
495  else if (reg >= 29 && reg <= 36)
496  {
497  /* MMX registers. */
498  return reg - 29 + I387_MM0_REGNUM (tdep);
499  }
500 
501  /* This will hopefully provoke a warning. */
502  return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
503 }
504 
505 /* Convert SVR4 register number REG to the appropriate register number
506  used by GDB. */
507 
508 static int
509 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
510 {
511  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
512 
513  /* This implements the GCC register map that tries to be compatible
514  with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
515 
516  /* The SVR4 register numbering includes %eip and %eflags, and
517  numbers the floating point registers differently. */
518  if (reg >= 0 && reg <= 9)
519  {
520  /* General-purpose registers. */
521  return reg;
522  }
523  else if (reg >= 11 && reg <= 18)
524  {
525  /* Floating-point registers. */
526  return reg - 11 + I387_ST0_REGNUM (tdep);
527  }
528  else if (reg >= 21 && reg <= 36)
529  {
530  /* The SSE and MMX registers have the same numbers as with dbx. */
531  return i386_dbx_reg_to_regnum (gdbarch, reg);
532  }
533 
534  switch (reg)
535  {
536  case 37: return I387_FCTRL_REGNUM (tdep);
537  case 38: return I387_FSTAT_REGNUM (tdep);
538  case 39: return I387_MXCSR_REGNUM (tdep);
539  case 40: return I386_ES_REGNUM;
540  case 41: return I386_CS_REGNUM;
541  case 42: return I386_SS_REGNUM;
542  case 43: return I386_DS_REGNUM;
543  case 44: return I386_FS_REGNUM;
544  case 45: return I386_GS_REGNUM;
545  }
546 
547  /* This will hopefully provoke a warning. */
548  return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
549 }
550 
551 
552 
553 /* This is the variable that is set with "set disassembly-flavor", and
554  its legitimate values. */
555 static const char att_flavor[] = "att";
556 static const char intel_flavor[] = "intel";
557 static const char *const valid_flavors[] =
558 {
559  att_flavor,
560  intel_flavor,
561  NULL
562 };
563 static const char *disassembly_flavor = att_flavor;
564 
565 
566 /* Use the program counter to determine the contents and size of a
567  breakpoint instruction. Return a pointer to a string of bytes that
568  encode a breakpoint instruction, store the length of the string in
569  *LEN and optionally adjust *PC to point to the correct memory
570  location for inserting the breakpoint.
571 
572  On the i386 we have a single breakpoint that fits in a single byte
573  and can be inserted anywhere.
574 
575  This function is 64-bit safe. */
576 
577 static const gdb_byte *
578 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
579 {
580  static gdb_byte break_insn[] = { 0xcc }; /* int 3 */
581 
582  *len = sizeof (break_insn);
583  return break_insn;
584 }
585 
586 /* Displaced instruction handling. */
587 
588 /* Skip the legacy instruction prefixes in INSN.
589  Not all prefixes are valid for any particular insn
590  but we needn't care, the insn will fault if it's invalid.
591  The result is a pointer to the first opcode byte,
592  or NULL if we run off the end of the buffer. */
593 
594 static gdb_byte *
595 i386_skip_prefixes (gdb_byte *insn, size_t max_len)
596 {
597  gdb_byte *end = insn + max_len;
598 
599  while (insn < end)
600  {
601  switch (*insn)
602  {
603  case DATA_PREFIX_OPCODE:
604  case ADDR_PREFIX_OPCODE:
605  case CS_PREFIX_OPCODE:
606  case DS_PREFIX_OPCODE:
607  case ES_PREFIX_OPCODE:
608  case FS_PREFIX_OPCODE:
609  case GS_PREFIX_OPCODE:
610  case SS_PREFIX_OPCODE:
611  case LOCK_PREFIX_OPCODE:
612  case REPE_PREFIX_OPCODE:
613  case REPNE_PREFIX_OPCODE:
614  ++insn;
615  continue;
616  default:
617  return insn;
618  }
619  }
620 
621  return NULL;
622 }
623 
624 static int
626 {
627  /* jmp far (absolute address in operand). */
628  if (insn[0] == 0xea)
629  return 1;
630 
631  if (insn[0] == 0xff)
632  {
633  /* jump near, absolute indirect (/4). */
634  if ((insn[1] & 0x38) == 0x20)
635  return 1;
636 
637  /* jump far, absolute indirect (/5). */
638  if ((insn[1] & 0x38) == 0x28)
639  return 1;
640  }
641 
642  return 0;
643 }
644 
645 /* Return non-zero if INSN is a jump, zero otherwise. */
646 
647 static int
648 i386_jmp_p (const gdb_byte *insn)
649 {
650  /* jump short, relative. */
651  if (insn[0] == 0xeb)
652  return 1;
653 
654  /* jump near, relative. */
655  if (insn[0] == 0xe9)
656  return 1;
657 
658  return i386_absolute_jmp_p (insn);
659 }
660 
661 static int
663 {
664  /* call far, absolute. */
665  if (insn[0] == 0x9a)
666  return 1;
667 
668  if (insn[0] == 0xff)
669  {
670  /* Call near, absolute indirect (/2). */
671  if ((insn[1] & 0x38) == 0x10)
672  return 1;
673 
674  /* Call far, absolute indirect (/3). */
675  if ((insn[1] & 0x38) == 0x18)
676  return 1;
677  }
678 
679  return 0;
680 }
681 
682 static int
683 i386_ret_p (const gdb_byte *insn)
684 {
685  switch (insn[0])
686  {
687  case 0xc2: /* ret near, pop N bytes. */
688  case 0xc3: /* ret near */
689  case 0xca: /* ret far, pop N bytes. */
690  case 0xcb: /* ret far */
691  case 0xcf: /* iret */
692  return 1;
693 
694  default:
695  return 0;
696  }
697 }
698 
699 static int
700 i386_call_p (const gdb_byte *insn)
701 {
702  if (i386_absolute_call_p (insn))
703  return 1;
704 
705  /* call near, relative. */
706  if (insn[0] == 0xe8)
707  return 1;
708 
709  return 0;
710 }
711 
712 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
713  length in bytes. Otherwise, return zero. */
714 
715 static int
716 i386_syscall_p (const gdb_byte *insn, int *lengthp)
717 {
718  /* Is it 'int $0x80'? */
719  if ((insn[0] == 0xcd && insn[1] == 0x80)
720  /* Or is it 'sysenter'? */
721  || (insn[0] == 0x0f && insn[1] == 0x34)
722  /* Or is it 'syscall'? */
723  || (insn[0] == 0x0f && insn[1] == 0x05))
724  {
725  *lengthp = 2;
726  return 1;
727  }
728 
729  return 0;
730 }
731 
732 /* The gdbarch insn_is_call method. */
733 
734 static int
735 i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
736 {
737  gdb_byte buf[I386_MAX_INSN_LEN], *insn;
738 
739  read_code (addr, buf, I386_MAX_INSN_LEN);
741 
742  return i386_call_p (insn);
743 }
744 
745 /* The gdbarch insn_is_ret method. */
746 
747 static int
748 i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
749 {
750  gdb_byte buf[I386_MAX_INSN_LEN], *insn;
751 
752  read_code (addr, buf, I386_MAX_INSN_LEN);
754 
755  return i386_ret_p (insn);
756 }
757 
758 /* The gdbarch insn_is_jump method. */
759 
760 static int
761 i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
762 {
763  gdb_byte buf[I386_MAX_INSN_LEN], *insn;
764 
765  read_code (addr, buf, I386_MAX_INSN_LEN);
767 
768  return i386_jmp_p (insn);
769 }
770 
771 /* Some kernels may run one past a syscall insn, so we have to cope.
772  Otherwise this is just simple_displaced_step_copy_insn. */
773 
774 struct displaced_step_closure *
775 i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
777  struct regcache *regs)
778 {
779  size_t len = gdbarch_max_insn_length (gdbarch);
780  gdb_byte *buf = xmalloc (len);
781 
782  read_memory (from, buf, len);
783 
784  /* GDB may get control back after the insn after the syscall.
785  Presumably this is a kernel bug.
786  If this is a syscall, make sure there's a nop afterwards. */
787  {
788  int syscall_length;
789  gdb_byte *insn;
790 
791  insn = i386_skip_prefixes (buf, len);
792  if (insn != NULL && i386_syscall_p (insn, &syscall_length))
793  insn[syscall_length] = NOP_OPCODE;
794  }
795 
796  write_memory (to, buf, len);
797 
798  if (debug_displaced)
799  {
800  fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
801  paddress (gdbarch, from), paddress (gdbarch, to));
803  }
804 
805  return (struct displaced_step_closure *) buf;
806 }
807 
808 /* Fix up the state of registers and memory after having single-stepped
809  a displaced instruction. */
810 
811 void
812 i386_displaced_step_fixup (struct gdbarch *gdbarch,
813  struct displaced_step_closure *closure,
815  struct regcache *regs)
816 {
817  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
818 
819  /* The offset we applied to the instruction's address.
820  This could well be negative (when viewed as a signed 32-bit
821  value), but ULONGEST won't reflect that, so take care when
822  applying it. */
823  ULONGEST insn_offset = to - from;
824 
825  /* Since we use simple_displaced_step_copy_insn, our closure is a
826  copy of the instruction. */
827  gdb_byte *insn = (gdb_byte *) closure;
828  /* The start of the insn, needed in case we see some prefixes. */
829  gdb_byte *insn_start = insn;
830 
831  if (debug_displaced)
833  "displaced: fixup (%s, %s), "
834  "insn = 0x%02x 0x%02x ...\n",
835  paddress (gdbarch, from), paddress (gdbarch, to),
836  insn[0], insn[1]);
837 
838  /* The list of issues to contend with here is taken from
839  resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
840  Yay for Free Software! */
841 
842  /* Relocate the %eip, if necessary. */
843 
844  /* The instruction recognizers we use assume any leading prefixes
845  have been skipped. */
846  {
847  /* This is the size of the buffer in closure. */
848  size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
849  gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
850  /* If there are too many prefixes, just ignore the insn.
851  It will fault when run. */
852  if (opcode != NULL)
853  insn = opcode;
854  }
855 
856  /* Except in the case of absolute or indirect jump or call
857  instructions, or a return instruction, the new eip is relative to
858  the displaced instruction; make it relative. Well, signal
859  handler returns don't need relocation either, but we use the
860  value of %eip to recognize those; see below. */
861  if (! i386_absolute_jmp_p (insn)
862  && ! i386_absolute_call_p (insn)
863  && ! i386_ret_p (insn))
864  {
865  ULONGEST orig_eip;
866  int insn_len;
867 
869 
870  /* A signal trampoline system call changes the %eip, resuming
871  execution of the main program after the signal handler has
872  returned. That makes them like 'return' instructions; we
873  shouldn't relocate %eip.
874 
875  But most system calls don't, and we do need to relocate %eip.
876 
877  Our heuristic for distinguishing these cases: if stepping
878  over the system call instruction left control directly after
879  the instruction, the we relocate --- control almost certainly
880  doesn't belong in the displaced copy. Otherwise, we assume
881  the instruction has put control where it belongs, and leave
882  it unrelocated. Goodness help us if there are PC-relative
883  system calls. */
884  if (i386_syscall_p (insn, &insn_len)
885  && orig_eip != to + (insn - insn_start) + insn_len
886  /* GDB can get control back after the insn after the syscall.
887  Presumably this is a kernel bug.
888  i386_displaced_step_copy_insn ensures its a nop,
889  we add one to the length for it. */
890  && orig_eip != to + (insn - insn_start) + insn_len + 1)
891  {
892  if (debug_displaced)
894  "displaced: syscall changed %%eip; "
895  "not relocating\n");
896  }
897  else
898  {
899  ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL;
900 
901  /* If we just stepped over a breakpoint insn, we don't backup
902  the pc on purpose; this is to match behaviour without
903  stepping. */
904 
906 
907  if (debug_displaced)
909  "displaced: "
910  "relocated %%eip from %s to %s\n",
911  paddress (gdbarch, orig_eip),
912  paddress (gdbarch, eip));
913  }
914  }
915 
916  /* If the instruction was PUSHFL, then the TF bit will be set in the
917  pushed value, and should be cleared. We'll leave this for later,
918  since GDB already messes up the TF flag when stepping over a
919  pushfl. */
920 
921  /* If the instruction was a call, the return address now atop the
922  stack is the address following the copied instruction. We need
923  to make it the address following the original instruction. */
924  if (i386_call_p (insn))
925  {
926  ULONGEST esp;
927  ULONGEST retaddr;
928  const ULONGEST retaddr_len = 4;
929 
931  retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
932  retaddr = (retaddr - insn_offset) & 0xffffffffUL;
933  write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
934 
935  if (debug_displaced)
937  "displaced: relocated return addr at %s to %s\n",
938  paddress (gdbarch, esp),
939  paddress (gdbarch, retaddr));
940  }
941 }
942 
943 static void
945 {
946  target_write_memory (*to, buf, len);
947  *to += len;
948 }
949 
950 static void
951 i386_relocate_instruction (struct gdbarch *gdbarch,
952  CORE_ADDR *to, CORE_ADDR oldloc)
953 {
954  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
956  int offset = 0, rel32, newrel;
957  int insn_length;
958  gdb_byte *insn = buf;
959 
960  read_memory (oldloc, buf, I386_MAX_INSN_LEN);
961 
962  insn_length = gdb_buffered_insn_length (gdbarch, insn,
963  I386_MAX_INSN_LEN, oldloc);
964 
965  /* Get past the prefixes. */
966  insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
967 
968  /* Adjust calls with 32-bit relative addresses as push/jump, with
969  the address pushed being the location where the original call in
970  the user program would return to. */
971  if (insn[0] == 0xe8)
972  {
973  gdb_byte push_buf[16];
974  unsigned int ret_addr;
975 
976  /* Where "ret" in the original code will return to. */
977  ret_addr = oldloc + insn_length;
978  push_buf[0] = 0x68; /* pushq $... */
979  store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
980  /* Push the push. */
981  append_insns (to, 5, push_buf);
982 
983  /* Convert the relative call to a relative jump. */
984  insn[0] = 0xe9;
985 
986  /* Adjust the destination offset. */
987  rel32 = extract_signed_integer (insn + 1, 4, byte_order);
988  newrel = (oldloc - *to) + rel32;
989  store_signed_integer (insn + 1, 4, byte_order, newrel);
990 
991  if (debug_displaced)
993  "Adjusted insn rel32=%s at %s to"
994  " rel32=%s at %s\n",
995  hex_string (rel32), paddress (gdbarch, oldloc),
996  hex_string (newrel), paddress (gdbarch, *to));
997 
998  /* Write the adjusted jump into its displaced location. */
999  append_insns (to, 5, insn);
1000  return;
1001  }
1002 
1003  /* Adjust jumps with 32-bit relative addresses. Calls are already
1004  handled above. */
1005  if (insn[0] == 0xe9)
1006  offset = 1;
1007  /* Adjust conditional jumps. */
1008  else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1009  offset = 2;
1010 
1011  if (offset)
1012  {
1013  rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1014  newrel = (oldloc - *to) + rel32;
1015  store_signed_integer (insn + offset, 4, byte_order, newrel);
1016  if (debug_displaced)
1018  "Adjusted insn rel32=%s at %s to"
1019  " rel32=%s at %s\n",
1020  hex_string (rel32), paddress (gdbarch, oldloc),
1021  hex_string (newrel), paddress (gdbarch, *to));
1022  }
1023 
1024  /* Write the adjusted instructions into their displaced
1025  location. */
1026  append_insns (to, insn_length, buf);
1027 }
1028 
1029 
1030 #ifdef I386_REGNO_TO_SYMMETRY
1031 #error "The Sequent Symmetry is no longer supported."
1032 #endif
1033 
1034 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1035  and %esp "belong" to the calling function. Therefore these
1036  registers should be saved if they're going to be modified. */
1037 
1038 /* The maximum number of saved registers. This should include all
1039  registers mentioned above, and %eip. */
1040 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1041 
1043 {
1044  /* Base address. */
1046  int base_p;
1049 
1050  /* Saved registers. */
1055 
1056  /* Stack space reserved for local variables. */
1057  long locals;
1058 };
1059 
1060 /* Allocate and initialize a frame cache. */
1061 
1062 static struct i386_frame_cache *
1064 {
1065  struct i386_frame_cache *cache;
1066  int i;
1067 
1068  cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
1069 
1070  /* Base address. */
1071  cache->base_p = 0;
1072  cache->base = 0;
1073  cache->sp_offset = -4;
1074  cache->pc = 0;
1075 
1076  /* Saved registers. We initialize these to -1 since zero is a valid
1077  offset (that's where %ebp is supposed to be stored). */
1078  for (i = 0; i < I386_NUM_SAVED_REGS; i++)
1079  cache->saved_regs[i] = -1;
1080  cache->saved_sp = 0;
1081  cache->saved_sp_reg = -1;
1082  cache->pc_in_eax = 0;
1083 
1084  /* Frameless until proven otherwise. */
1085  cache->locals = -1;
1086 
1087  return cache;
1088 }
1089 
1090 /* If the instruction at PC is a jump, return the address of its
1091  target. Otherwise, return PC. */
1092 
1093 static CORE_ADDR
1094 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
1095 {
1096  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1097  gdb_byte op;
1098  long delta = 0;
1099  int data16 = 0;
1100 
1101  if (target_read_code (pc, &op, 1))
1102  return pc;
1103 
1104  if (op == 0x66)
1105  {
1106  data16 = 1;
1107 
1108  op = read_code_unsigned_integer (pc + 1, 1, byte_order);
1109  }
1110 
1111  switch (op)
1112  {
1113  case 0xe9:
1114  /* Relative jump: if data16 == 0, disp32, else disp16. */
1115  if (data16)
1116  {
1117  delta = read_memory_integer (pc + 2, 2, byte_order);
1118 
1119  /* Include the size of the jmp instruction (including the
1120  0x66 prefix). */
1121  delta += 4;
1122  }
1123  else
1124  {
1125  delta = read_memory_integer (pc + 1, 4, byte_order);
1126 
1127  /* Include the size of the jmp instruction. */
1128  delta += 5;
1129  }
1130  break;
1131  case 0xeb:
1132  /* Relative jump, disp8 (ignore data16). */
1133  delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
1134 
1135  delta += data16 + 2;
1136  break;
1137  }
1138 
1139  return pc + delta;
1140 }
1141 
1142 /* Check whether PC points at a prologue for a function returning a
1143  structure or union. If so, it updates CACHE and returns the
1144  address of the first instruction after the code sequence that
1145  removes the "hidden" argument from the stack or CURRENT_PC,
1146  whichever is smaller. Otherwise, return PC. */
1147 
1148 static CORE_ADDR
1150  struct i386_frame_cache *cache)
1151 {
1152  /* Functions that return a structure or union start with:
1153 
1154  popl %eax 0x58
1155  xchgl %eax, (%esp) 0x87 0x04 0x24
1156  or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1157 
1158  (the System V compiler puts out the second `xchg' instruction,
1159  and the assembler doesn't try to optimize it, so the 'sib' form
1160  gets generated). This sequence is used to get the address of the
1161  return buffer for a function that returns a structure. */
1162  static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
1163  static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
1164  gdb_byte buf[4];
1165  gdb_byte op;
1166 
1167  if (current_pc <= pc)
1168  return pc;
1169 
1170  if (target_read_code (pc, &op, 1))
1171  return pc;
1172 
1173  if (op != 0x58) /* popl %eax */
1174  return pc;
1175 
1176  if (target_read_code (pc + 1, buf, 4))
1177  return pc;
1178 
1179  if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
1180  return pc;
1181 
1182  if (current_pc == pc)
1183  {
1184  cache->sp_offset += 4;
1185  return current_pc;
1186  }
1187 
1188  if (current_pc == pc + 1)
1189  {
1190  cache->pc_in_eax = 1;
1191  return current_pc;
1192  }
1193 
1194  if (buf[1] == proto1[1])
1195  return pc + 4;
1196  else
1197  return pc + 5;
1198 }
1199 
1200 static CORE_ADDR
1202 {
1203  /* A function may start with
1204 
1205  pushl constant
1206  call _probe
1207  addl $4, %esp
1208 
1209  followed by
1210 
1211  pushl %ebp
1212 
1213  etc. */
1214  gdb_byte buf[8];
1215  gdb_byte op;
1216 
1217  if (target_read_code (pc, &op, 1))
1218  return pc;
1219 
1220  if (op == 0x68 || op == 0x6a)
1221  {
1222  int delta;
1223 
1224  /* Skip past the `pushl' instruction; it has either a one-byte or a
1225  four-byte operand, depending on the opcode. */
1226  if (op == 0x68)
1227  delta = 5;
1228  else
1229  delta = 2;
1230 
1231  /* Read the following 8 bytes, which should be `call _probe' (6
1232  bytes) followed by `addl $4,%esp' (2 bytes). */
1233  read_memory (pc + delta, buf, sizeof (buf));
1234  if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
1235  pc += delta + sizeof (buf);
1236  }
1237 
1238  return pc;
1239 }
1240 
1241 /* GCC 4.1 and later, can put code in the prologue to realign the
1242  stack pointer. Check whether PC points to such code, and update
1243  CACHE accordingly. Return the first instruction after the code
1244  sequence or CURRENT_PC, whichever is smaller. If we don't
1245  recognize the code, return PC. */
1246 
1247 static CORE_ADDR
1249  struct i386_frame_cache *cache)
1250 {
1251  /* There are 2 code sequences to re-align stack before the frame
1252  gets set up:
1253 
1254  1. Use a caller-saved saved register:
1255 
1256  leal 4(%esp), %reg
1257  andl $-XXX, %esp
1258  pushl -4(%reg)
1259 
1260  2. Use a callee-saved saved register:
1261 
1262  pushl %reg
1263  leal 8(%esp), %reg
1264  andl $-XXX, %esp
1265  pushl -4(%reg)
1266 
1267  "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1268 
1269  0x83 0xe4 0xf0 andl $-16, %esp
1270  0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1271  */
1272 
1273  gdb_byte buf[14];
1274  int reg;
1275  int offset, offset_and;
1276  static int regnums[8] = {
1277  I386_EAX_REGNUM, /* %eax */
1278  I386_ECX_REGNUM, /* %ecx */
1279  I386_EDX_REGNUM, /* %edx */
1280  I386_EBX_REGNUM, /* %ebx */
1281  I386_ESP_REGNUM, /* %esp */
1282  I386_EBP_REGNUM, /* %ebp */
1283  I386_ESI_REGNUM, /* %esi */
1284  I386_EDI_REGNUM /* %edi */
1285  };
1286 
1287  if (target_read_code (pc, buf, sizeof buf))
1288  return pc;
1289 
1290  /* Check caller-saved saved register. The first instruction has
1291  to be "leal 4(%esp), %reg". */
1292  if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
1293  {
1294  /* MOD must be binary 10 and R/M must be binary 100. */
1295  if ((buf[1] & 0xc7) != 0x44)
1296  return pc;
1297 
1298  /* REG has register number. */
1299  reg = (buf[1] >> 3) & 7;
1300  offset = 4;
1301  }
1302  else
1303  {
1304  /* Check callee-saved saved register. The first instruction
1305  has to be "pushl %reg". */
1306  if ((buf[0] & 0xf8) != 0x50)
1307  return pc;
1308 
1309  /* Get register. */
1310  reg = buf[0] & 0x7;
1311 
1312  /* The next instruction has to be "leal 8(%esp), %reg". */
1313  if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
1314  return pc;
1315 
1316  /* MOD must be binary 10 and R/M must be binary 100. */
1317  if ((buf[2] & 0xc7) != 0x44)
1318  return pc;
1319 
1320  /* REG has register number. Registers in pushl and leal have to
1321  be the same. */
1322  if (reg != ((buf[2] >> 3) & 7))
1323  return pc;
1324 
1325  offset = 5;
1326  }
1327 
1328  /* Rigister can't be %esp nor %ebp. */
1329  if (reg == 4 || reg == 5)
1330  return pc;
1331 
1332  /* The next instruction has to be "andl $-XXX, %esp". */
1333  if (buf[offset + 1] != 0xe4
1334  || (buf[offset] != 0x81 && buf[offset] != 0x83))
1335  return pc;
1336 
1337  offset_and = offset;
1338  offset += buf[offset] == 0x81 ? 6 : 3;
1339 
1340  /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1341  0xfc. REG must be binary 110 and MOD must be binary 01. */
1342  if (buf[offset] != 0xff
1343  || buf[offset + 2] != 0xfc
1344  || (buf[offset + 1] & 0xf8) != 0x70)
1345  return pc;
1346 
1347  /* R/M has register. Registers in leal and pushl have to be the
1348  same. */
1349  if (reg != (buf[offset + 1] & 7))
1350  return pc;
1351 
1352  if (current_pc > pc + offset_and)
1353  cache->saved_sp_reg = regnums[reg];
1354 
1355  return min (pc + offset + 3, current_pc);
1356 }
1357 
1358 /* Maximum instruction length we need to handle. */
1359 #define I386_MAX_MATCHED_INSN_LEN 6
1360 
1361 /* Instruction description. */
1363 {
1364  size_t len;
1367 };
1368 
1369 /* Return whether instruction at PC matches PATTERN. */
1370 
1371 static int
1373 {
1374  gdb_byte op;
1375 
1376  if (target_read_code (pc, &op, 1))
1377  return 0;
1378 
1379  if ((op & pattern.mask[0]) == pattern.insn[0])
1380  {
1382  int insn_matched = 1;
1383  size_t i;
1384 
1385  gdb_assert (pattern.len > 1);
1387 
1388  if (target_read_code (pc + 1, buf, pattern.len - 1))
1389  return 0;
1390 
1391  for (i = 1; i < pattern.len; i++)
1392  {
1393  if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i])
1394  insn_matched = 0;
1395  }
1396  return insn_matched;
1397  }
1398  return 0;
1399 }
1400 
1401 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1402  the first instruction description that matches. Otherwise, return
1403  NULL. */
1404 
1405 static struct i386_insn *
1406 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns)
1407 {
1408  struct i386_insn *pattern;
1409 
1410  for (pattern = insn_patterns; pattern->len > 0; pattern++)
1411  {
1412  if (i386_match_pattern (pc, *pattern))
1413  return pattern;
1414  }
1415 
1416  return NULL;
1417 }
1418 
1419 /* Return whether PC points inside a sequence of instructions that
1420  matches INSN_PATTERNS. */
1421 
1422 static int
1423 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns)
1424 {
1425  CORE_ADDR current_pc;
1426  int ix, i;
1427  struct i386_insn *insn;
1428 
1429  insn = i386_match_insn (pc, insn_patterns);
1430  if (insn == NULL)
1431  return 0;
1432 
1433  current_pc = pc;
1434  ix = insn - insn_patterns;
1435  for (i = ix - 1; i >= 0; i--)
1436  {
1437  current_pc -= insn_patterns[i].len;
1438 
1439  if (!i386_match_pattern (current_pc, insn_patterns[i]))
1440  return 0;
1441  }
1442 
1443  current_pc = pc + insn->len;
1444  for (insn = insn_patterns + ix + 1; insn->len > 0; insn++)
1445  {
1446  if (!i386_match_pattern (current_pc, *insn))
1447  return 0;
1448 
1449  current_pc += insn->len;
1450  }
1451 
1452  return 1;
1453 }
1454 
1455 /* Some special instructions that might be migrated by GCC into the
1456  part of the prologue that sets up the new stack frame. Because the
1457  stack frame hasn't been setup yet, no registers have been saved
1458  yet, and only the scratch registers %eax, %ecx and %edx can be
1459  touched. */
1460 
1461 struct i386_insn i386_frame_setup_skip_insns[] =
1462 {
1463  /* Check for `movb imm8, r' and `movl imm32, r'.
1464 
1465  ??? Should we handle 16-bit operand-sizes here? */
1466 
1467  /* `movb imm8, %al' and `movb imm8, %ah' */
1468  /* `movb imm8, %cl' and `movb imm8, %ch' */
1469  { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1470  /* `movb imm8, %dl' and `movb imm8, %dh' */
1471  { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1472  /* `movl imm32, %eax' and `movl imm32, %ecx' */
1473  { 5, { 0xb8 }, { 0xfe } },
1474  /* `movl imm32, %edx' */
1475  { 5, { 0xba }, { 0xff } },
1476 
1477  /* Check for `mov imm32, r32'. Note that there is an alternative
1478  encoding for `mov m32, %eax'.
1479 
1480  ??? Should we handle SIB adressing here?
1481  ??? Should we handle 16-bit operand-sizes here? */
1482 
1483  /* `movl m32, %eax' */
1484  { 5, { 0xa1 }, { 0xff } },
1485  /* `movl m32, %eax' and `mov; m32, %ecx' */
1486  { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1487  /* `movl m32, %edx' */
1488  { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1489 
1490  /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1491  Because of the symmetry, there are actually two ways to encode
1492  these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1493  opcode bytes 0x31 and 0x33 for `xorl'. */
1494 
1495  /* `subl %eax, %eax' */
1496  { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1497  /* `subl %ecx, %ecx' */
1498  { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1499  /* `subl %edx, %edx' */
1500  { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1501  /* `xorl %eax, %eax' */
1502  { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1503  /* `xorl %ecx, %ecx' */
1504  { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1505  /* `xorl %edx, %edx' */
1506  { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1507  { 0 }
1508 };
1509 
1510 
1511 /* Check whether PC points to a no-op instruction. */
1512 static CORE_ADDR
1514 {
1515  gdb_byte op;
1516  int check = 1;
1517 
1518  if (target_read_code (pc, &op, 1))
1519  return pc;
1520 
1521  while (check)
1522  {
1523  check = 0;
1524  /* Ignore `nop' instruction. */
1525  if (op == 0x90)
1526  {
1527  pc += 1;
1528  if (target_read_code (pc, &op, 1))
1529  return pc;
1530  check = 1;
1531  }
1532  /* Ignore no-op instruction `mov %edi, %edi'.
1533  Microsoft system dlls often start with
1534  a `mov %edi,%edi' instruction.
1535  The 5 bytes before the function start are
1536  filled with `nop' instructions.
1537  This pattern can be used for hot-patching:
1538  The `mov %edi, %edi' instruction can be replaced by a
1539  near jump to the location of the 5 `nop' instructions
1540  which can be replaced by a 32-bit jump to anywhere
1541  in the 32-bit address space. */
1542 
1543  else if (op == 0x8b)
1544  {
1545  if (target_read_code (pc + 1, &op, 1))
1546  return pc;
1547 
1548  if (op == 0xff)
1549  {
1550  pc += 2;
1551  if (target_read_code (pc, &op, 1))
1552  return pc;
1553 
1554  check = 1;
1555  }
1556  }
1557  }
1558  return pc;
1559 }
1560 
1561 /* Check whether PC points at a code that sets up a new stack frame.
1562  If so, it updates CACHE and returns the address of the first
1563  instruction after the sequence that sets up the frame or LIMIT,
1564  whichever is smaller. If we don't recognize the code, return PC. */
1565 
1566 static CORE_ADDR
1567 i386_analyze_frame_setup (struct gdbarch *gdbarch,
1568  CORE_ADDR pc, CORE_ADDR limit,
1569  struct i386_frame_cache *cache)
1570 {
1571  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1572  struct i386_insn *insn;
1573  gdb_byte op;
1574  int skip = 0;
1575 
1576  if (limit <= pc)
1577  return limit;
1578 
1579  if (target_read_code (pc, &op, 1))
1580  return pc;
1581 
1582  if (op == 0x55) /* pushl %ebp */
1583  {
1584  /* Take into account that we've executed the `pushl %ebp' that
1585  starts this instruction sequence. */
1586  cache->saved_regs[I386_EBP_REGNUM] = 0;
1587  cache->sp_offset += 4;
1588  pc++;
1589 
1590  /* If that's all, return now. */
1591  if (limit <= pc)
1592  return limit;
1593 
1594  /* Check for some special instructions that might be migrated by
1595  GCC into the prologue and skip them. At this point in the
1596  prologue, code should only touch the scratch registers %eax,
1597  %ecx and %edx, so while the number of posibilities is sheer,
1598  it is limited.
1599 
1600  Make sure we only skip these instructions if we later see the
1601  `movl %esp, %ebp' that actually sets up the frame. */
1602  while (pc + skip < limit)
1603  {
1604  insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
1605  if (insn == NULL)
1606  break;
1607 
1608  skip += insn->len;
1609  }
1610 
1611  /* If that's all, return now. */
1612  if (limit <= pc + skip)
1613  return limit;
1614 
1615  if (target_read_code (pc + skip, &op, 1))
1616  return pc + skip;
1617 
1618  /* The i386 prologue looks like
1619 
1620  push %ebp
1621  mov %esp,%ebp
1622  sub $0x10,%esp
1623 
1624  and a different prologue can be generated for atom.
1625 
1626  push %ebp
1627  lea (%esp),%ebp
1628  lea -0x10(%esp),%esp
1629 
1630  We handle both of them here. */
1631 
1632  switch (op)
1633  {
1634  /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1635  case 0x8b:
1636  if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1637  != 0xec)
1638  return pc;
1639  pc += (skip + 2);
1640  break;
1641  case 0x89:
1642  if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
1643  != 0xe5)
1644  return pc;
1645  pc += (skip + 2);
1646  break;
1647  case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1648  if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order)
1649  != 0x242c)
1650  return pc;
1651  pc += (skip + 3);
1652  break;
1653  default:
1654  return pc;
1655  }
1656 
1657  /* OK, we actually have a frame. We just don't know how large
1658  it is yet. Set its size to zero. We'll adjust it if
1659  necessary. We also now commit to skipping the special
1660  instructions mentioned before. */
1661  cache->locals = 0;
1662 
1663  /* If that's all, return now. */
1664  if (limit <= pc)
1665  return limit;
1666 
1667  /* Check for stack adjustment
1668 
1669  subl $XXX, %esp
1670  or
1671  lea -XXX(%esp),%esp
1672 
1673  NOTE: You can't subtract a 16-bit immediate from a 32-bit
1674  reg, so we don't have to worry about a data16 prefix. */
1675  if (target_read_code (pc, &op, 1))
1676  return pc;
1677  if (op == 0x83)
1678  {
1679  /* `subl' with 8-bit immediate. */
1680  if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1681  /* Some instruction starting with 0x83 other than `subl'. */
1682  return pc;
1683 
1684  /* `subl' with signed 8-bit immediate (though it wouldn't
1685  make sense to be negative). */
1686  cache->locals = read_code_integer (pc + 2, 1, byte_order);
1687  return pc + 3;
1688  }
1689  else if (op == 0x81)
1690  {
1691  /* Maybe it is `subl' with a 32-bit immediate. */
1692  if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
1693  /* Some instruction starting with 0x81 other than `subl'. */
1694  return pc;
1695 
1696  /* It is `subl' with a 32-bit immediate. */
1697  cache->locals = read_code_integer (pc + 2, 4, byte_order);
1698  return pc + 6;
1699  }
1700  else if (op == 0x8d)
1701  {
1702  /* The ModR/M byte is 0x64. */
1703  if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64)
1704  return pc;
1705  /* 'lea' with 8-bit displacement. */
1706  cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order);
1707  return pc + 4;
1708  }
1709  else
1710  {
1711  /* Some instruction other than `subl' nor 'lea'. */
1712  return pc;
1713  }
1714  }
1715  else if (op == 0xc8) /* enter */
1716  {
1717  cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order);
1718  return pc + 4;
1719  }
1720 
1721  return pc;
1722 }
1723 
1724 /* Check whether PC points at code that saves registers on the stack.
1725  If so, it updates CACHE and returns the address of the first
1726  instruction after the register saves or CURRENT_PC, whichever is
1727  smaller. Otherwise, return PC. */
1728 
1729 static CORE_ADDR
1731  struct i386_frame_cache *cache)
1732 {
1733  CORE_ADDR offset = 0;
1734  gdb_byte op;
1735  int i;
1736 
1737  if (cache->locals > 0)
1738  offset -= cache->locals;
1739  for (i = 0; i < 8 && pc < current_pc; i++)
1740  {
1741  if (target_read_code (pc, &op, 1))
1742  return pc;
1743  if (op < 0x50 || op > 0x57)
1744  break;
1745 
1746  offset -= 4;
1747  cache->saved_regs[op - 0x50] = offset;
1748  cache->sp_offset += 4;
1749  pc++;
1750  }
1751 
1752  return pc;
1753 }
1754 
1755 /* Do a full analysis of the prologue at PC and update CACHE
1756  accordingly. Bail out early if CURRENT_PC is reached. Return the
1757  address where the analysis stopped.
1758 
1759  We handle these cases:
1760 
1761  The startup sequence can be at the start of the function, or the
1762  function can start with a branch to startup code at the end.
1763 
1764  %ebp can be set up with either the 'enter' instruction, or "pushl
1765  %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1766  once used in the System V compiler).
1767 
1768  Local space is allocated just below the saved %ebp by either the
1769  'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1770  16-bit unsigned argument for space to allocate, and the 'addl'
1771  instruction could have either a signed byte, or 32-bit immediate.
1772 
1773  Next, the registers used by this function are pushed. With the
1774  System V compiler they will always be in the order: %edi, %esi,
1775  %ebx (and sometimes a harmless bug causes it to also save but not
1776  restore %eax); however, the code below is willing to see the pushes
1777  in any order, and will handle up to 8 of them.
1778 
1779  If the setup sequence is at the end of the function, then the next
1780  instruction will be a branch back to the start. */
1781 
1782 static CORE_ADDR
1783 i386_analyze_prologue (struct gdbarch *gdbarch,
1784  CORE_ADDR pc, CORE_ADDR current_pc,
1785  struct i386_frame_cache *cache)
1786 {
1787  pc = i386_skip_noop (pc);
1788  pc = i386_follow_jump (gdbarch, pc);
1789  pc = i386_analyze_struct_return (pc, current_pc, cache);
1790  pc = i386_skip_probe (pc);
1791  pc = i386_analyze_stack_align (pc, current_pc, cache);
1792  pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
1793  return i386_analyze_register_saves (pc, current_pc, cache);
1794 }
1795 
1796 /* Return PC of first real instruction. */
1797 
1798 static CORE_ADDR
1799 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1800 {
1801  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1802 
1803  static gdb_byte pic_pat[6] =
1804  {
1805  0xe8, 0, 0, 0, 0, /* call 0x0 */
1806  0x5b, /* popl %ebx */
1807  };
1808  struct i386_frame_cache cache;
1809  CORE_ADDR pc;
1810  gdb_byte op;
1811  int i;
1812  CORE_ADDR func_addr;
1813 
1814  if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
1815  {
1816  CORE_ADDR post_prologue_pc
1817  = skip_prologue_using_sal (gdbarch, func_addr);
1818  struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
1819 
1820  /* Clang always emits a line note before the prologue and another
1821  one after. We trust clang to emit usable line notes. */
1822  if (post_prologue_pc
1823  && (cust != NULL
1824  && COMPUNIT_PRODUCER (cust) != NULL
1825  && startswith (COMPUNIT_PRODUCER (cust), "clang ")))
1826  return max (start_pc, post_prologue_pc);
1827  }
1828 
1829  cache.locals = -1;
1830  pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
1831  if (cache.locals < 0)
1832  return start_pc;
1833 
1834  /* Found valid frame setup. */
1835 
1836  /* The native cc on SVR4 in -K PIC mode inserts the following code
1837  to get the address of the global offset table (GOT) into register
1838  %ebx:
1839 
1840  call 0x0
1841  popl %ebx
1842  movl %ebx,x(%ebp) (optional)
1843  addl y,%ebx
1844 
1845  This code is with the rest of the prologue (at the end of the
1846  function), so we have to skip it to get to the first real
1847  instruction at the start of the function. */
1848 
1849  for (i = 0; i < 6; i++)
1850  {
1851  if (target_read_code (pc + i, &op, 1))
1852  return pc;
1853 
1854  if (pic_pat[i] != op)
1855  break;
1856  }
1857  if (i == 6)
1858  {
1859  int delta = 6;
1860 
1861  if (target_read_code (pc + delta, &op, 1))
1862  return pc;
1863 
1864  if (op == 0x89) /* movl %ebx, x(%ebp) */
1865  {
1866  op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order);
1867 
1868  if (op == 0x5d) /* One byte offset from %ebp. */
1869  delta += 3;
1870  else if (op == 0x9d) /* Four byte offset from %ebp. */
1871  delta += 6;
1872  else /* Unexpected instruction. */
1873  delta = 0;
1874 
1875  if (target_read_code (pc + delta, &op, 1))
1876  return pc;
1877  }
1878 
1879  /* addl y,%ebx */
1880  if (delta > 0 && op == 0x81
1881  && read_code_unsigned_integer (pc + delta + 1, 1, byte_order)
1882  == 0xc3)
1883  {
1884  pc += delta + 6;
1885  }
1886  }
1887 
1888  /* If the function starts with a branch (to startup code at the end)
1889  the last instruction should bring us back to the first
1890  instruction of the real code. */
1891  if (i386_follow_jump (gdbarch, start_pc) != start_pc)
1892  pc = i386_follow_jump (gdbarch, pc);
1893 
1894  return pc;
1895 }
1896 
1897 /* Check that the code pointed to by PC corresponds to a call to
1898  __main, skip it if so. Return PC otherwise. */
1899 
1900 CORE_ADDR
1901 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1902 {
1903  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1904  gdb_byte op;
1905 
1906  if (target_read_code (pc, &op, 1))
1907  return pc;
1908  if (op == 0xe8)
1909  {
1910  gdb_byte buf[4];
1911 
1912  if (target_read_code (pc + 1, buf, sizeof buf) == 0)
1913  {
1914  /* Make sure address is computed correctly as a 32bit
1915  integer even if CORE_ADDR is 64 bit wide. */
1916  struct bound_minimal_symbol s;
1917  CORE_ADDR call_dest;
1918 
1919  call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
1920  call_dest = call_dest & 0xffffffffU;
1921  s = lookup_minimal_symbol_by_pc (call_dest);
1922  if (s.minsym != NULL
1923  && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL
1924  && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0)
1925  pc += 5;
1926  }
1927  }
1928 
1929  return pc;
1930 }
1931 
1932 /* This function is 64-bit safe. */
1933 
1934 static CORE_ADDR
1935 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1936 {
1937  gdb_byte buf[8];
1938 
1939  frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1940  return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1941 }
1942 
1943 
1944 /* Normal frames. */
1945 
1946 static void
1947 i386_frame_cache_1 (struct frame_info *this_frame,
1948  struct i386_frame_cache *cache)
1949 {
1950  struct gdbarch *gdbarch = get_frame_arch (this_frame);
1951  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1952  gdb_byte buf[4];
1953  int i;
1954 
1955  cache->pc = get_frame_func (this_frame);
1956 
1957  /* In principle, for normal frames, %ebp holds the frame pointer,
1958  which holds the base address for the current stack frame.
1959  However, for functions that don't need it, the frame pointer is
1960  optional. For these "frameless" functions the frame pointer is
1961  actually the frame pointer of the calling frame. Signal
1962  trampolines are just a special case of a "frameless" function.
1963  They (usually) share their frame pointer with the frame that was
1964  in progress when the signal occurred. */
1965 
1966  get_frame_register (this_frame, I386_EBP_REGNUM, buf);
1967  cache->base = extract_unsigned_integer (buf, 4, byte_order);
1968  if (cache->base == 0)
1969  {
1970  cache->base_p = 1;
1971  return;
1972  }
1973 
1974  /* For normal frames, %eip is stored at 4(%ebp). */
1975  cache->saved_regs[I386_EIP_REGNUM] = 4;
1976 
1977  if (cache->pc != 0)
1978  i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
1979  cache);
1980 
1981  if (cache->locals < 0)
1982  {
1983  /* We didn't find a valid frame, which means that CACHE->base
1984  currently holds the frame pointer for our calling frame. If
1985  we're at the start of a function, or somewhere half-way its
1986  prologue, the function's frame probably hasn't been fully
1987  setup yet. Try to reconstruct the base address for the stack
1988  frame by looking at the stack pointer. For truly "frameless"
1989  functions this might work too. */
1990 
1991  if (cache->saved_sp_reg != -1)
1992  {
1993  /* Saved stack pointer has been saved. */
1994  get_frame_register (this_frame, cache->saved_sp_reg, buf);
1995  cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
1996 
1997  /* We're halfway aligning the stack. */
1998  cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
1999  cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
2000 
2001  /* This will be added back below. */
2002  cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
2003  }
2004  else if (cache->pc != 0
2005  || target_read_code (get_frame_pc (this_frame), buf, 1))
2006  {
2007  /* We're in a known function, but did not find a frame
2008  setup. Assume that the function does not use %ebp.
2009  Alternatively, we may have jumped to an invalid
2010  address; in that case there is definitely no new
2011  frame in %ebp. */
2012  get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2013  cache->base = extract_unsigned_integer (buf, 4, byte_order)
2014  + cache->sp_offset;
2015  }
2016  else
2017  /* We're in an unknown function. We could not find the start
2018  of the function to analyze the prologue; our best option is
2019  to assume a typical frame layout with the caller's %ebp
2020  saved. */
2021  cache->saved_regs[I386_EBP_REGNUM] = 0;
2022  }
2023 
2024  if (cache->saved_sp_reg != -1)
2025  {
2026  /* Saved stack pointer has been saved (but the SAVED_SP_REG
2027  register may be unavailable). */
2028  if (cache->saved_sp == 0
2029  && deprecated_frame_register_read (this_frame,
2030  cache->saved_sp_reg, buf))
2031  cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
2032  }
2033  /* Now that we have the base address for the stack frame we can
2034  calculate the value of %esp in the calling frame. */
2035  else if (cache->saved_sp == 0)
2036  cache->saved_sp = cache->base + 8;
2037 
2038  /* Adjust all the saved registers such that they contain addresses
2039  instead of offsets. */
2040  for (i = 0; i < I386_NUM_SAVED_REGS; i++)
2041  if (cache->saved_regs[i] != -1)
2042  cache->saved_regs[i] += cache->base;
2043 
2044  cache->base_p = 1;
2045 }
2046 
2047 static struct i386_frame_cache *
2048 i386_frame_cache (struct frame_info *this_frame, void **this_cache)
2049 {
2050  struct i386_frame_cache *cache;
2051 
2052  if (*this_cache)
2053  return *this_cache;
2054 
2055  cache = i386_alloc_frame_cache ();
2056  *this_cache = cache;
2057 
2058  TRY
2059  {
2060  i386_frame_cache_1 (this_frame, cache);
2061  }
2062  CATCH (ex, RETURN_MASK_ERROR)
2063  {
2064  if (ex.error != NOT_AVAILABLE_ERROR)
2065  throw_exception (ex);
2066  }
2067  END_CATCH
2068 
2069  return cache;
2070 }
2071 
2072 static void
2073 i386_frame_this_id (struct frame_info *this_frame, void **this_cache,
2074  struct frame_id *this_id)
2075 {
2076  struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2077 
2078  if (!cache->base_p)
2079  (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2080  else if (cache->base == 0)
2081  {
2082  /* This marks the outermost frame. */
2083  }
2084  else
2085  {
2086  /* See the end of i386_push_dummy_call. */
2087  (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2088  }
2089 }
2090 
2091 static enum unwind_stop_reason
2093  void **this_cache)
2094 {
2095  struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2096 
2097  if (!cache->base_p)
2098  return UNWIND_UNAVAILABLE;
2099 
2100  /* This marks the outermost frame. */
2101  if (cache->base == 0)
2102  return UNWIND_OUTERMOST;
2103 
2104  return UNWIND_NO_REASON;
2105 }
2106 
2107 static struct value *
2108 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2109  int regnum)
2110 {
2111  struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2112 
2113  gdb_assert (regnum >= 0);
2114 
2115  /* The System V ABI says that:
2116 
2117  "The flags register contains the system flags, such as the
2118  direction flag and the carry flag. The direction flag must be
2119  set to the forward (that is, zero) direction before entry and
2120  upon exit from a function. Other user flags have no specified
2121  role in the standard calling sequence and are not preserved."
2122 
2123  To guarantee the "upon exit" part of that statement we fake a
2124  saved flags register that has its direction flag cleared.
2125 
2126  Note that GCC doesn't seem to rely on the fact that the direction
2127  flag is cleared after a function return; it always explicitly
2128  clears the flag before operations where it matters.
2129 
2130  FIXME: kettenis/20030316: I'm not quite sure whether this is the
2131  right thing to do. The way we fake the flags register here makes
2132  it impossible to change it. */
2133 
2134  if (regnum == I386_EFLAGS_REGNUM)
2135  {
2136  ULONGEST val;
2137 
2138  val = get_frame_register_unsigned (this_frame, regnum);
2139  val &= ~(1 << 10);
2140  return frame_unwind_got_constant (this_frame, regnum, val);
2141  }
2142 
2143  if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
2144  return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
2145 
2146  if (regnum == I386_ESP_REGNUM
2147  && (cache->saved_sp != 0 || cache->saved_sp_reg != -1))
2148  {
2149  /* If the SP has been saved, but we don't know where, then this
2150  means that SAVED_SP_REG register was found unavailable back
2151  when we built the cache. */
2152  if (cache->saved_sp == 0)
2153  return frame_unwind_got_register (this_frame, regnum,
2154  cache->saved_sp_reg);
2155  else
2156  return frame_unwind_got_constant (this_frame, regnum,
2157  cache->saved_sp);
2158  }
2159 
2160  if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
2161  return frame_unwind_got_memory (this_frame, regnum,
2162  cache->saved_regs[regnum]);
2163 
2164  return frame_unwind_got_register (this_frame, regnum, regnum);
2165 }
2166 
2167 static const struct frame_unwind i386_frame_unwind =
2168 {
2169  NORMAL_FRAME,
2173  NULL,
2175 };
2176 
2177 /* Normal frames, but in a function epilogue. */
2178 
2179 /* Implement the stack_frame_destroyed_p gdbarch method.
2180 
2181  The epilogue is defined here as the 'ret' instruction, which will
2182  follow any instruction such as 'leave' or 'pop %ebp' that destroys
2183  the function's stack frame. */
2184 
2185 static int
2186 i386_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2187 {
2188  gdb_byte insn;
2189  struct compunit_symtab *cust;
2190 
2191  cust = find_pc_compunit_symtab (pc);
2192  if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
2193  return 0;
2194 
2195  if (target_read_memory (pc, &insn, 1))
2196  return 0; /* Can't read memory at pc. */
2197 
2198  if (insn != 0xc3) /* 'ret' instruction. */
2199  return 0;
2200 
2201  return 1;
2202 }
2203 
2204 static int
2206  struct frame_info *this_frame,
2207  void **this_prologue_cache)
2208 {
2209  if (frame_relative_level (this_frame) == 0)
2210  return i386_stack_frame_destroyed_p (get_frame_arch (this_frame),
2211  get_frame_pc (this_frame));
2212  else
2213  return 0;
2214 }
2215 
2216 static struct i386_frame_cache *
2217 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2218 {
2219  struct i386_frame_cache *cache;
2220  CORE_ADDR sp;
2221 
2222  if (*this_cache)
2223  return *this_cache;
2224 
2225  cache = i386_alloc_frame_cache ();
2226  *this_cache = cache;
2227 
2228  TRY
2229  {
2230  cache->pc = get_frame_func (this_frame);
2231 
2232  /* At this point the stack looks as if we just entered the
2233  function, with the return address at the top of the
2234  stack. */
2235  sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM);
2236  cache->base = sp + cache->sp_offset;
2237  cache->saved_sp = cache->base + 8;
2238  cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
2239 
2240  cache->base_p = 1;
2241  }
2242  CATCH (ex, RETURN_MASK_ERROR)
2243  {
2244  if (ex.error != NOT_AVAILABLE_ERROR)
2245  throw_exception (ex);
2246  }
2247  END_CATCH
2248 
2249  return cache;
2250 }
2251 
2252 static enum unwind_stop_reason
2254  void **this_cache)
2255 {
2256  struct i386_frame_cache *cache =
2257  i386_epilogue_frame_cache (this_frame, this_cache);
2258 
2259  if (!cache->base_p)
2260  return UNWIND_UNAVAILABLE;
2261 
2262  return UNWIND_NO_REASON;
2263 }
2264 
2265 static void
2267  void **this_cache,
2268  struct frame_id *this_id)
2269 {
2270  struct i386_frame_cache *cache =
2271  i386_epilogue_frame_cache (this_frame, this_cache);
2272 
2273  if (!cache->base_p)
2274  (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2275  else
2276  (*this_id) = frame_id_build (cache->base + 8, cache->pc);
2277 }
2278 
2279 static struct value *
2281  void **this_cache, int regnum)
2282 {
2283  /* Make sure we've initialized the cache. */
2284  i386_epilogue_frame_cache (this_frame, this_cache);
2285 
2286  return i386_frame_prev_register (this_frame, this_cache, regnum);
2287 }
2288 
2289 static const struct frame_unwind i386_epilogue_frame_unwind =
2290 {
2291  NORMAL_FRAME,
2295  NULL,
2297 };
2298 
2299 
2300 /* Stack-based trampolines. */
2301 
2302 /* These trampolines are used on cross x86 targets, when taking the
2303  address of a nested function. When executing these trampolines,
2304  no stack frame is set up, so we are in a similar situation as in
2305  epilogues and i386_epilogue_frame_this_id can be re-used. */
2306 
2307 /* Static chain passed in register. */
2308 
2309 struct i386_insn i386_tramp_chain_in_reg_insns[] =
2310 {
2311  /* `movl imm32, %eax' and `movl imm32, %ecx' */
2312  { 5, { 0xb8 }, { 0xfe } },
2313 
2314  /* `jmp imm32' */
2315  { 5, { 0xe9 }, { 0xff } },
2316 
2317  {0}
2318 };
2319 
2320 /* Static chain passed on stack (when regparm=3). */
2321 
2322 struct i386_insn i386_tramp_chain_on_stack_insns[] =
2323 {
2324  /* `push imm32' */
2325  { 5, { 0x68 }, { 0xff } },
2326 
2327  /* `jmp imm32' */
2328  { 5, { 0xe9 }, { 0xff } },
2329 
2330  {0}
2331 };
2332 
2333 /* Return whether PC points inside a stack trampoline. */
2334 
2335 static int
2337 {
2338  gdb_byte insn;
2339  const char *name;
2340 
2341  /* A stack trampoline is detected if no name is associated
2342  to the current pc and if it points inside a trampoline
2343  sequence. */
2344 
2345  find_pc_partial_function (pc, &name, NULL, NULL);
2346  if (name)
2347  return 0;
2348 
2349  if (target_read_memory (pc, &insn, 1))
2350  return 0;
2351 
2352  if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns)
2353  && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns))
2354  return 0;
2355 
2356  return 1;
2357 }
2358 
2359 static int
2361  struct frame_info *this_frame,
2362  void **this_cache)
2363 {
2364  if (frame_relative_level (this_frame) == 0)
2365  return i386_in_stack_tramp_p (get_frame_pc (this_frame));
2366  else
2367  return 0;
2368 }
2369 
2370 static const struct frame_unwind i386_stack_tramp_frame_unwind =
2371 {
2372  NORMAL_FRAME,
2376  NULL,
2378 };
2379 
2380 /* Generate a bytecode expression to get the value of the saved PC. */
2381 
2382 static void
2383 i386_gen_return_address (struct gdbarch *gdbarch,
2384  struct agent_expr *ax, struct axs_value *value,
2385  CORE_ADDR scope)
2386 {
2387  /* The following sequence assumes the traditional use of the base
2388  register. */
2389  ax_reg (ax, I386_EBP_REGNUM);
2390  ax_const_l (ax, 4);
2391  ax_simple (ax, aop_add);
2392  value->type = register_type (gdbarch, I386_EIP_REGNUM);
2393  value->kind = axs_lvalue_memory;
2394 }
2395 
2396 
2397 /* Signal trampolines. */
2398 
2399 static struct i386_frame_cache *
2400 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2401 {
2402  struct gdbarch *gdbarch = get_frame_arch (this_frame);
2403  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2404  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2405  struct i386_frame_cache *cache;
2406  CORE_ADDR addr;
2407  gdb_byte buf[4];
2408 
2409  if (*this_cache)
2410  return *this_cache;
2411 
2412  cache = i386_alloc_frame_cache ();
2413 
2414  TRY
2415  {
2416  get_frame_register (this_frame, I386_ESP_REGNUM, buf);
2417  cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
2418 
2419  addr = tdep->sigcontext_addr (this_frame);
2420  if (tdep->sc_reg_offset)
2421  {
2422  int i;
2423 
2425 
2426  for (i = 0; i < tdep->sc_num_regs; i++)
2427  if (tdep->sc_reg_offset[i] != -1)
2428  cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
2429  }
2430  else
2431  {
2432  cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
2433  cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
2434  }
2435 
2436  cache->base_p = 1;
2437  }
2438  CATCH (ex, RETURN_MASK_ERROR)
2439  {
2440  if (ex.error != NOT_AVAILABLE_ERROR)
2441  throw_exception (ex);
2442  }
2443  END_CATCH
2444 
2445  *this_cache = cache;
2446  return cache;
2447 }
2448 
2449 static enum unwind_stop_reason
2451  void **this_cache)
2452 {
2453  struct i386_frame_cache *cache =
2454  i386_sigtramp_frame_cache (this_frame, this_cache);
2455 
2456  if (!cache->base_p)
2457  return UNWIND_UNAVAILABLE;
2458 
2459  return UNWIND_NO_REASON;
2460 }
2461 
2462 static void
2463 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
2464  struct frame_id *this_id)
2465 {
2466  struct i386_frame_cache *cache =
2467  i386_sigtramp_frame_cache (this_frame, this_cache);
2468 
2469  if (!cache->base_p)
2470  (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2471  else
2472  {
2473  /* See the end of i386_push_dummy_call. */
2474  (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
2475  }
2476 }
2477 
2478 static struct value *
2480  void **this_cache, int regnum)
2481 {
2482  /* Make sure we've initialized the cache. */
2483  i386_sigtramp_frame_cache (this_frame, this_cache);
2484 
2485  return i386_frame_prev_register (this_frame, this_cache, regnum);
2486 }
2487 
2488 static int
2490  struct frame_info *this_frame,
2491  void **this_prologue_cache)
2492 {
2493  struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2494 
2495  /* We shouldn't even bother if we don't have a sigcontext_addr
2496  handler. */
2497  if (tdep->sigcontext_addr == NULL)
2498  return 0;
2499 
2500  if (tdep->sigtramp_p != NULL)
2501  {
2502  if (tdep->sigtramp_p (this_frame))
2503  return 1;
2504  }
2505 
2506  if (tdep->sigtramp_start != 0)
2507  {
2508  CORE_ADDR pc = get_frame_pc (this_frame);
2509 
2510  gdb_assert (tdep->sigtramp_end != 0);
2511  if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
2512  return 1;
2513  }
2514 
2515  return 0;
2516 }
2517 
2518 static const struct frame_unwind i386_sigtramp_frame_unwind =
2519 {
2524  NULL,
2526 };
2527 
2528 
2529 static CORE_ADDR
2530 i386_frame_base_address (struct frame_info *this_frame, void **this_cache)
2531 {
2532  struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
2533 
2534  return cache->base;
2535 }
2536 
2537 static const struct frame_base i386_frame_base =
2538 {
2542  i386_frame_base_address
2543 };
2544 
2545 static struct frame_id
2546 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2547 {
2548  CORE_ADDR fp;
2549 
2550  fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
2551 
2552  /* See the end of i386_push_dummy_call. */
2553  return frame_id_build (fp + 8, get_frame_pc (this_frame));
2554 }
2555 
2556 /* _Decimal128 function return values need 16-byte alignment on the
2557  stack. */
2558 
2559 static CORE_ADDR
2560 i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2561 {
2562  return sp & -(CORE_ADDR)16;
2563 }
2564 
2565 
2566 /* Figure out where the longjmp will land. Slurp the args out of the
2567  stack. We expect the first arg to be a pointer to the jmp_buf
2568  structure from which we extract the address that we will land at.
2569  This address is copied into PC. This routine returns non-zero on
2570  success. */
2571 
2572 static int
2574 {
2575  gdb_byte buf[4];
2576  CORE_ADDR sp, jb_addr;
2577  struct gdbarch *gdbarch = get_frame_arch (frame);
2578  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2579  int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
2580 
2581  /* If JB_PC_OFFSET is -1, we have no way to find out where the
2582  longjmp will land. */
2583  if (jb_pc_offset == -1)
2584  return 0;
2585 
2586  get_frame_register (frame, I386_ESP_REGNUM, buf);
2587  sp = extract_unsigned_integer (buf, 4, byte_order);
2588  if (target_read_memory (sp + 4, buf, 4))
2589  return 0;
2590 
2591  jb_addr = extract_unsigned_integer (buf, 4, byte_order);
2592  if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
2593  return 0;
2594 
2595  *pc = extract_unsigned_integer (buf, 4, byte_order);
2596  return 1;
2597 }
2598 
2599 
2600 /* Check whether TYPE must be 16-byte-aligned when passed as a
2601  function argument. 16-byte vectors, _Decimal128 and structures or
2602  unions containing such types must be 16-byte-aligned; other
2603  arguments are 4-byte-aligned. */
2604 
2605 static int
2607 {
2608  type = check_typedef (type);
2609  if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT
2610  || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)))
2611  && TYPE_LENGTH (type) == 16)
2612  return 1;
2613  if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2614  return i386_16_byte_align_p (TYPE_TARGET_TYPE (type));
2615  if (TYPE_CODE (type) == TYPE_CODE_STRUCT
2616  || TYPE_CODE (type) == TYPE_CODE_UNION)
2617  {
2618  int i;
2619  for (i = 0; i < TYPE_NFIELDS (type); i++)
2620  {
2621  if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i)))
2622  return 1;
2623  }
2624  }
2625  return 0;
2626 }
2627 
2628 /* Implementation for set_gdbarch_push_dummy_code. */
2629 
2630 static CORE_ADDR
2631 i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
2632  struct value **args, int nargs, struct type *value_type,
2633  CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
2634  struct regcache *regcache)
2635 {
2636  /* Use 0xcc breakpoint - 1 byte. */
2637  *bp_addr = sp - 1;
2638  *real_pc = funaddr;
2639 
2640  /* Keep the stack aligned. */
2641  return sp - 16;
2642 }
2643 
2644 static CORE_ADDR
2645 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2646  struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2647  struct value **args, CORE_ADDR sp, int struct_return,
2648  CORE_ADDR struct_addr)
2649 {
2650  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2651  gdb_byte buf[4];
2652  int i;
2653  int write_pass;
2654  int args_space = 0;
2655 
2656  /* Determine the total space required for arguments and struct
2657  return address in a first pass (allowing for 16-byte-aligned
2658  arguments), then push arguments in a second pass. */
2659 
2660  for (write_pass = 0; write_pass < 2; write_pass++)
2661  {
2662  int args_space_used = 0;
2663 
2664  if (struct_return)
2665  {
2666  if (write_pass)
2667  {
2668  /* Push value address. */
2669  store_unsigned_integer (buf, 4, byte_order, struct_addr);
2670  write_memory (sp, buf, 4);
2671  args_space_used += 4;
2672  }
2673  else
2674  args_space += 4;
2675  }
2676 
2677  for (i = 0; i < nargs; i++)
2678  {
2679  int len = TYPE_LENGTH (value_enclosing_type (args[i]));
2680 
2681  if (write_pass)
2682  {
2684  args_space_used = align_up (args_space_used, 16);
2685 
2686  write_memory (sp + args_space_used,
2687  value_contents_all (args[i]), len);
2688  /* The System V ABI says that:
2689 
2690  "An argument's size is increased, if necessary, to make it a
2691  multiple of [32-bit] words. This may require tail padding,
2692  depending on the size of the argument."
2693 
2694  This makes sure the stack stays word-aligned. */
2695  args_space_used += align_up (len, 4);
2696  }
2697  else
2698  {
2700  args_space = align_up (args_space, 16);
2701  args_space += align_up (len, 4);
2702  }
2703  }
2704 
2705  if (!write_pass)
2706  {
2707  sp -= args_space;
2708 
2709  /* The original System V ABI only requires word alignment,
2710  but modern incarnations need 16-byte alignment in order
2711  to support SSE. Since wasting a few bytes here isn't
2712  harmful we unconditionally enforce 16-byte alignment. */
2713  sp &= ~0xf;
2714  }
2715  }
2716 
2717  /* Store return address. */
2718  sp -= 4;
2719  store_unsigned_integer (buf, 4, byte_order, bp_addr);
2720  write_memory (sp, buf, 4);
2721 
2722  /* Finally, update the stack pointer... */
2723  store_unsigned_integer (buf, 4, byte_order, sp);
2724  regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
2725 
2726  /* ...and fake a frame pointer. */
2727  regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
2728 
2729  /* MarkK wrote: This "+ 8" is all over the place:
2730  (i386_frame_this_id, i386_sigtramp_frame_this_id,
2731  i386_dummy_id). It's there, since all frame unwinders for
2732  a given target have to agree (within a certain margin) on the
2733  definition of the stack address of a frame. Otherwise frame id
2734  comparison might not work correctly. Since DWARF2/GCC uses the
2735  stack address *before* the function call as a frame's CFA. On
2736  the i386, when %ebp is used as a frame pointer, the offset
2737  between the contents %ebp and the CFA as defined by GCC. */
2738  return sp + 8;
2739 }
2740 
2741 /* These registers are used for returning integers (and on some
2742  targets also for returning `struct' and `union' values when their
2743  size and alignment match an integer type). */
2744 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2745 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2746 
2747 /* Read, for architecture GDBARCH, a function return value of TYPE
2748  from REGCACHE, and copy that into VALBUF. */
2749 
2750 static void
2751 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
2752  struct regcache *regcache, gdb_byte *valbuf)
2753 {
2754  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2755  int len = TYPE_LENGTH (type);
2757 
2758  if (TYPE_CODE (type) == TYPE_CODE_FLT)
2759  {
2760  if (tdep->st0_regnum < 0)
2761  {
2762  warning (_("Cannot find floating-point return value."));
2763  memset (valbuf, 0, len);
2764  return;
2765  }
2766 
2767  /* Floating-point return values can be found in %st(0). Convert
2768  its contents to the desired type. This is probably not
2769  exactly how it would happen on the target itself, but it is
2770  the best we can do. */
2771  regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
2772  convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type);
2773  }
2774  else
2775  {
2776  int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2777  int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2778 
2779  if (len <= low_size)
2780  {
2781  regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2782  memcpy (valbuf, buf, len);
2783  }
2784  else if (len <= (low_size + high_size))
2785  {
2786  regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
2787  memcpy (valbuf, buf, low_size);
2788  regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
2789  memcpy (valbuf + low_size, buf, len - low_size);
2790  }
2791  else
2792  internal_error (__FILE__, __LINE__,
2793  _("Cannot extract return value of %d bytes long."),
2794  len);
2795  }
2796 }
2797 
2798 /* Write, for architecture GDBARCH, a function return value of TYPE
2799  from VALBUF into REGCACHE. */
2800 
2801 static void
2802 i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
2803  struct regcache *regcache, const gdb_byte *valbuf)
2804 {
2805  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2806  int len = TYPE_LENGTH (type);
2807 
2808  if (TYPE_CODE (type) == TYPE_CODE_FLT)
2809  {
2810  ULONGEST fstat;
2812 
2813  if (tdep->st0_regnum < 0)
2814  {
2815  warning (_("Cannot set floating-point return value."));
2816  return;
2817  }
2818 
2819  /* Returning floating-point values is a bit tricky. Apart from
2820  storing the return value in %st(0), we have to simulate the
2821  state of the FPU at function return point. */
2822 
2823  /* Convert the value found in VALBUF to the extended
2824  floating-point format used by the FPU. This is probably
2825  not exactly how it would happen on the target itself, but
2826  it is the best we can do. */
2827  convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch));
2828  regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
2829 
2830  /* Set the top of the floating-point register stack to 7. The
2831  actual value doesn't really matter, but 7 is what a normal
2832  function return would end up with if the program started out
2833  with a freshly initialized FPU. */
2834  regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
2835  fstat |= (7 << 11);
2836  regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
2837 
2838  /* Mark %st(1) through %st(7) as empty. Since we set the top of
2839  the floating-point register stack to 7, the appropriate value
2840  for the tag word is 0x3fff. */
2841  regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
2842  }
2843  else
2844  {
2845  int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
2846  int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
2847 
2848  if (len <= low_size)
2849  regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
2850  else if (len <= (low_size + high_size))
2851  {
2852  regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
2854  len - low_size, valbuf + low_size);
2855  }
2856  else
2857  internal_error (__FILE__, __LINE__,
2858  _("Cannot store return value of %d bytes long."), len);
2859  }
2860 }
2861 
2862 
2863 /* This is the variable that is set with "set struct-convention", and
2864  its legitimate values. */
2865 static const char default_struct_convention[] = "default";
2866 static const char pcc_struct_convention[] = "pcc";
2867 static const char reg_struct_convention[] = "reg";
2868 static const char *const valid_conventions[] =
2869 {
2873  NULL
2874 };
2876 
2877 /* Return non-zero if TYPE, which is assumed to be a structure,
2878  a union type, or an array type, should be returned in registers
2879  for architecture GDBARCH. */
2880 
2881 static int
2882 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
2883 {
2884  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2885  enum type_code code = TYPE_CODE (type);
2886  int len = TYPE_LENGTH (type);
2887 
2888  gdb_assert (code == TYPE_CODE_STRUCT
2889  || code == TYPE_CODE_UNION
2890  || code == TYPE_CODE_ARRAY);
2891 
2894  && tdep->struct_return == pcc_struct_return))
2895  return 0;
2896 
2897  /* Structures consisting of a single `float', `double' or 'long
2898  double' member are returned in %st(0). */
2899  if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2900  {
2901  type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2902  if (TYPE_CODE (type) == TYPE_CODE_FLT)
2903  return (len == 4 || len == 8 || len == 12);
2904  }
2905 
2906  return (len == 1 || len == 2 || len == 4 || len == 8);
2907 }
2908 
2909 /* Determine, for architecture GDBARCH, how a return value of TYPE
2910  should be returned. If it is supposed to be returned in registers,
2911  and READBUF is non-zero, read the appropriate value from REGCACHE,
2912  and copy it into READBUF. If WRITEBUF is non-zero, write the value
2913  from WRITEBUF into REGCACHE. */
2914 
2915 static enum return_value_convention
2916 i386_return_value (struct gdbarch *gdbarch, struct value *function,
2917  struct type *type, struct regcache *regcache,
2918  gdb_byte *readbuf, const gdb_byte *writebuf)
2919 {
2920  enum type_code code = TYPE_CODE (type);
2921 
2922  if (((code == TYPE_CODE_STRUCT
2923  || code == TYPE_CODE_UNION
2924  || code == TYPE_CODE_ARRAY)
2925  && !i386_reg_struct_return_p (gdbarch, type))
2926  /* Complex double and long double uses the struct return covention. */
2927  || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16)
2928  || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24)
2929  /* 128-bit decimal float uses the struct return convention. */
2930  || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16))
2931  {
2932  /* The System V ABI says that:
2933 
2934  "A function that returns a structure or union also sets %eax
2935  to the value of the original address of the caller's area
2936  before it returns. Thus when the caller receives control
2937  again, the address of the returned object resides in register
2938  %eax and can be used to access the object."
2939 
2940  So the ABI guarantees that we can always find the return
2941  value just after the function has returned. */
2942 
2943  /* Note that the ABI doesn't mention functions returning arrays,
2944  which is something possible in certain languages such as Ada.
2945  In this case, the value is returned as if it was wrapped in
2946  a record, so the convention applied to records also applies
2947  to arrays. */
2948 
2949  if (readbuf)
2950  {
2951  ULONGEST addr;
2952 
2953  regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
2954  read_memory (addr, readbuf, TYPE_LENGTH (type));
2955  }
2956 
2958  }
2959 
2960  /* This special case is for structures consisting of a single
2961  `float', `double' or 'long double' member. These structures are
2962  returned in %st(0). For these structures, we call ourselves
2963  recursively, changing TYPE into the type of the first member of
2964  the structure. Since that should work for all structures that
2965  have only one member, we don't bother to check the member's type
2966  here. */
2967  if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1)
2968  {
2969  type = check_typedef (TYPE_FIELD_TYPE (type, 0));
2970  return i386_return_value (gdbarch, function, type, regcache,
2971  readbuf, writebuf);
2972  }
2973 
2974  if (readbuf)
2975  i386_extract_return_value (gdbarch, type, regcache, readbuf);
2976  if (writebuf)
2977  i386_store_return_value (gdbarch, type, regcache, writebuf);
2978 
2980 }
2981 
2982 
2983 struct type *
2984 i387_ext_type (struct gdbarch *gdbarch)
2985 {
2986  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2987 
2988  if (!tdep->i387_ext_type)
2989  {
2990  tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
2991  gdb_assert (tdep->i387_ext_type != NULL);
2992  }
2993 
2994  return tdep->i387_ext_type;
2995 }
2996 
2997 /* Construct type for pseudo BND registers. We can't use
2998  tdesc_find_type since a complement of one value has to be used
2999  to describe the upper bound. */
3000 
3001 static struct type *
3002 i386_bnd_type (struct gdbarch *gdbarch)
3003 {
3004  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3005 
3006 
3007  if (!tdep->i386_bnd_type)
3008  {
3009  struct type *t, *bound_t;
3010  const struct builtin_type *bt = builtin_type (gdbarch);
3011 
3012  /* The type we're building is described bellow: */
3013 #if 0
3014  struct __bound128
3015  {
3016  void *lbound;
3017  void *ubound; /* One complement of raw ubound field. */
3018  };
3019 #endif
3020 
3021  t = arch_composite_type (gdbarch,
3022  "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT);
3023 
3024  append_composite_type_field (t, "lbound", bt->builtin_data_ptr);
3025  append_composite_type_field (t, "ubound", bt->builtin_data_ptr);
3026 
3027  TYPE_NAME (t) = "builtin_type_bound128";
3028  tdep->i386_bnd_type = t;
3029  }
3030 
3031  return tdep->i386_bnd_type;
3032 }
3033 
3034 /* Construct vector type for pseudo ZMM registers. We can't use
3035  tdesc_find_type since ZMM isn't described in target description. */
3036 
3037 static struct type *
3038 i386_zmm_type (struct gdbarch *gdbarch)
3039 {
3040  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3041 
3042  if (!tdep->i386_zmm_type)
3043  {
3044  const struct builtin_type *bt = builtin_type (gdbarch);
3045 
3046  /* The type we're building is this: */
3047 #if 0
3048  union __gdb_builtin_type_vec512i
3049  {
3050  int128_t uint128[4];
3051  int64_t v4_int64[8];
3052  int32_t v8_int32[16];
3053  int16_t v16_int16[32];
3054  int8_t v32_int8[64];
3055  double v4_double[8];
3056  float v8_float[16];
3057  };
3058 #endif
3059 
3060  struct type *t;
3061 
3062  t = arch_composite_type (gdbarch,
3063  "__gdb_builtin_type_vec512i", TYPE_CODE_UNION);
3064  append_composite_type_field (t, "v16_float",
3065  init_vector_type (bt->builtin_float, 16));
3066  append_composite_type_field (t, "v8_double",
3067  init_vector_type (bt->builtin_double, 8));
3068  append_composite_type_field (t, "v64_int8",
3069  init_vector_type (bt->builtin_int8, 64));
3070  append_composite_type_field (t, "v32_int16",
3071  init_vector_type (bt->builtin_int16, 32));
3072  append_composite_type_field (t, "v16_int32",
3073  init_vector_type (bt->builtin_int32, 16));
3074  append_composite_type_field (t, "v8_int64",
3075  init_vector_type (bt->builtin_int64, 8));
3076  append_composite_type_field (t, "v4_int128",
3077  init_vector_type (bt->builtin_int128, 4));
3078 
3079  TYPE_VECTOR (t) = 1;
3080  TYPE_NAME (t) = "builtin_type_vec512i";
3081  tdep->i386_zmm_type = t;
3082  }
3083 
3084  return tdep->i386_zmm_type;
3085 }
3086 
3087 /* Construct vector type for pseudo YMM registers. We can't use
3088  tdesc_find_type since YMM isn't described in target description. */
3089 
3090 static struct type *
3091 i386_ymm_type (struct gdbarch *gdbarch)
3092 {
3093  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3094 
3095  if (!tdep->i386_ymm_type)
3096  {
3097  const struct builtin_type *bt = builtin_type (gdbarch);
3098 
3099  /* The type we're building is this: */
3100 #if 0
3101  union __gdb_builtin_type_vec256i
3102  {
3103  int128_t uint128[2];
3104  int64_t v2_int64[4];
3105  int32_t v4_int32[8];
3106  int16_t v8_int16[16];
3107  int8_t v16_int8[32];
3108  double v2_double[4];
3109  float v4_float[8];
3110  };
3111 #endif
3112 
3113  struct type *t;
3114 
3115  t = arch_composite_type (gdbarch,
3116  "__gdb_builtin_type_vec256i", TYPE_CODE_UNION);
3117  append_composite_type_field (t, "v8_float",
3118  init_vector_type (bt->builtin_float, 8));
3119  append_composite_type_field (t, "v4_double",
3120  init_vector_type (bt->builtin_double, 4));
3121  append_composite_type_field (t, "v32_int8",
3122  init_vector_type (bt->builtin_int8, 32));
3123  append_composite_type_field (t, "v16_int16",
3124  init_vector_type (bt->builtin_int16, 16));
3125  append_composite_type_field (t, "v8_int32",
3126  init_vector_type (bt->builtin_int32, 8));
3127  append_composite_type_field (t, "v4_int64",
3128  init_vector_type (bt->builtin_int64, 4));
3129  append_composite_type_field (t, "v2_int128",
3130  init_vector_type (bt->builtin_int128, 2));
3131 
3132  TYPE_VECTOR (t) = 1;
3133  TYPE_NAME (t) = "builtin_type_vec256i";
3134  tdep->i386_ymm_type = t;
3135  }
3136 
3137  return tdep->i386_ymm_type;
3138 }
3139 
3140 /* Construct vector type for MMX registers. */
3141 static struct type *
3142 i386_mmx_type (struct gdbarch *gdbarch)
3143 {
3144  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3145 
3146  if (!tdep->i386_mmx_type)
3147  {
3148  const struct builtin_type *bt = builtin_type (gdbarch);
3149 
3150  /* The type we're building is this: */
3151 #if 0
3152  union __gdb_builtin_type_vec64i
3153  {
3154  int64_t uint64;
3155  int32_t v2_int32[2];
3156  int16_t v4_int16[4];
3157  int8_t v8_int8[8];
3158  };
3159 #endif
3160 
3161  struct type *t;
3162 
3163  t = arch_composite_type (gdbarch,
3164  "__gdb_builtin_type_vec64i", TYPE_CODE_UNION);
3165 
3166  append_composite_type_field (t, "uint64", bt->builtin_int64);
3167  append_composite_type_field (t, "v2_int32",
3168  init_vector_type (bt->builtin_int32, 2));
3169  append_composite_type_field (t, "v4_int16",
3170  init_vector_type (bt->builtin_int16, 4));
3171  append_composite_type_field (t, "v8_int8",
3172  init_vector_type (bt->builtin_int8, 8));
3173 
3174  TYPE_VECTOR (t) = 1;
3175  TYPE_NAME (t) = "builtin_type_vec64i";
3176  tdep->i386_mmx_type = t;
3177  }
3178 
3179  return tdep->i386_mmx_type;
3180 }
3181 
3182 /* Return the GDB type object for the "standard" data type of data in
3183  register REGNUM. */
3184 
3185 struct type *
3186 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3187 {
3188  if (i386_bnd_regnum_p (gdbarch, regnum))
3189  return i386_bnd_type (gdbarch);
3190  if (i386_mmx_regnum_p (gdbarch, regnum))
3191  return i386_mmx_type (gdbarch);
3192  else if (i386_ymm_regnum_p (gdbarch, regnum))
3193  return i386_ymm_type (gdbarch);
3194  else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3195  return i386_ymm_type (gdbarch);
3196  else if (i386_zmm_regnum_p (gdbarch, regnum))
3197  return i386_zmm_type (gdbarch);
3198  else
3199  {
3200  const struct builtin_type *bt = builtin_type (gdbarch);
3201  if (i386_byte_regnum_p (gdbarch, regnum))
3202  return bt->builtin_int8;
3203  else if (i386_word_regnum_p (gdbarch, regnum))
3204  return bt->builtin_int16;
3205  else if (i386_dword_regnum_p (gdbarch, regnum))
3206  return bt->builtin_int32;
3207  else if (i386_k_regnum_p (gdbarch, regnum))
3208  return bt->builtin_int64;
3209  }
3210 
3211  internal_error (__FILE__, __LINE__, _("invalid regnum"));
3212 }
3213 
3214 /* Map a cooked register onto a raw register or memory. For the i386,
3215  the MMX registers need to be mapped onto floating point registers. */
3216 
3217 static int
3219 {
3220  struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
3221  int mmxreg, fpreg;
3222  ULONGEST fstat;
3223  int tos;
3224 
3225  mmxreg = regnum - tdep->mm0_regnum;
3226  regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
3227  tos = (fstat >> 11) & 0x7;
3228  fpreg = (mmxreg + tos) % 8;
3229 
3230  return (I387_ST0_REGNUM (tdep) + fpreg);
3231 }
3232 
3233 /* A helper function for us by i386_pseudo_register_read_value and
3234  amd64_pseudo_register_read_value. It does all the work but reads
3235  the data into an already-allocated value. */
3236 
3237 void
3238 i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
3239  struct regcache *regcache,
3240  int regnum,
3241  struct value *result_value)
3242 {
3243  gdb_byte raw_buf[MAX_REGISTER_SIZE];
3244  enum register_status status;
3245  gdb_byte *buf = value_contents_raw (result_value);
3246 
3247  if (i386_mmx_regnum_p (gdbarch, regnum))
3248  {
3249  int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3250 
3251  /* Extract (always little endian). */
3252  status = regcache_raw_read (regcache, fpnum, raw_buf);
3253  if (status != REG_VALID)
3254  mark_value_bytes_unavailable (result_value, 0,
3255  TYPE_LENGTH (value_type (result_value)));
3256  else
3257  memcpy (buf, raw_buf, register_size (gdbarch, regnum));
3258  }
3259  else
3260  {
3261  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3262  if (i386_bnd_regnum_p (gdbarch, regnum))
3263  {
3264  regnum -= tdep->bnd0_regnum;
3265 
3266  /* Extract (always little endian). Read lower 128bits. */
3267  status = regcache_raw_read (regcache,
3268  I387_BND0R_REGNUM (tdep) + regnum,
3269  raw_buf);
3270  if (status != REG_VALID)
3271  mark_value_bytes_unavailable (result_value, 0, 16);
3272  else
3273  {
3274  enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3275  LONGEST upper, lower;
3276  int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3277 
3278  lower = extract_unsigned_integer (raw_buf, 8, byte_order);
3279  upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order);
3280  upper = ~upper;
3281 
3282  memcpy (buf, &lower, size);
3283  memcpy (buf + size, &upper, size);
3284  }
3285  }
3286  else if (i386_k_regnum_p (gdbarch, regnum))
3287  {
3288  regnum -= tdep->k0_regnum;
3289 
3290  /* Extract (always little endian). */
3291  status = regcache_raw_read (regcache,
3292  tdep->k0_regnum + regnum,
3293  raw_buf);
3294  if (status != REG_VALID)
3295  mark_value_bytes_unavailable (result_value, 0, 8);
3296  else
3297  memcpy (buf, raw_buf, 8);
3298  }
3299  else if (i386_zmm_regnum_p (gdbarch, regnum))
3300  {
3301  regnum -= tdep->zmm0_regnum;
3302 
3303  if (regnum < num_lower_zmm_regs)
3304  {
3305  /* Extract (always little endian). Read lower 128bits. */
3306  status = regcache_raw_read (regcache,
3307  I387_XMM0_REGNUM (tdep) + regnum,
3308  raw_buf);
3309  if (status != REG_VALID)
3310  mark_value_bytes_unavailable (result_value, 0, 16);
3311  else
3312  memcpy (buf, raw_buf, 16);
3313 
3314  /* Extract (always little endian). Read upper 128bits. */
3315  status = regcache_raw_read (regcache,
3316  tdep->ymm0h_regnum + regnum,
3317  raw_buf);
3318  if (status != REG_VALID)
3319  mark_value_bytes_unavailable (result_value, 16, 16);
3320  else
3321  memcpy (buf + 16, raw_buf, 16);
3322  }
3323  else
3324  {
3325  /* Extract (always little endian). Read lower 128bits. */
3326  status = regcache_raw_read (regcache,
3327  I387_XMM16_REGNUM (tdep) + regnum
3329  raw_buf);
3330  if (status != REG_VALID)
3331  mark_value_bytes_unavailable (result_value, 0, 16);
3332  else
3333  memcpy (buf, raw_buf, 16);
3334 
3335  /* Extract (always little endian). Read upper 128bits. */
3336  status = regcache_raw_read (regcache,
3337  I387_YMM16H_REGNUM (tdep) + regnum
3339  raw_buf);
3340  if (status != REG_VALID)
3341  mark_value_bytes_unavailable (result_value, 16, 16);
3342  else
3343  memcpy (buf + 16, raw_buf, 16);
3344  }
3345 
3346  /* Read upper 256bits. */
3347  status = regcache_raw_read (regcache,
3348  tdep->zmm0h_regnum + regnum,
3349  raw_buf);
3350  if (status != REG_VALID)
3351  mark_value_bytes_unavailable (result_value, 32, 32);
3352  else
3353  memcpy (buf + 32, raw_buf, 32);
3354  }
3355  else if (i386_ymm_regnum_p (gdbarch, regnum))
3356  {
3357  regnum -= tdep->ymm0_regnum;
3358 
3359  /* Extract (always little endian). Read lower 128bits. */
3360  status = regcache_raw_read (regcache,
3361  I387_XMM0_REGNUM (tdep) + regnum,
3362  raw_buf);
3363  if (status != REG_VALID)
3364  mark_value_bytes_unavailable (result_value, 0, 16);
3365  else
3366  memcpy (buf, raw_buf, 16);
3367  /* Read upper 128bits. */
3368  status = regcache_raw_read (regcache,
3369  tdep->ymm0h_regnum + regnum,
3370  raw_buf);
3371  if (status != REG_VALID)
3372  mark_value_bytes_unavailable (result_value, 16, 32);
3373  else
3374  memcpy (buf + 16, raw_buf, 16);
3375  }
3376  else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3377  {
3378  regnum -= tdep->ymm16_regnum;
3379  /* Extract (always little endian). Read lower 128bits. */
3380  status = regcache_raw_read (regcache,
3381  I387_XMM16_REGNUM (tdep) + regnum,
3382  raw_buf);
3383  if (status != REG_VALID)
3384  mark_value_bytes_unavailable (result_value, 0, 16);
3385  else
3386  memcpy (buf, raw_buf, 16);
3387  /* Read upper 128bits. */
3388  status = regcache_raw_read (regcache,
3389  tdep->ymm16h_regnum + regnum,
3390  raw_buf);
3391  if (status != REG_VALID)
3392  mark_value_bytes_unavailable (result_value, 16, 16);
3393  else
3394  memcpy (buf + 16, raw_buf, 16);
3395  }
3396  else if (i386_word_regnum_p (gdbarch, regnum))
3397  {
3398  int gpnum = regnum - tdep->ax_regnum;
3399 
3400  /* Extract (always little endian). */
3401  status = regcache_raw_read (regcache, gpnum, raw_buf);
3402  if (status != REG_VALID)
3403  mark_value_bytes_unavailable (result_value, 0,
3404  TYPE_LENGTH (value_type (result_value)));
3405  else
3406  memcpy (buf, raw_buf, 2);
3407  }
3408  else if (i386_byte_regnum_p (gdbarch, regnum))
3409  {
3410  /* Check byte pseudo registers last since this function will
3411  be called from amd64_pseudo_register_read, which handles
3412  byte pseudo registers differently. */
3413  int gpnum = regnum - tdep->al_regnum;
3414 
3415  /* Extract (always little endian). We read both lower and
3416  upper registers. */
3417  status = regcache_raw_read (regcache, gpnum % 4, raw_buf);
3418  if (status != REG_VALID)
3419  mark_value_bytes_unavailable (result_value, 0,
3420  TYPE_LENGTH (value_type (result_value)));
3421  else if (gpnum >= 4)
3422  memcpy (buf, raw_buf + 1, 1);
3423  else
3424  memcpy (buf, raw_buf, 1);
3425  }
3426  else
3427  internal_error (__FILE__, __LINE__, _("invalid regnum"));
3428  }
3429 }
3430 
3431 static struct value *
3432 i386_pseudo_register_read_value (struct gdbarch *gdbarch,
3433  struct regcache *regcache,
3434  int regnum)
3435 {
3436  struct value *result;
3437 
3438  result = allocate_value (register_type (gdbarch, regnum));
3439  VALUE_LVAL (result) = lval_register;
3440  VALUE_REGNUM (result) = regnum;
3441 
3442  i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result);
3443 
3444  return result;
3445 }
3446 
3447 void
3448 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3449  int regnum, const gdb_byte *buf)
3450 {
3451  gdb_byte raw_buf[MAX_REGISTER_SIZE];
3452 
3453  if (i386_mmx_regnum_p (gdbarch, regnum))
3454  {
3455  int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
3456 
3457  /* Read ... */
3458  regcache_raw_read (regcache, fpnum, raw_buf);
3459  /* ... Modify ... (always little endian). */
3460  memcpy (raw_buf, buf, register_size (gdbarch, regnum));
3461  /* ... Write. */
3462  regcache_raw_write (regcache, fpnum, raw_buf);
3463  }
3464  else
3465  {
3466  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3467 
3468  if (i386_bnd_regnum_p (gdbarch, regnum))
3469  {
3470  ULONGEST upper, lower;
3471  int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr);
3472  enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
3473 
3474  /* New values from input value. */
3475  regnum -= tdep->bnd0_regnum;
3476  lower = extract_unsigned_integer (buf, size, byte_order);
3477  upper = extract_unsigned_integer (buf + size, size, byte_order);
3478 
3479  /* Fetching register buffer. */
3480  regcache_raw_read (regcache,
3481  I387_BND0R_REGNUM (tdep) + regnum,
3482  raw_buf);
3483 
3484  upper = ~upper;
3485 
3486  /* Set register bits. */
3487  memcpy (raw_buf, &lower, 8);
3488  memcpy (raw_buf + 8, &upper, 8);
3489 
3490 
3491  regcache_raw_write (regcache,
3492  I387_BND0R_REGNUM (tdep) + regnum,
3493  raw_buf);
3494  }
3495  else if (i386_k_regnum_p (gdbarch, regnum))
3496  {
3497  regnum -= tdep->k0_regnum;
3498 
3499  regcache_raw_write (regcache,
3500  tdep->k0_regnum + regnum,
3501  buf);
3502  }
3503  else if (i386_zmm_regnum_p (gdbarch, regnum))
3504  {
3505  regnum -= tdep->zmm0_regnum;
3506 
3507  if (regnum < num_lower_zmm_regs)
3508  {
3509  /* Write lower 128bits. */
3510  regcache_raw_write (regcache,
3511  I387_XMM0_REGNUM (tdep) + regnum,
3512  buf);
3513  /* Write upper 128bits. */
3514  regcache_raw_write (regcache,
3515  I387_YMM0_REGNUM (tdep) + regnum,
3516  buf + 16);
3517  }
3518  else
3519  {
3520  /* Write lower 128bits. */
3521  regcache_raw_write (regcache,
3522  I387_XMM16_REGNUM (tdep) + regnum
3524  buf);
3525  /* Write upper 128bits. */
3526  regcache_raw_write (regcache,
3527  I387_YMM16H_REGNUM (tdep) + regnum
3529  buf + 16);
3530  }
3531  /* Write upper 256bits. */
3532  regcache_raw_write (regcache,
3533  tdep->zmm0h_regnum + regnum,
3534  buf + 32);
3535  }
3536  else if (i386_ymm_regnum_p (gdbarch, regnum))
3537  {
3538  regnum -= tdep->ymm0_regnum;
3539 
3540  /* ... Write lower 128bits. */
3541  regcache_raw_write (regcache,
3542  I387_XMM0_REGNUM (tdep) + regnum,
3543  buf);
3544  /* ... Write upper 128bits. */
3545  regcache_raw_write (regcache,
3546  tdep->ymm0h_regnum + regnum,
3547  buf + 16);
3548  }
3549  else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
3550  {
3551  regnum -= tdep->ymm16_regnum;
3552 
3553  /* ... Write lower 128bits. */
3554  regcache_raw_write (regcache,
3555  I387_XMM16_REGNUM (tdep) + regnum,
3556  buf);
3557  /* ... Write upper 128bits. */
3558  regcache_raw_write (regcache,
3559  tdep->ymm16h_regnum + regnum,
3560  buf + 16);
3561  }
3562  else if (i386_word_regnum_p (gdbarch, regnum))
3563  {
3564  int gpnum = regnum - tdep->ax_regnum;
3565 
3566  /* Read ... */
3567  regcache_raw_read (regcache, gpnum, raw_buf);
3568  /* ... Modify ... (always little endian). */
3569  memcpy (raw_buf, buf, 2);
3570  /* ... Write. */
3571  regcache_raw_write (regcache, gpnum, raw_buf);
3572  }
3573  else if (i386_byte_regnum_p (gdbarch, regnum))
3574  {
3575  /* Check byte pseudo registers last since this function will
3576  be called from amd64_pseudo_register_read, which handles
3577  byte pseudo registers differently. */
3578  int gpnum = regnum - tdep->al_regnum;
3579 
3580  /* Read ... We read both lower and upper registers. */
3581  regcache_raw_read (regcache, gpnum % 4, raw_buf);
3582  /* ... Modify ... (always little endian). */
3583  if (gpnum >= 4)
3584  memcpy (raw_buf + 1, buf, 1);
3585  else
3586  memcpy (raw_buf, buf, 1);
3587  /* ... Write. */
3588  regcache_raw_write (regcache, gpnum % 4, raw_buf);
3589  }
3590  else
3591  internal_error (__FILE__, __LINE__, _("invalid regnum"));
3592  }
3593 }
3594 
3595 
3596 /* Return the register number of the register allocated by GCC after
3597  REGNUM, or -1 if there is no such register. */
3598 
3599 static int
3601 {
3602  /* GCC allocates the registers in the order:
3603 
3604  %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3605 
3606  Since storing a variable in %esp doesn't make any sense we return
3607  -1 for %ebp and for %esp itself. */
3608  static int next_regnum[] =
3609  {
3610  I386_EDX_REGNUM, /* Slot for %eax. */
3611  I386_EBX_REGNUM, /* Slot for %ecx. */
3612  I386_ECX_REGNUM, /* Slot for %edx. */
3613  I386_ESI_REGNUM, /* Slot for %ebx. */
3614  -1, -1, /* Slots for %esp and %ebp. */
3615  I386_EDI_REGNUM, /* Slot for %esi. */
3616  I386_EBP_REGNUM /* Slot for %edi. */
3617  };
3618 
3619  if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
3620  return next_regnum[regnum];
3621 
3622  return -1;
3623 }
3624 
3625 /* Return nonzero if a value of type TYPE stored in register REGNUM
3626  needs any special handling. */
3627 
3628 static int
3629 i386_convert_register_p (struct gdbarch *gdbarch,
3630  int regnum, struct type *type)
3631 {
3632  int len = TYPE_LENGTH (type);
3633 
3634  /* Values may be spread across multiple registers. Most debugging
3635  formats aren't expressive enough to specify the locations, so
3636  some heuristics is involved. Right now we only handle types that
3637  have a length that is a multiple of the word size, since GCC
3638  doesn't seem to put any other types into registers. */
3639  if (len > 4 && len % 4 == 0)
3640  {
3641  int last_regnum = regnum;
3642 
3643  while (len > 4)
3644  {
3645  last_regnum = i386_next_regnum (last_regnum);
3646  len -= 4;
3647  }
3648 
3649  if (last_regnum != -1)
3650  return 1;
3651  }
3652 
3653  return i387_convert_register_p (gdbarch, regnum, type);
3654 }
3655 
3656 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3657  return its contents in TO. */
3658 
3659 static int
3661  struct type *type, gdb_byte *to,
3662  int *optimizedp, int *unavailablep)
3663 {
3664  struct gdbarch *gdbarch = get_frame_arch (frame);
3665  int len = TYPE_LENGTH (type);
3666 
3667  if (i386_fp_regnum_p (gdbarch, regnum))
3668  return i387_register_to_value (frame, regnum, type, to,
3669  optimizedp, unavailablep);
3670 
3671  /* Read a value spread across multiple registers. */
3672 
3673  gdb_assert (len > 4 && len % 4 == 0);
3674 
3675  while (len > 0)
3676  {
3677  gdb_assert (regnum != -1);
3678  gdb_assert (register_size (gdbarch, regnum) == 4);
3679 
3680  if (!get_frame_register_bytes (frame, regnum, 0,
3681  register_size (gdbarch, regnum),
3682  to, optimizedp, unavailablep))
3683  return 0;
3684 
3685  regnum = i386_next_regnum (regnum);
3686  len -= 4;
3687  to += 4;
3688  }
3689 
3690  *optimizedp = *unavailablep = 0;
3691  return 1;
3692 }
3693 
3694 /* Write the contents FROM of a value of type TYPE into register
3695  REGNUM in frame FRAME. */
3696 
3697 static void
3699  struct type *type, const gdb_byte *from)
3700 {
3701  int len = TYPE_LENGTH (type);
3702 
3703  if (i386_fp_regnum_p (get_frame_arch (frame), regnum))
3704  {
3705  i387_value_to_register (frame, regnum, type, from);
3706  return;
3707  }
3708 
3709  /* Write a value spread across multiple registers. */
3710 
3711  gdb_assert (len > 4 && len % 4 == 0);
3712 
3713  while (len > 0)
3714  {
3715  gdb_assert (regnum != -1);
3716  gdb_assert (register_size (get_frame_arch (frame), regnum) == 4);
3717 
3718  put_frame_register (frame, regnum, from);
3719  regnum = i386_next_regnum (regnum);
3720  len -= 4;
3721  from += 4;
3722  }
3723 }
3724 
3725 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3726  in the general-purpose register set REGSET to register cache
3727  REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3728 
3729 void
3731  int regnum, const void *gregs, size_t len)
3732 {
3733  struct gdbarch *gdbarch = get_regcache_arch (regcache);
3734  const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3735  const gdb_byte *regs = gregs;
3736  int i;
3737 
3738  gdb_assert (len >= tdep->sizeof_gregset);
3739 
3740  for (i = 0; i < tdep->gregset_num_regs; i++)
3741  {
3742  if ((regnum == i || regnum == -1)
3743  && tdep->gregset_reg_offset[i] != -1)
3744  regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]);
3745  }
3746 }
3747 
3748 /* Collect register REGNUM from the register cache REGCACHE and store
3749  it in the buffer specified by GREGS and LEN as described by the
3750  general-purpose register set REGSET. If REGNUM is -1, do this for
3751  all registers in REGSET. */
3752 
3753 static void
3755  const struct regcache *regcache,
3756  int regnum, void *gregs, size_t len)
3757 {
3758  struct gdbarch *gdbarch = get_regcache_arch (regcache);
3759  const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3760  gdb_byte *regs = gregs;
3761  int i;
3762 
3763  gdb_assert (len >= tdep->sizeof_gregset);
3764 
3765  for (i = 0; i < tdep->gregset_num_regs; i++)
3766  {
3767  if ((regnum == i || regnum == -1)
3768  && tdep->gregset_reg_offset[i] != -1)
3769  regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]);
3770  }
3771 }
3772 
3773 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3774  in the floating-point register set REGSET to register cache
3775  REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3776 
3777 static void
3779  int regnum, const void *fpregs, size_t len)
3780 {
3781  struct gdbarch *gdbarch = get_regcache_arch (regcache);
3782  const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3783 
3784  if (len == I387_SIZEOF_FXSAVE)
3785  {
3786  i387_supply_fxsave (regcache, regnum, fpregs);
3787  return;
3788  }
3789 
3790  gdb_assert (len >= tdep->sizeof_fpregset);
3791  i387_supply_fsave (regcache, regnum, fpregs);
3792 }
3793 
3794 /* Collect register REGNUM from the register cache REGCACHE and store
3795  it in the buffer specified by FPREGS and LEN as described by the
3796  floating-point register set REGSET. If REGNUM is -1, do this for
3797  all registers in REGSET. */
3798 
3799 static void
3801  const struct regcache *regcache,
3802  int regnum, void *fpregs, size_t len)
3803 {
3804  struct gdbarch *gdbarch = get_regcache_arch (regcache);
3805  const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3806 
3807  if (len == I387_SIZEOF_FXSAVE)
3808  {
3809  i387_collect_fxsave (regcache, regnum, fpregs);
3810  return;
3811  }
3812 
3813  gdb_assert (len >= tdep->sizeof_fpregset);
3814  i387_collect_fsave (regcache, regnum, fpregs);
3815 }
3816 
3817 /* Register set definitions. */
3818 
3819 const struct regset i386_gregset =
3820  {
3822  };
3823 
3824 const struct regset i386_fpregset =
3825  {
3827  };
3828 
3829 /* Default iterator over core file register note sections. */
3830 
3831 void
3832 i386_iterate_over_regset_sections (struct gdbarch *gdbarch,
3834  void *cb_data,
3835  const struct regcache *regcache)
3836 {
3837  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3838 
3839  cb (".reg", tdep->sizeof_gregset, &i386_gregset, NULL, cb_data);
3840  if (tdep->sizeof_fpregset)
3841  cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
3842 }
3843 
3844 
3845 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3846 
3847 CORE_ADDR
3849  CORE_ADDR pc, char *name)
3850 {
3851  struct gdbarch *gdbarch = get_frame_arch (frame);
3852  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3853 
3854  /* jmp *(dest) */
3855  if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff)
3856  {
3857  unsigned long indirect =
3858  read_memory_unsigned_integer (pc + 2, 4, byte_order);
3859  struct minimal_symbol *indsym =
3860  indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0;
3861  const char *symname = indsym ? MSYMBOL_LINKAGE_NAME (indsym) : 0;
3862 
3863  if (symname)
3864  {
3865  if (startswith (symname, "__imp_")
3866  || startswith (symname, "_imp_"))
3867  return name ? 1 :
3868  read_memory_unsigned_integer (indirect, 4, byte_order);
3869  }
3870  }
3871  return 0; /* Not a trampoline. */
3872 }
3873 
3874 
3875 /* Return whether the THIS_FRAME corresponds to a sigtramp
3876  routine. */
3877 
3878 int
3879 i386_sigtramp_p (struct frame_info *this_frame)
3880 {
3881  CORE_ADDR pc = get_frame_pc (this_frame);
3882  const char *name;
3883 
3884  find_pc_partial_function (pc, &name, NULL, NULL);
3885  return (name && strcmp ("_sigtramp", name) == 0);
3886 }
3887 
3888 
3889 /* We have two flavours of disassembly. The machinery on this page
3890  deals with switching between those. */
3891 
3892 static int
3893 i386_print_insn (bfd_vma pc, struct disassemble_info *info)
3894 {
3897 
3898  /* FIXME: kettenis/20020915: Until disassembler_options is properly
3899  constified, cast to prevent a compiler warning. */
3900  info->disassembler_options = (char *) disassembly_flavor;
3901 
3902  return print_insn_i386 (pc, info);
3903 }
3904 
3905 
3906 /* There are a few i386 architecture variants that differ only
3907  slightly from the generic i386 target. For now, we don't give them
3908  their own source file, but include them here. As a consequence,
3909  they'll always be included. */
3910 
3911 /* System V Release 4 (SVR4). */
3912 
3913 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3914  routine. */
3915 
3916 static int
3917 i386_svr4_sigtramp_p (struct frame_info *this_frame)
3918 {
3919  CORE_ADDR pc = get_frame_pc (this_frame);
3920  const char *name;
3921 
3922  /* The origin of these symbols is currently unknown. */
3923  find_pc_partial_function (pc, &name, NULL, NULL);
3924  return (name && (strcmp ("_sigreturn", name) == 0
3925  || strcmp ("sigvechandler", name) == 0));
3926 }
3927 
3928 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3929  address of the associated sigcontext (ucontext) structure. */
3930 
3931 static CORE_ADDR
3933 {
3934  struct gdbarch *gdbarch = get_frame_arch (this_frame);
3935  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3936  gdb_byte buf[4];
3937  CORE_ADDR sp;
3938 
3939  get_frame_register (this_frame, I386_ESP_REGNUM, buf);
3940  sp = extract_unsigned_integer (buf, 4, byte_order);
3941 
3942  return read_memory_unsigned_integer (sp + 8, 4, byte_order);
3943 }
3944 
3945 
3946 
3947 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
3948  gdbarch.h. */
3949 
3950 int
3951 i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s)
3952 {
3953  return (*s == '$' /* Literal number. */
3954  || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */
3955  || (*s == '(' && s[1] == '%') /* Register indirection. */
3956  || (*s == '%' && isalpha (s[1]))); /* Register access. */
3957 }
3958 
3959 /* Helper function for i386_stap_parse_special_token.
3960 
3961  This function parses operands of the form `-8+3+1(%rbp)', which
3962  must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
3963 
3964  Return 1 if the operand was parsed successfully, zero
3965  otherwise. */
3966 
3967 static int
3968 i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch,
3969  struct stap_parse_info *p)
3970 {
3971  const char *s = p->arg;
3972 
3973  if (isdigit (*s) || *s == '-' || *s == '+')
3974  {
3975  int got_minus[3];
3976  int i;
3977  long displacements[3];
3978  const char *start;
3979  char *regname;
3980  int len;
3981  struct stoken str;
3982  char *endp;
3983 
3984  got_minus[0] = 0;
3985  if (*s == '+')
3986  ++s;
3987  else if (*s == '-')
3988  {
3989  ++s;
3990  got_minus[0] = 1;
3991  }
3992 
3993  if (!isdigit ((unsigned char) *s))
3994  return 0;
3995 
3996  displacements[0] = strtol (s, &endp, 10);
3997  s = endp;
3998 
3999  if (*s != '+' && *s != '-')
4000  {
4001  /* We are not dealing with a triplet. */
4002  return 0;
4003  }
4004 
4005  got_minus[1] = 0;
4006  if (*s == '+')
4007  ++s;
4008  else
4009  {
4010  ++s;
4011  got_minus[1] = 1;
4012  }
4013 
4014  if (!isdigit ((unsigned char) *s))
4015  return 0;
4016 
4017  displacements[1] = strtol (s, &endp, 10);
4018  s = endp;
4019 
4020  if (*s != '+' && *s != '-')
4021  {
4022  /* We are not dealing with a triplet. */
4023  return 0;
4024  }
4025 
4026  got_minus[2] = 0;
4027  if (*s == '+')
4028  ++s;
4029  else
4030  {
4031  ++s;
4032  got_minus[2] = 1;
4033  }
4034 
4035  if (!isdigit ((unsigned char) *s))
4036  return 0;
4037 
4038  displacements[2] = strtol (s, &endp, 10);
4039  s = endp;
4040 
4041  if (*s != '(' || s[1] != '%')
4042  return 0;
4043 
4044  s += 2;
4045  start = s;
4046 
4047  while (isalnum (*s))
4048  ++s;
4049 
4050  if (*s++ != ')')
4051  return 0;
4052 
4053  len = s - start - 1;
4054  regname = alloca (len + 1);
4055 
4056  strncpy (regname, start, len);
4057  regname[len] = '\0';
4058 
4059  if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1)
4060  error (_("Invalid register name `%s' on expression `%s'."),
4061  regname, p->saved_arg);
4062 
4063  for (i = 0; i < 3; i++)
4064  {
4065  write_exp_elt_opcode (&p->pstate, OP_LONG);
4067  (&p->pstate, builtin_type (gdbarch)->builtin_long);
4068  write_exp_elt_longcst (&p->pstate, displacements[i]);
4069  write_exp_elt_opcode (&p->pstate, OP_LONG);
4070  if (got_minus[i])
4071  write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4072  }
4073 
4074  write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4075  str.ptr = regname;
4076  str.length = len;
4077  write_exp_string (&p->pstate, str);
4078  write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4079 
4080  write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4082  builtin_type (gdbarch)->builtin_data_ptr);
4083  write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4084 
4085  write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4086  write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4087  write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4088 
4089  write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4092  write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4093 
4094  write_exp_elt_opcode (&p->pstate, UNOP_IND);
4095 
4096  p->arg = s;
4097 
4098  return 1;
4099  }
4100 
4101  return 0;
4102 }
4103 
4104 /* Helper function for i386_stap_parse_special_token.
4105 
4106  This function parses operands of the form `register base +
4107  (register index * size) + offset', as represented in
4108  `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4109 
4110  Return 1 if the operand was parsed successfully, zero
4111  otherwise. */
4112 
4113 static int
4115  struct stap_parse_info *p)
4116 {
4117  const char *s = p->arg;
4118 
4119  if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+')
4120  {
4121  int offset_minus = 0;
4122  long offset = 0;
4123  int size_minus = 0;
4124  long size = 0;
4125  const char *start;
4126  char *base;
4127  int len_base;
4128  char *index;
4129  int len_index;
4130  struct stoken base_token, index_token;
4131 
4132  if (*s == '+')
4133  ++s;
4134  else if (*s == '-')
4135  {
4136  ++s;
4137  offset_minus = 1;
4138  }
4139 
4140  if (offset_minus && !isdigit (*s))
4141  return 0;
4142 
4143  if (isdigit (*s))
4144  {
4145  char *endp;
4146 
4147  offset = strtol (s, &endp, 10);
4148  s = endp;
4149  }
4150 
4151  if (*s != '(' || s[1] != '%')
4152  return 0;
4153 
4154  s += 2;
4155  start = s;
4156 
4157  while (isalnum (*s))
4158  ++s;
4159 
4160  if (*s != ',' || s[1] != '%')
4161  return 0;
4162 
4163  len_base = s - start;
4164  base = alloca (len_base + 1);
4165  strncpy (base, start, len_base);
4166  base[len_base] = '\0';
4167 
4168  if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1)
4169  error (_("Invalid register name `%s' on expression `%s'."),
4170  base, p->saved_arg);
4171 
4172  s += 2;
4173  start = s;
4174 
4175  while (isalnum (*s))
4176  ++s;
4177 
4178  len_index = s - start;
4179  index = alloca (len_index + 1);
4180  strncpy (index, start, len_index);
4181  index[len_index] = '\0';
4182 
4183  if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1)
4184  error (_("Invalid register name `%s' on expression `%s'."),
4185  index, p->saved_arg);
4186 
4187  if (*s != ',' && *s != ')')
4188  return 0;
4189 
4190  if (*s == ',')
4191  {
4192  char *endp;
4193 
4194  ++s;
4195  if (*s == '+')
4196  ++s;
4197  else if (*s == '-')
4198  {
4199  ++s;
4200  size_minus = 1;
4201  }
4202 
4203  size = strtol (s, &endp, 10);
4204  s = endp;
4205 
4206  if (*s != ')')
4207  return 0;
4208  }
4209 
4210  ++s;
4211 
4212  if (offset)
4213  {
4214  write_exp_elt_opcode (&p->pstate, OP_LONG);
4216  builtin_type (gdbarch)->builtin_long);
4217  write_exp_elt_longcst (&p->pstate, offset);
4218  write_exp_elt_opcode (&p->pstate, OP_LONG);
4219  if (offset_minus)
4220  write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4221  }
4222 
4223  write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4224  base_token.ptr = base;
4225  base_token.length = len_base;
4226  write_exp_string (&p->pstate, base_token);
4227  write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4228 
4229  if (offset)
4230  write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4231 
4232  write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4233  index_token.ptr = index;
4234  index_token.length = len_index;
4235  write_exp_string (&p->pstate, index_token);
4236  write_exp_elt_opcode (&p->pstate, OP_REGISTER);
4237 
4238  if (size)
4239  {
4240  write_exp_elt_opcode (&p->pstate, OP_LONG);
4242  builtin_type (gdbarch)->builtin_long);
4243  write_exp_elt_longcst (&p->pstate, size);
4244  write_exp_elt_opcode (&p->pstate, OP_LONG);
4245  if (size_minus)
4246  write_exp_elt_opcode (&p->pstate, UNOP_NEG);
4247  write_exp_elt_opcode (&p->pstate, BINOP_MUL);
4248  }
4249 
4250  write_exp_elt_opcode (&p->pstate, BINOP_ADD);
4251 
4252  write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4255  write_exp_elt_opcode (&p->pstate, UNOP_CAST);
4256 
4257  write_exp_elt_opcode (&p->pstate, UNOP_IND);
4258 
4259  p->arg = s;
4260 
4261  return 1;
4262  }
4263 
4264  return 0;
4265 }
4266 
4267 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4268  gdbarch.h. */
4269 
4270 int
4271 i386_stap_parse_special_token (struct gdbarch *gdbarch,
4272  struct stap_parse_info *p)
4273 {
4274  /* In order to parse special tokens, we use a state-machine that go
4275  through every known token and try to get a match. */
4276  enum
4277  {
4278  TRIPLET,
4279  THREE_ARG_DISPLACEMENT,
4280  DONE
4281  };
4282  int current_state;
4283 
4284  current_state = TRIPLET;
4285 
4286  /* The special tokens to be parsed here are:
4287 
4288  - `register base + (register index * size) + offset', as represented
4289  in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4290 
4291  - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4292  `*(-8 + 3 - 1 + (void *) $eax)'. */
4293 
4294  while (current_state != DONE)
4295  {
4296  switch (current_state)
4297  {
4298  case TRIPLET:
4299  if (i386_stap_parse_special_token_triplet (gdbarch, p))
4300  return 1;
4301  break;
4302 
4303  case THREE_ARG_DISPLACEMENT:
4305  return 1;
4306  break;
4307  }
4308 
4309  /* Advancing to the next state. */
4310  ++current_state;
4311  }
4312 
4313  return 0;
4314 }
4315 
4316 
4317 
4318 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always
4319  also supplies -m64 or -m32 by gdbarch_gcc_target_options. */
4320 
4321 static const char *
4322 i386_gnu_triplet_regexp (struct gdbarch *gdbarch)
4323 {
4324  return "(x86_64|i.86)";
4325 }
4326 
4327 
4328 
4329 /* Generic ELF. */
4330 
4331 void
4332 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4333 {
4334  static const char *const stap_integer_prefixes[] = { "$", NULL };
4335  static const char *const stap_register_prefixes[] = { "%", NULL };
4336  static const char *const stap_register_indirection_prefixes[] = { "(",
4337  NULL };
4338  static const char *const stap_register_indirection_suffixes[] = { ")",
4339  NULL };
4340 
4341  /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4343 
4344  /* Registering SystemTap handlers. */
4345  set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
4346  set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
4348  stap_register_indirection_prefixes);
4350  stap_register_indirection_suffixes);
4355 
4357 }
4358 
4359 /* System V Release 4 (SVR4). */
4360 
4361 void
4362 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4363 {
4364  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4365 
4366  /* System V Release 4 uses ELF. */
4367  i386_elf_init_abi (info, gdbarch);
4368 
4369  /* System V Release 4 has shared libraries. */
4371 
4374  tdep->sc_pc_offset = 36 + 14 * 4;
4375  tdep->sc_sp_offset = 36 + 17 * 4;
4376 
4377  tdep->jb_pc_offset = 20;
4378 }
4379 
4380 /* DJGPP. */
4381 
4382 static void
4383 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
4384 {
4385  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4386 
4387  /* DJGPP doesn't have any special frames for signal handlers. */
4388  tdep->sigtramp_p = NULL;
4389 
4390  tdep->jb_pc_offset = 36;
4391 
4392  /* DJGPP does not support the SSE registers. */
4393  if (! tdesc_has_registers (info.target_desc))
4394  tdep->tdesc = tdesc_i386_mmx;
4395 
4396  /* Native compiler is GCC, which uses the SVR4 register numbering
4397  even in COFF and STABS. See the comment in i386_gdbarch_init,
4398  before the calls to set_gdbarch_stab_reg_to_regnum and
4399  set_gdbarch_sdb_reg_to_regnum. */
4402 
4404 
4406 }
4407 
4408 
4409 /* i386 register groups. In addition to the normal groups, add "mmx"
4410  and "sse". */
4411 
4414 
4415 static void
4417 {
4418  i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
4419  i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
4420 }
4421 
4422 static void
4423 i386_add_reggroups (struct gdbarch *gdbarch)
4424 {
4425  reggroup_add (gdbarch, i386_sse_reggroup);
4426  reggroup_add (gdbarch, i386_mmx_reggroup);
4427  reggroup_add (gdbarch, general_reggroup);
4428  reggroup_add (gdbarch, float_reggroup);
4429  reggroup_add (gdbarch, all_reggroup);
4430  reggroup_add (gdbarch, save_reggroup);
4431  reggroup_add (gdbarch, restore_reggroup);
4432  reggroup_add (gdbarch, vector_reggroup);
4433  reggroup_add (gdbarch, system_reggroup);
4434 }
4435 
4436 int
4437 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
4438  struct reggroup *group)
4439 {
4440  const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4441  int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p,
4442  ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p,
4443  bndr_regnum_p, bnd_regnum_p, k_regnum_p, zmm_regnum_p, zmmh_regnum_p,
4444  zmm_avx512_regnum_p, mpx_ctrl_regnum_p, xmm_avx512_regnum_p,
4445  avx512_p, avx_p, sse_p;
4446 
4447  /* Don't include pseudo registers, except for MMX, in any register
4448  groups. */
4449  if (i386_byte_regnum_p (gdbarch, regnum))
4450  return 0;
4451 
4452  if (i386_word_regnum_p (gdbarch, regnum))
4453  return 0;
4454 
4455  if (i386_dword_regnum_p (gdbarch, regnum))
4456  return 0;
4457 
4458  mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum);
4459  if (group == i386_mmx_reggroup)
4460  return mmx_regnum_p;
4461 
4462  xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum);
4463  xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum);
4464  mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum);
4465  if (group == i386_sse_reggroup)
4466  return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p;
4467 
4468  ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum);
4469  ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum);
4470  zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum);
4471 
4472  avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4474  avx_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4475  == X86_XSTATE_AVX_MASK) && !avx512_p;
4476  sse_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK)
4477  == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p;
4478 
4479  if (group == vector_reggroup)
4480  return (mmx_regnum_p
4481  || (zmm_regnum_p && avx512_p)
4482  || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p)
4483  || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p)
4484  || mxcsr_regnum_p);
4485 
4486  fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum)
4487  || i386_fpc_regnum_p (gdbarch, regnum));
4488  if (group == float_reggroup)
4489  return fp_regnum_p;
4490 
4491  /* For "info reg all", don't include upper YMM registers nor XMM
4492  registers when AVX is supported. */
4493  ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum);
4494  ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum);
4495  zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum);
4496  if (group == all_reggroup
4497  && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p)
4498  || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p)
4499  || ymmh_regnum_p
4500  || ymmh_avx512_regnum_p
4501  || zmmh_regnum_p))
4502  return 0;
4503 
4504  bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum);
4505  if (group == all_reggroup
4506  && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4507  return bnd_regnum_p;
4508 
4509  bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum);
4510  if (group == all_reggroup
4511  && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4512  return 0;
4513 
4514  mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum);
4515  if (group == all_reggroup
4516  && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK))))
4517  return mpx_ctrl_regnum_p;
4518 
4519  if (group == general_reggroup)
4520  return (!fp_regnum_p
4521  && !mmx_regnum_p
4522  && !mxcsr_regnum_p
4523  && !xmm_regnum_p
4524  && !xmm_avx512_regnum_p
4525  && !ymm_regnum_p
4526  && !ymmh_regnum_p
4527  && !ymm_avx512_regnum_p
4528  && !ymmh_avx512_regnum_p
4529  && !bndr_regnum_p
4530  && !bnd_regnum_p
4531  && !mpx_ctrl_regnum_p
4532  && !zmm_regnum_p
4533  && !zmmh_regnum_p);
4534 
4535  return default_register_reggroup_p (gdbarch, regnum, group);
4536 }
4537 
4538 
4539 /* Get the ARGIth function argument for the current function. */
4540 
4541 static CORE_ADDR
4542 i386_fetch_pointer_argument (struct frame_info *frame, int argi,
4543  struct type *type)
4544 {
4545  struct gdbarch *gdbarch = get_frame_arch (frame);
4546  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4548  return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order);
4549 }
4550 
4551 #define PREFIX_REPZ 0x01
4552 #define PREFIX_REPNZ 0x02
4553 #define PREFIX_LOCK 0x04
4554 #define PREFIX_DATA 0x08
4555 #define PREFIX_ADDR 0x10
4556 
4557 /* operand size */
4558 enum
4559 {
4560  OT_BYTE = 0,
4565 };
4566 
4567 /* i386 arith/logic operations */
4568 enum
4569 {
4578 };
4579 
4581 {
4582  struct gdbarch *gdbarch;
4586  int aflag;
4587  int dflag;
4588  int override;
4589  uint8_t modrm;
4590  uint8_t mod, reg, rm;
4591  int ot;
4592  uint8_t rex_x;
4593  uint8_t rex_b;
4596  const int *regmap;
4597 };
4598 
4599 /* Parse the "modrm" part of the memory address irp->addr points at.
4600  Returns -1 if something goes wrong, 0 otherwise. */
4601 
4602 static int
4604 {
4605  struct gdbarch *gdbarch = irp->gdbarch;
4606 
4607  if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1))
4608  return -1;
4609 
4610  irp->addr++;
4611  irp->mod = (irp->modrm >> 6) & 3;
4612  irp->reg = (irp->modrm >> 3) & 7;
4613  irp->rm = irp->modrm & 7;
4614 
4615  return 0;
4616 }
4617 
4618 /* Extract the memory address that the current instruction writes to,
4619  and return it in *ADDR. Return -1 if something goes wrong. */
4620 
4621 static int
4622 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr)
4623 {
4624  struct gdbarch *gdbarch = irp->gdbarch;
4625  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4626  gdb_byte buf[4];
4627  ULONGEST offset64;
4628 
4629  *addr = 0;
4630  if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM])
4631  {
4632  /* 32/64 bits */
4633  int havesib = 0;
4634  uint8_t scale = 0;
4635  uint8_t byte;
4636  uint8_t index = 0;
4637  uint8_t base = irp->rm;
4638 
4639  if (base == 4)
4640  {
4641  havesib = 1;
4642  if (record_read_memory (gdbarch, irp->addr, &byte, 1))
4643  return -1;
4644  irp->addr++;
4645  scale = (byte >> 6) & 3;
4646  index = ((byte >> 3) & 7) | irp->rex_x;
4647  base = (byte & 7);
4648  }
4649  base |= irp->rex_b;
4650 
4651  switch (irp->mod)
4652  {
4653  case 0:
4654  if ((base & 7) == 5)
4655  {
4656  base = 0xff;
4657  if (record_read_memory (gdbarch, irp->addr, buf, 4))
4658  return -1;
4659  irp->addr += 4;
4660  *addr = extract_signed_integer (buf, 4, byte_order);
4661  if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib)
4662  *addr += irp->addr + irp->rip_offset;
4663  }
4664  break;
4665  case 1:
4666  if (record_read_memory (gdbarch, irp->addr, buf, 1))
4667  return -1;
4668  irp->addr++;
4669  *addr = (int8_t) buf[0];
4670  break;
4671  case 2:
4672  if (record_read_memory (gdbarch, irp->addr, buf, 4))
4673  return -1;
4674  *addr = extract_signed_integer (buf, 4, byte_order);
4675  irp->addr += 4;
4676  break;
4677  }
4678 
4679  offset64 = 0;
4680  if (base != 0xff)
4681  {
4682  if (base == 4 && irp->popl_esp_hack)
4683  *addr += irp->popl_esp_hack;
4684  regcache_raw_read_unsigned (irp->regcache, irp->regmap[base],
4685  &offset64);
4686  }
4687  if (irp->aflag == 2)
4688  {
4689  *addr += offset64;
4690  }
4691  else
4692  *addr = (uint32_t) (offset64 + *addr);
4693 
4694  if (havesib && (index != 4 || scale != 0))
4695  {
4696  regcache_raw_read_unsigned (irp->regcache, irp->regmap[index],
4697  &offset64);
4698  if (irp->aflag == 2)
4699  *addr += offset64 << scale;
4700  else
4701  *addr = (uint32_t) (*addr + (offset64 << scale));
4702  }
4703 
4704  if (!irp->aflag)
4705  {
4706  /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4707  address from 32-bit to 64-bit. */
4708  *addr = (uint32_t) *addr;
4709  }
4710  }
4711  else
4712  {
4713  /* 16 bits */
4714  switch (irp->mod)
4715  {
4716  case 0:
4717  if (irp->rm == 6)
4718  {
4719  if (record_read_memory (gdbarch, irp->addr, buf, 2))
4720  return -1;
4721  irp->addr += 2;
4722  *addr = extract_signed_integer (buf, 2, byte_order);
4723  irp->rm = 0;
4724  goto no_rm;
4725  }
4726  break;
4727  case 1:
4728  if (record_read_memory (gdbarch, irp->addr, buf, 1))
4729  return -1;
4730  irp->addr++;
4731  *addr = (int8_t) buf[0];
4732  break;
4733  case 2:
4734  if (record_read_memory (gdbarch, irp->addr, buf, 2))
4735  return -1;
4736  irp->addr += 2;
4737  *addr = extract_signed_integer (buf, 2, byte_order);
4738  break;
4739  }
4740 
4741  switch (irp->rm)
4742  {
4743  case 0:
4746  &offset64);
4747  *addr = (uint32_t) (*addr + offset64);
4750  &offset64);
4751  *addr = (uint32_t) (*addr + offset64);
4752  break;
4753  case 1:
4756  &offset64);
4757  *addr = (uint32_t) (*addr + offset64);
4760  &offset64);
4761  *addr = (uint32_t) (*addr + offset64);
4762  break;
4763  case 2:
4766  &offset64);
4767  *addr = (uint32_t) (*addr + offset64);
4770  &offset64);
4771  *addr = (uint32_t) (*addr + offset64);
4772  break;
4773  case 3:
4776  &offset64);
4777  *addr = (uint32_t) (*addr + offset64);
4780  &offset64);
4781  *addr = (uint32_t) (*addr + offset64);
4782  break;
4783  case 4:
4786  &offset64);
4787  *addr = (uint32_t) (*addr + offset64);
4788  break;
4789  case 5:
4792  &offset64);
4793  *addr = (uint32_t) (*addr + offset64);
4794  break;
4795  case 6:
4798  &offset64);
4799  *addr = (uint32_t) (*addr + offset64);
4800  break;
4801  case 7:
4804  &offset64);
4805  *addr = (uint32_t) (*addr + offset64);
4806  break;
4807  }
4808  *addr &= 0xffff;
4809  }
4810 
4811  no_rm:
4812  return 0;
4813 }
4814 
4815 /* Record the address and contents of the memory that will be changed
4816  by the current instruction. Return -1 if something goes wrong, 0
4817  otherwise. */
4818 
4819 static int
4821 {
4822  struct gdbarch *gdbarch = irp->gdbarch;
4823  uint64_t addr;
4824 
4825  if (irp->override >= 0)
4826  {
4828  {
4829  int q;
4830 
4832  q = yquery (_("\
4833 Process record ignores the memory change of instruction at address %s\n\
4834 because it can't get the value of the segment register.\n\
4835 Do you want to stop the program?"),
4836  paddress (gdbarch, irp->orig_addr));
4838  if (q)
4839  return -1;
4840  }
4841 
4842  return 0;
4843  }
4844 
4845  if (i386_record_lea_modrm_addr (irp, &addr))
4846  return -1;
4847 
4848  if (record_full_arch_list_add_mem (addr, 1 << irp->ot))
4849  return -1;
4850 
4851  return 0;
4852 }
4853 
4854 /* Record the effects of a push operation. Return -1 if something
4855  goes wrong, 0 otherwise. */
4856 
4857 static int
4859 {
4860  ULONGEST addr;
4861 
4864  return -1;
4867  &addr);
4868  if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size))
4869  return -1;
4870 
4871  return 0;
4872 }
4873 
4874 
4875 /* Defines contents to record. */
4876 #define I386_SAVE_FPU_REGS 0xfffd
4877 #define I386_SAVE_FPU_ENV 0xfffe
4878 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4879 
4880 /* Record the values of the floating point registers which will be
4881  changed by the current instruction. Returns -1 if something is
4882  wrong, 0 otherwise. */
4883 
4884 static int i386_record_floats (struct gdbarch *gdbarch,
4885  struct i386_record_s *ir,
4886  uint32_t iregnum)
4887 {
4888  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4889  int i;
4890 
4891  /* Oza: Because of floating point insn push/pop of fpu stack is going to
4892  happen. Currently we store st0-st7 registers, but we need not store all
4893  registers all the time, in future we use ftag register and record only
4894  those who are not marked as an empty. */
4895 
4896  if (I386_SAVE_FPU_REGS == iregnum)
4897  {
4898  for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++)
4899  {
4901  return -1;
4902  }
4903  }
4904  else if (I386_SAVE_FPU_ENV == iregnum)
4905  {
4906  for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4907  {
4909  return -1;
4910  }
4911  }
4912  else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum)
4913  {
4914  for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4915  {
4917  return -1;
4918  }
4919  }
4920  else if ((iregnum >= I387_ST0_REGNUM (tdep)) &&
4921  (iregnum <= I387_FOP_REGNUM (tdep)))
4922  {
4923  if (record_full_arch_list_add_reg (ir->regcache,iregnum))
4924  return -1;
4925  }
4926  else
4927  {
4928  /* Parameter error. */
4929  return -1;
4930  }
4931  if(I386_SAVE_FPU_ENV != iregnum)
4932  {
4933  for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++)
4934  {
4936  return -1;
4937  }
4938  }
4939  return 0;
4940 }
4941 
4942 /* Parse the current instruction, and record the values of the
4943  registers and memory that will be changed by the current
4944  instruction. Returns -1 if something goes wrong, 0 otherwise. */
4945 
4946 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
4947  record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
4948 
4949 int
4950 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
4951  CORE_ADDR input_addr)
4952 {
4953  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4954  int prefixes = 0;
4955  int regnum = 0;
4956  uint32_t opcode;
4957  uint8_t opcode8;
4958  ULONGEST addr;
4960  struct i386_record_s ir;
4961  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4962  uint8_t rex_w = -1;
4963  uint8_t rex_r = 0;
4964 
4965  memset (&ir, 0, sizeof (struct i386_record_s));
4966  ir.regcache = regcache;
4967  ir.addr = input_addr;
4968  ir.orig_addr = input_addr;
4969  ir.aflag = 1;
4970  ir.dflag = 1;
4971  ir.override = -1;
4972  ir.popl_esp_hack = 0;
4973  ir.regmap = tdep->record_regmap;
4974  ir.gdbarch = gdbarch;
4975 
4976  if (record_debug > 1)
4977  fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record "
4978  "addr = %s\n",
4979  paddress (gdbarch, ir.addr));
4980 
4981  /* prefixes */
4982  while (1)
4983  {
4984  if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
4985  return -1;
4986  ir.addr++;
4987  switch (opcode8) /* Instruction prefixes */
4988  {
4989  case REPE_PREFIX_OPCODE:
4990  prefixes |= PREFIX_REPZ;
4991  break;
4992  case REPNE_PREFIX_OPCODE:
4993  prefixes |= PREFIX_REPNZ;
4994  break;
4995  case LOCK_PREFIX_OPCODE:
4996  prefixes |= PREFIX_LOCK;
4997  break;
4998  case CS_PREFIX_OPCODE:
5000  break;
5001  case SS_PREFIX_OPCODE:
5003  break;
5004  case DS_PREFIX_OPCODE:
5006  break;
5007  case ES_PREFIX_OPCODE:
5009  break;
5010  case FS_PREFIX_OPCODE:
5012  break;
5013  case GS_PREFIX_OPCODE:
5015  break;
5016  case DATA_PREFIX_OPCODE:
5017  prefixes |= PREFIX_DATA;
5018  break;
5019  case ADDR_PREFIX_OPCODE:
5020  prefixes |= PREFIX_ADDR;
5021  break;
5022  case 0x40: /* i386 inc %eax */
5023  case 0x41: /* i386 inc %ecx */
5024  case 0x42: /* i386 inc %edx */
5025  case 0x43: /* i386 inc %ebx */
5026  case 0x44: /* i386 inc %esp */
5027  case 0x45: /* i386 inc %ebp */
5028  case 0x46: /* i386 inc %esi */
5029  case 0x47: /* i386 inc %edi */
5030  case 0x48: /* i386 dec %eax */
5031  case 0x49: /* i386 dec %ecx */
5032  case 0x4a: /* i386 dec %edx */
5033  case 0x4b: /* i386 dec %ebx */
5034  case 0x4c: /* i386 dec %esp */
5035  case 0x4d: /* i386 dec %ebp */
5036  case 0x4e: /* i386 dec %esi */
5037  case 0x4f: /* i386 dec %edi */
5038  if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */
5039  {
5040  /* REX */
5041  rex_w = (opcode8 >> 3) & 1;
5042  rex_r = (opcode8 & 0x4) << 1;
5043  ir.rex_x = (opcode8 & 0x2) << 2;
5044  ir.rex_b = (opcode8 & 0x1) << 3;
5045  }
5046  else /* 32 bit target */
5047  goto out_prefixes;
5048  break;
5049  default:
5050  goto out_prefixes;
5051  break;
5052  }
5053  }
5054  out_prefixes:
5055  if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1)
5056  {
5057  ir.dflag = 2;
5058  }
5059  else
5060  {
5061  if (prefixes & PREFIX_DATA)
5062  ir.dflag ^= 1;
5063  }
5064  if (prefixes & PREFIX_ADDR)
5065  ir.aflag ^= 1;
5066  else if (ir.regmap[X86_RECORD_R8_REGNUM])
5067  ir.aflag = 2;
5068 
5069  /* Now check op code. */
5070  opcode = (uint32_t) opcode8;
5071  reswitch:
5072  switch (opcode)
5073  {
5074  case 0x0f:
5075  if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
5076  return -1;
5077  ir.addr++;
5078  opcode = (uint32_t) opcode8 | 0x0f00;
5079  goto reswitch;
5080  break;
5081 
5082  case 0x00: /* arith & logic */
5083  case 0x01:
5084  case 0x02:
5085  case 0x03:
5086  case 0x04:
5087  case 0x05:
5088  case 0x08:
5089  case 0x09:
5090  case 0x0a:
5091  case 0x0b:
5092  case 0x0c:
5093  case 0x0d:
5094  case 0x10:
5095  case 0x11:
5096  case 0x12:
5097  case 0x13:
5098  case 0x14:
5099  case 0x15:
5100  case 0x18:
5101  case 0x19:
5102  case 0x1a:
5103  case 0x1b:
5104  case 0x1c:
5105  case 0x1d:
5106  case 0x20:
5107  case 0x21:
5108  case 0x22:
5109  case 0x23:
5110  case 0x24:
5111  case 0x25:
5112  case 0x28:
5113  case 0x29:
5114  case 0x2a:
5115  case 0x2b:
5116  case 0x2c:
5117  case 0x2d:
5118  case 0x30:
5119  case 0x31:
5120  case 0x32:
5121  case 0x33:
5122  case 0x34:
5123  case 0x35:
5124  case 0x38:
5125  case 0x39:
5126  case 0x3a:
5127  case 0x3b:
5128  case 0x3c:
5129  case 0x3d:
5130  if (((opcode >> 3) & 7) != OP_CMPL)
5131  {
5132  if ((opcode & 1) == 0)
5133  ir.ot = OT_BYTE;
5134  else
5135  ir.ot = ir.dflag + OT_WORD;
5136 
5137  switch ((opcode >> 1) & 3)
5138  {
5139  case 0: /* OP Ev, Gv */
5140  if (i386_record_modrm (&ir))
5141  return -1;
5142  if (ir.mod != 3)
5143  {
5144  if (i386_record_lea_modrm (&ir))
5145  return -1;
5146  }
5147  else
5148  {
5149  ir.rm |= ir.rex_b;
5150  if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5151  ir.rm &= 0x3;
5153  }
5154  break;
5155  case 1: /* OP Gv, Ev */
5156  if (i386_record_modrm (&ir))
5157  return -1;
5158  ir.reg |= rex_r;
5159  if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5160  ir.reg &= 0x3;
5162  break;
5163  case 2: /* OP A, Iv */
5165  break;
5166  }
5167  }
5169  break;
5170 
5171  case 0x80: /* GRP1 */
5172  case 0x81:
5173  case 0x82:
5174  case 0x83:
5175  if (i386_record_modrm (&ir))
5176  return -1;
5177 
5178  if (ir.reg != OP_CMPL)
5179  {
5180  if ((opcode & 1) == 0)
5181  ir.ot = OT_BYTE;
5182  else
5183  ir.ot = ir.dflag + OT_WORD;
5184 
5185  if (ir.mod != 3)
5186  {
5187  if (opcode == 0x83)
5188  ir.rip_offset = 1;
5189  else
5190  ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5191  if (i386_record_lea_modrm (&ir))
5192  return -1;
5193  }
5194  else
5196  }
5198  break;
5199 
5200  case 0x40: /* inc */
5201  case 0x41:
5202  case 0x42:
5203  case 0x43:
5204  case 0x44:
5205  case 0x45:
5206  case 0x46:
5207  case 0x47:
5208 
5209  case 0x48: /* dec */
5210  case 0x49:
5211  case 0x4a:
5212  case 0x4b:
5213  case 0x4c:
5214  case 0x4d:
5215  case 0x4e:
5216  case 0x4f:
5217 
5220  break;
5221 
5222  case 0xf6: /* GRP3 */
5223  case 0xf7:
5224  if ((opcode & 1) == 0)
5225  ir.ot = OT_BYTE;
5226  else
5227  ir.ot = ir.dflag + OT_WORD;
5228  if (i386_record_modrm (&ir))
5229  return -1;
5230 
5231  if (ir.mod != 3 && ir.reg == 0)
5232  ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5233 
5234  switch (ir.reg)
5235  {
5236  case 0: /* test */
5238  break;
5239  case 2: /* not */
5240  case 3: /* neg */
5241  if (ir.mod != 3)
5242  {
5243  if (i386_record_lea_modrm (&ir))
5244  return -1;
5245  }
5246  else
5247  {
5248  ir.rm |= ir.rex_b;
5249  if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5250  ir.rm &= 0x3;
5252  }
5253  if (ir.reg == 3) /* neg */
5255  break;
5256  case 4: /* mul */
5257  case 5: /* imul */
5258  case 6: /* div */
5259  case 7: /* idiv */
5261  if (ir.ot != OT_BYTE)
5264  break;
5265  default:
5266  ir.addr -= 2;
5267  opcode = opcode << 8 | ir.modrm;
5268  goto no_support;
5269  break;
5270  }
5271  break;
5272 
5273  case 0xfe: /* GRP4 */
5274  case 0xff: /* GRP5 */
5275  if (i386_record_modrm (&ir))
5276  return -1;
5277  if (ir.reg >= 2 && opcode == 0xfe)
5278  {
5279  ir.addr -= 2;
5280  opcode = opcode << 8 | ir.modrm;
5281  goto no_support;
5282  }
5283  switch (ir.reg)
5284  {
5285  case 0: /* inc */
5286  case 1: /* dec */
5287  if ((opcode & 1) == 0)
5288  ir.ot = OT_BYTE;
5289  else
5290  ir.ot = ir.dflag + OT_WORD;
5291  if (ir.mod != 3)
5292  {
5293  if (i386_record_lea_modrm (&ir))
5294  return -1;
5295  }
5296  else
5297  {
5298  ir.rm |= ir.rex_b;
5299  if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5300  ir.rm &= 0x3;
5302  }
5304  break;
5305  case 2: /* call */
5306  if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5307  ir.dflag = 2;
5308  if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5309  return -1;
5311  break;
5312  case 3: /* lcall */
5314  if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5315  return -1;
5317  break;
5318  case 4: /* jmp */
5319  case 5: /* ljmp */
5321  break;
5322  case 6: /* push */
5323  if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5324  ir.dflag = 2;
5325  if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5326  return -1;
5327  break;
5328  default:
5329  ir.addr -= 2;
5330  opcode = opcode << 8 | ir.modrm;
5331  goto no_support;
5332  break;
5333  }
5334  break;
5335 
5336  case 0x84: /* test */
5337  case 0x85:
5338  case 0xa8:
5339  case 0xa9:
5341  break;
5342 
5343  case 0x98: /* CWDE/CBW */
5345  break;
5346 
5347  case 0x99: /* CDQ/CWD */
5350  break;
5351 
5352  case 0x0faf: /* imul */
5353  case 0x69:
5354  case 0x6b:
5355  ir.ot = ir.dflag + OT_WORD;
5356  if (i386_record_modrm (&ir))
5357  return -1;
5358  if (opcode == 0x69)
5359  ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5360  else if (opcode == 0x6b)
5361  ir.rip_offset = 1;
5362  ir.reg |= rex_r;
5363  if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5364  ir.reg &= 0x3;
5367  break;
5368 
5369  case 0x0fc0: /* xadd */
5370  case 0x0fc1:
5371  if ((opcode & 1) == 0)
5372  ir.ot = OT_BYTE;
5373  else
5374  ir.ot = ir.dflag + OT_WORD;
5375  if (i386_record_modrm (&ir))
5376  return -1;
5377  ir.reg |= rex_r;
5378  if (ir.mod == 3)
5379  {
5380  if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5381  ir.reg &= 0x3;
5383  if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5384  ir.rm &= 0x3;
5386  }
5387  else
5388  {
5389  if (i386_record_lea_modrm (&ir))
5390  return -1;
5391  if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5392  ir.reg &= 0x3;
5394  }
5396  break;
5397 
5398  case 0x0fb0: /* cmpxchg */
5399  case 0x0fb1:
5400  if ((opcode & 1) == 0)
5401  ir.ot = OT_BYTE;
5402  else
5403  ir.ot = ir.dflag + OT_WORD;
5404  if (i386_record_modrm (&ir))
5405  return -1;
5406  if (ir.mod == 3)
5407  {
5408  ir.reg |= rex_r;
5410  if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5411  ir.reg &= 0x3;
5413  }
5414  else
5415  {
5417  if (i386_record_lea_modrm (&ir))
5418  return -1;
5419  }
5421  break;
5422 
5423  case 0x0fc7: /* cmpxchg8b */
5424  if (i386_record_modrm (&ir))
5425  return -1;
5426  if (ir.mod == 3)
5427  {
5428  ir.addr -= 2;
5429  opcode = opcode << 8 | ir.modrm;
5430  goto no_support;
5431  }
5434  if (i386_record_lea_modrm (&ir))
5435  return -1;
5437  break;
5438 
5439  case 0x50: /* push */
5440  case 0x51:
5441  case 0x52:
5442  case 0x53:
5443  case 0x54:
5444  case 0x55:
5445  case 0x56:
5446  case 0x57:
5447  case 0x68:
5448  case 0x6a:
5449  if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5450  ir.dflag = 2;
5451  if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5452  return -1;
5453  break;
5454 
5455  case 0x06: /* push es */
5456  case 0x0e: /* push cs */
5457  case 0x16: /* push ss */
5458  case 0x1e: /* push ds */
5459  if (ir.regmap[X86_RECORD_R8_REGNUM])
5460  {
5461  ir.addr -= 1;
5462  goto no_support;
5463  }
5464  if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5465  return -1;
5466  break;
5467 
5468  case 0x0fa0: /* push fs */
5469  case 0x0fa8: /* push gs */
5470  if (ir.regmap[X86_RECORD_R8_REGNUM])
5471  {
5472  ir.addr -= 2;
5473  goto no_support;
5474  }
5475  if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5476  return -1;
5477  break;
5478 
5479  case 0x60: /* pusha */
5480  if (ir.regmap[X86_RECORD_R8_REGNUM])
5481  {
5482  ir.addr -= 1;
5483  goto no_support;
5484  }
5485  if (i386_record_push (&ir, 1 << (ir.dflag + 4)))
5486  return -1;
5487  break;
5488 
5489  case 0x58: /* pop */
5490  case 0x59:
5491  case 0x5a:
5492  case 0x5b:
5493  case 0x5c:
5494  case 0x5d:
5495  case 0x5e:
5496  case 0x5f:
5498  I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5499  break;
5500 
5501  case 0x61: /* popa */
5502  if (ir.regmap[X86_RECORD_R8_REGNUM])
5503  {
5504  ir.addr -= 1;
5505  goto no_support;
5506  }
5507  for (regnum = X86_RECORD_REAX_REGNUM;
5508  regnum <= X86_RECORD_REDI_REGNUM;
5509  regnum++)
5511  break;
5512 
5513  case 0x8f: /* pop */
5514  if (ir.regmap[X86_RECORD_R8_REGNUM])
5515  ir.ot = ir.dflag ? OT_QUAD : OT_WORD;
5516  else
5517  ir.ot = ir.dflag + OT_WORD;
5518  if (i386_record_modrm (&ir))
5519  return -1;
5520  if (ir.mod == 3)
5522  else
5523  {
5524  ir.popl_esp_hack = 1 << ir.ot;
5525  if (i386_record_lea_modrm (&ir))
5526  return -1;
5527  }
5529  break;
5530 
5531  case 0xc8: /* enter */
5533  if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
5534  ir.dflag = 2;
5535  if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
5536  return -1;
5537  break;
5538 
5539  case 0xc9: /* leave */
5542  break;
5543 
5544  case 0x07: /* pop es */
5545  if (ir.regmap[X86_RECORD_R8_REGNUM])
5546  {
5547  ir.addr -= 1;
5548  goto no_support;
5549  }
5553  break;
5554 
5555  case 0x17: /* pop ss */
5556  if (ir.regmap[X86_RECORD_R8_REGNUM])
5557  {
5558  ir.addr -= 1;
5559  goto no_support;
5560  }
5564  break;
5565 
5566  case 0x1f: /* pop ds */
5567  if (ir.regmap[X86_RECORD_R8_REGNUM])
5568  {
5569  ir.addr -= 1;
5570  goto no_support;
5571  }
5575  break;
5576 
5577  case 0x0fa1: /* pop fs */
5581  break;
5582 
5583  case 0x0fa9: /* pop gs */
5587  break;
5588 
5589  case 0x88: /* mov */
5590  case 0x89:
5591  case 0xc6:
5592  case 0xc7:
5593  if ((opcode & 1) == 0)
5594  ir.ot = OT_BYTE;
5595  else
5596  ir.ot = ir.dflag + OT_WORD;
5597 
5598  if (i386_record_modrm (&ir))
5599  return -1;
5600 
5601  if (ir.mod != 3)
5602  {
5603  if (opcode == 0xc6 || opcode == 0xc7)
5604  ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot);
5605  if (i386_record_lea_modrm (&ir))
5606  return -1;
5607  }
5608  else
5609  {
5610  if (opcode == 0xc6 || opcode == 0xc7)
5611  ir.rm |= ir.rex_b;
5612  if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5613  ir.rm &= 0x3;
5615  }
5616  break;
5617 
5618  case 0x8a: /* mov */
5619  case 0x8b:
5620  if ((opcode & 1) == 0)
5621  ir.ot = OT_BYTE;
5622  else
5623  ir.ot = ir.dflag + OT_WORD;
5624  if (i386_record_modrm (&ir))
5625  return -1;
5626  ir.reg |= rex_r;
5627  if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5628  ir.reg &= 0x3;
5630  break;
5631 
5632  case 0x8c: /* mov seg */
5633  if (i386_record_modrm (&ir))
5634  return -1;
5635  if (ir.reg > 5)
5636  {
5637  ir.addr -= 2;
5638  opcode = opcode << 8 | ir.modrm;
5639  goto no_support;
5640  }
5641 
5642  if (ir.mod == 3)
5644  else
5645  {
5646  ir.ot = OT_WORD;
5647  if (i386_record_lea_modrm (&ir))
5648  return -1;
5649  }
5650  break;
5651 
5652  case 0x8e: /* mov seg */
5653  if (i386_record_modrm (&ir))
5654  return -1;
5655  switch (ir.reg)
5656  {
5657  case 0:
5658  regnum = X86_RECORD_ES_REGNUM;
5659  break;
5660  case 2:
5661  regnum = X86_RECORD_SS_REGNUM;
5662  break;
5663  case 3:
5664  regnum = X86_RECORD_DS_REGNUM;
5665  break;
5666  case 4:
5667  regnum = X86_RECORD_FS_REGNUM;
5668  break;
5669  case 5:
5670  regnum = X86_RECORD_GS_REGNUM;
5671  break;
5672  default:
5673  ir.addr -= 2;
5674  opcode = opcode << 8 | ir.modrm;
5675  goto no_support;
5676  break;
5677  }
5680  break;
5681 
5682  case 0x0fb6: /* movzbS */
5683  case 0x0fb7: /* movzwS */
5684  case 0x0fbe: /* movsbS */
5685  case 0x0fbf: /* movswS */
5686  if (i386_record_modrm (&ir))
5687  return -1;
5689  break;
5690 
5691  case 0x8d: /* lea */
5692  if (i386_record_modrm (&ir))
5693  return -1;
5694  if (ir.mod == 3)
5695  {
5696  ir.addr -= 2;
5697  opcode = opcode << 8 | ir.modrm;
5698  goto no_support;
5699  }
5700  ir.ot = ir.dflag;
5701  ir.reg |= rex_r;
5702  if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5703  ir.reg &= 0x3;
5705  break;
5706 
5707  case 0xa0: /* mov EAX */
5708  case 0xa1:
5709 
5710  case 0xd7: /* xlat */
5712  break;
5713 
5714  case 0xa2: /* mov EAX */
5715  case 0xa3:
5716  if (ir.override >= 0)
5717  {
5719  {
5720  int q;
5721 
5723  q = yquery (_("\
5724 Process record ignores the memory change of instruction at address %s\n\
5725 because it can't get the value of the segment register.\n\
5726 Do you want to stop the program?"),
5727  paddress (gdbarch, ir.orig_addr));
5729  if (q)
5730  return -1;
5731  }
5732  }
5733  else
5734  {
5735  if ((opcode & 1) == 0)
5736  ir.ot = OT_BYTE;
5737  else
5738  ir.ot = ir.dflag + OT_WORD;
5739  if (ir.aflag == 2)
5740  {
5741  if (record_read_memory (gdbarch, ir.addr, buf, 8))
5742  return -1;
5743  ir.addr += 8;
5744  addr = extract_unsigned_integer (buf, 8, byte_order);
5745  }
5746  else if (ir.aflag)
5747  {
5748  if (record_read_memory (gdbarch, ir.addr, buf, 4))
5749  return -1;
5750  ir.addr += 4;
5751  addr = extract_unsigned_integer (buf, 4, byte_order);
5752  }
5753  else
5754  {
5755  if (record_read_memory (gdbarch, ir.addr, buf, 2))
5756  return -1;
5757  ir.addr += 2;
5758  addr = extract_unsigned_integer (buf, 2, byte_order);
5759  }
5760  if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
5761  return -1;
5762  }
5763  break;
5764 
5765  case 0xb0: /* mov R, Ib */
5766  case 0xb1:
5767  case 0xb2:
5768  case 0xb3:
5769  case 0xb4:
5770  case 0xb5:
5771  case 0xb6:
5772  case 0xb7:
5774  ? ((opcode & 0x7) | ir.rex_b)
5775  : ((opcode & 0x7) & 0x3));
5776  break;
5777 
5778  case 0xb8: /* mov R, Iv */
5779  case 0xb9:
5780  case 0xba:
5781  case 0xbb:
5782  case 0xbc:
5783  case 0xbd:
5784  case 0xbe:
5785  case 0xbf:
5786  I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b);
5787  break;
5788 
5789  case 0x91: /* xchg R, EAX */
5790  case 0x92:
5791  case 0x93:
5792  case 0x94:
5793  case 0x95:
5794  case 0x96:
5795  case 0x97:
5797  I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7);
5798  break;
5799 
5800  case 0x86: /* xchg Ev, Gv */
5801  case 0x87:
5802  if ((opcode & 1) == 0)
5803  ir.ot = OT_BYTE;
5804  else
5805  ir.ot = ir.dflag + OT_WORD;
5806  if (i386_record_modrm (&ir))
5807  return -1;
5808  if (ir.mod == 3)
5809  {
5810  ir.rm |= ir.rex_b;
5811  if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5812  ir.rm &= 0x3;
5814  }
5815  else
5816  {
5817  if (i386_record_lea_modrm (&ir))
5818  return -1;
5819  }
5820  ir.reg |= rex_r;
5821  if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5822  ir.reg &= 0x3;
5824  break;
5825 
5826  case 0xc4: /* les Gv */
5827  case 0xc5: /* lds Gv */
5828  if (ir.regmap[X86_RECORD_R8_REGNUM])
5829  {
5830  ir.addr -= 1;
5831  goto no_support;
5832  }
5833  /* FALLTHROUGH */
5834  case 0x0fb2: /* lss Gv */
5835  case 0x0fb4: /* lfs Gv */
5836  case 0x0fb5: /* lgs Gv */
5837  if (i386_record_modrm (&ir))
5838  return -1;
5839  if (ir.mod == 3)
5840  {
5841  if (opcode > 0xff)
5842  ir.addr -= 3;
5843  else
5844  ir.addr -= 2;
5845  opcode = opcode << 8 | ir.modrm;
5846  goto no_support;
5847  }
5848  switch (opcode)
5849  {
5850  case 0xc4: /* les Gv */
5851  regnum = X86_RECORD_ES_REGNUM;
5852  break;
5853  case 0xc5: /* lds Gv */
5854  regnum = X86_RECORD_DS_REGNUM;
5855  break;
5856  case 0x0fb2: /* lss Gv */
5857  regnum = X86_RECORD_SS_REGNUM;
5858  break;
5859  case 0x0fb4: /* lfs Gv */
5860  regnum = X86_RECORD_FS_REGNUM;
5861  break;
5862  case 0x0fb5: /* lgs Gv */
5863  regnum = X86_RECORD_GS_REGNUM;
5864  break;
5865  }
5869  break;
5870 
5871  case 0xc0: /* shifts */
5872  case 0xc1:
5873  case 0xd0:
5874  case 0xd1:
5875  case 0xd2:
5876  case 0xd3:
5877  if ((opcode & 1) == 0)
5878  ir.ot = OT_BYTE;
5879  else
5880  ir.ot = ir.dflag + OT_WORD;
5881  if (i386_record_modrm (&ir))
5882  return -1;
5883  if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3))
5884  {
5885  if (i386_record_lea_modrm (&ir))
5886  return -1;
5887  }
5888  else
5889  {
5890  ir.rm |= ir.rex_b;
5891  if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM])
5892  ir.rm &= 0x3;
5894  }
5896  break;
5897 
5898  case 0x0fa4:
5899  case 0x0fa5:
5900  case 0x0fac:
5901  case 0x0fad:
5902  if (i386_record_modrm (&ir))
5903  return -1;
5904  if (ir.mod == 3)
5905  {
5907  return -1;
5908  }
5909  else
5910  {
5911  if (i386_record_lea_modrm (&ir))
5912  return -1;
5913  }
5914  break;
5915 
5916  case 0xd8: /* Floats. */
5917  case 0xd9:
5918  case 0xda:
5919  case 0xdb:
5920  case 0xdc:
5921  case 0xdd:
5922  case 0xde:
5923  case 0xdf:
5924  if (i386_record_modrm (&ir))
5925  return -1;
5926  ir.reg |= ((opcode & 7) << 3);
5927  if (ir.mod != 3)
5928  {
5929  /* Memory. */
5930  uint64_t addr64;
5931 
5932  if (i386_record_lea_modrm_addr (&ir, &addr64))
5933  return -1;
5934  switch (ir.reg)
5935  {
5936  case 0x02:
5937  case 0x12:
5938  case 0x22:
5939  case 0x32:
5940  /* For fcom, ficom nothing to do. */
5941  break;
5942  case 0x03:
5943  case 0x13:
5944  case 0x23:
5945  case 0x33:
5946  /* For fcomp, ficomp pop FPU stack, store all. */
5947  if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
5948  return -1;
5949  break;
5950  case 0x00:
5951  case 0x01:
5952  case 0x04:
5953  case 0x05:
5954  case 0x06:
5955  case 0x07:
5956  case 0x10:
5957  case 0x11:
5958  case 0x14:
5959  case 0x15:
5960  case 0x16:
5961  case 0x17:
5962  case 0x20:
5963  case 0x21:
5964  case 0x24:
5965  case 0x25:
5966  case 0x26:
5967  case 0x27:
5968  case 0x30:
5969  case 0x31:
5970  case 0x34:
5971  case 0x35:
5972  case 0x36:
5973  case 0x37:
5974  /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5975  fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5976  of code, always affects st(0) register. */
5977  if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
5978  return -1;
5979  break;
5980  case 0x08:
5981  case 0x0a:
5982  case 0x0b:
5983  case 0x18:
5984  case 0x19:
5985  case 0x1a:
5986  case 0x1b:
5987  case 0x1d:
5988  case 0x28:
5989  case 0x29:
5990  case 0x2a:
5991  case 0x2b:
5992  case 0x38:
5993  case 0x39:
5994  case 0x3a:
5995  case 0x3b:
5996  case 0x3c:
5997  case 0x3d:
5998  switch (ir.reg & 7)
5999  {
6000  case 0:
6001  /* Handling fld, fild. */
6002  if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6003  return -1;
6004  break;
6005  case 1:
6006  switch (ir.reg >> 4)
6007  {
6008  case 0:
6009  if (record_full_arch_list_add_mem (addr64, 4))
6010  return -1;
6011  break;
6012  case 2:
6013  if (record_full_arch_list_add_mem (addr64, 8))
6014  return -1;
6015  break;
6016  case 3:
6017  break;
6018  default:
6019  if (record_full_arch_list_add_mem (addr64, 2))
6020  return -1;
6021  break;
6022  }
6023  break;
6024  default:
6025  switch (ir.reg >> 4)
6026  {
6027  case 0:
6028  if (record_full_arch_list_add_mem (addr64, 4))
6029  return -1;
6030  if (3 == (ir.reg & 7))
6031  {
6032  /* For fstp m32fp. */
6033  if (i386_record_floats (gdbarch, &ir,
6035  return -1;
6036  }
6037  break;
6038  case 1:
6039  if (record_full_arch_list_add_mem (addr64, 4))
6040  return -1;
6041  if ((3 == (ir.reg & 7))
6042  || (5 == (ir.reg & 7))
6043  || (7 == (ir.reg & 7)))
6044  {
6045  /* For fstp insn. */
6046  if (i386_record_floats (gdbarch, &ir,
6048  return -1;
6049  }
6050  break;
6051  case 2:
6052  if (record_full_arch_list_add_mem (addr64, 8))
6053  return -1;
6054  if (3 == (ir.reg & 7))
6055  {
6056  /* For fstp m64fp. */
6057  if (i386_record_floats (gdbarch, &ir,
6059  return -1;
6060  }
6061  break;
6062  case 3:
6063  if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7)))
6064  {
6065  /* For fistp, fbld, fild, fbstp. */
6066  if (i386_record_floats (gdbarch, &ir,
6068  return -1;
6069  }
6070  /* Fall through */
6071  default:
6072  if (record_full_arch_list_add_mem (addr64, 2))
6073  return -1;
6074  break;
6075  }
6076  break;
6077  }
6078  break;
6079  case 0x0c:
6080  /* Insn fldenv. */
6081  if (i386_record_floats (gdbarch, &ir,
6083  return -1;
6084  break;
6085  case 0x0d:
6086  /* Insn fldcw. */
6087  if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep)))
6088  return -1;
6089  break;
6090  case 0x2c:
6091  /* Insn frstor. */
6092  if (i386_record_floats (gdbarch, &ir,
6094  return -1;
6095  break;
6096  case 0x0e:
6097  if (ir.dflag)
6098  {
6099  if (record_full_arch_list_add_mem (addr64, 28))
6100  return -1;
6101  }
6102  else
6103  {
6104  if (record_full_arch_list_add_mem (addr64, 14))
6105  return -1;
6106  }
6107  break;
6108  case 0x0f:
6109  case 0x2f:
6110  if (record_full_arch_list_add_mem (addr64, 2))
6111  return -1;
6112  /* Insn fstp, fbstp. */
6113  if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6114  return -1;
6115  break;
6116  case 0x1f:
6117  case 0x3e:
6118  if (record_full_arch_list_add_mem (addr64, 10))
6119  return -1;
6120  break;
6121  case 0x2e:
6122  if (ir.dflag)
6123  {
6124  if (record_full_arch_list_add_mem (addr64, 28))
6125  return -1;
6126  addr64 += 28;
6127  }
6128  else
6129  {
6130  if (record_full_arch_list_add_mem (addr64, 14))
6131  return -1;
6132  addr64 += 14;
6133  }
6134  if (record_full_arch_list_add_mem (addr64, 80))
6135  return -1;
6136  /* Insn fsave. */
6137  if (i386_record_floats (gdbarch, &ir,
6139  return -1;
6140  break;
6141  case 0x3f:
6142  if (record_full_arch_list_add_mem (addr64, 8))
6143  return -1;
6144  /* Insn fistp. */
6145  if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6146  return -1;
6147  break;
6148  default:
6149  ir.addr -= 2;
6150  opcode = opcode << 8 | ir.modrm;
6151  goto no_support;
6152  break;
6153  }
6154  }
6155  /* Opcode is an extension of modR/M byte. */
6156  else
6157  {
6158  switch (opcode)
6159  {
6160  case 0xd8:
6161  if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep)))
6162  return -1;
6163  break;
6164  case 0xd9:
6165  if (0x0c == (ir.modrm >> 4))
6166  {
6167  if ((ir.modrm & 0x0f) <= 7)
6168  {
6169  if (i386_record_floats (gdbarch, &ir,
6171  return -1;
6172  }
6173  else
6174  {
6175  if (i386_record_floats (gdbarch, &ir,
6176  I387_ST0_REGNUM (tdep)))
6177  return -1;
6178  /* If only st(0) is changing, then we have already
6179  recorded. */
6180  if ((ir.modrm & 0x0f) - 0x08)
6181  {
6182  if (i386_record_floats (gdbarch, &ir,
6183  I387_ST0_REGNUM (tdep) +
6184  ((ir.modrm & 0x0f) - 0x08)))
6185  return -1;
6186  }
6187  }
6188  }
6189  else
6190  {
6191  switch (ir.modrm)
6192  {
6193  case 0xe0:
6194  case 0xe1:
6195  case 0xf0:
6196  case 0xf5:
6197  case 0xf8:
6198  case 0xfa:
6199  case 0xfc:
6200  case 0xfe:
6201  case 0xff:
6202  if (i386_record_floats (gdbarch, &ir,
6203  I387_ST0_REGNUM (tdep)))
6204  return -1;
6205  break;
6206  case 0xf1:
6207  case 0xf2:
6208  case 0xf3:
6209  case 0xf4:
6210  case 0xf6:
6211  case 0xf7:
6212  case 0xe8:
6213  case 0xe9:
6214  case 0xea:
6215  case 0xeb:
6216  case 0xec:
6217  case 0xed:
6218  case 0xee:
6219  case 0xf9:
6220  case 0xfb:
6221  if (i386_record_floats (gdbarch, &ir,
6223  return -1;
6224  break;
6225  case 0xfd:
6226  if (i386_record_floats (gdbarch, &ir,
6227  I387_ST0_REGNUM (tdep)))
6228  return -1;
6229  if (i386_record_floats (gdbarch, &ir,
6230  I387_ST0_REGNUM (tdep) + 1))
6231  return -1;
6232  break;
6233  }
6234  }
6235  break;
6236  case 0xda:
6237  if (0xe9 == ir.modrm)
6238  {
6239  if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6240  return -1;
6241  }
6242  else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6243  {
6244  if (i386_record_floats (gdbarch, &ir,
6245  I387_ST0_REGNUM (tdep)))
6246  return -1;
6247  if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6248  {
6249  if (i386_record_floats (gdbarch, &ir,
6250  I387_ST0_REGNUM (tdep) +
6251  (ir.modrm & 0x0f)))
6252  return -1;
6253  }
6254  else if ((ir.modrm & 0x0f) - 0x08)
6255  {
6256  if (i386_record_floats (gdbarch, &ir,
6257  I387_ST0_REGNUM (tdep) +
6258  ((ir.modrm & 0x0f) - 0x08)))
6259  return -1;
6260  }
6261  }
6262  break;
6263  case 0xdb:
6264  if (0xe3 == ir.modrm)
6265  {
6266  if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV))
6267  return -1;
6268  }
6269  else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4))
6270  {
6271  if (i386_record_floats (gdbarch, &ir,
6272  I387_ST0_REGNUM (tdep)))
6273  return -1;
6274  if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7))
6275  {
6276  if (i386_record_floats (gdbarch, &ir,
6277  I387_ST0_REGNUM (tdep) +
6278  (ir.modrm & 0x0f)))
6279  return -1;
6280  }
6281  else if ((ir.modrm & 0x0f) - 0x08)
6282  {
6283  if (i386_record_floats (gdbarch, &ir,
6284  I387_ST0_REGNUM (tdep) +
6285  ((ir.modrm & 0x0f) - 0x08)))
6286  return -1;
6287  }
6288  }
6289  break;
6290  case 0xdc:
6291  if ((0x0c == ir.modrm >> 4)
6292  || (0x0d == ir.modrm >> 4)
6293  || (0x0f == ir.modrm >> 4))
6294  {
6295  if ((ir.modrm & 0x0f) <= 7)
6296  {
6297  if (i386_record_floats (gdbarch, &ir,
6298  I387_ST0_REGNUM (tdep) +
6299  (ir.modrm & 0x0f)))
6300  return -1;
6301  }
6302  else
6303  {
6304  if (i386_record_floats (gdbarch, &ir,
6305  I387_ST0_REGNUM (tdep) +
6306  ((ir.modrm & 0x0f) - 0x08)))
6307  return -1;
6308  }
6309  }
6310  break;
6311  case 0xdd:
6312  if (0x0c == ir.modrm >> 4)
6313  {
6314  if (i386_record_floats (gdbarch, &ir,
6315  I387_FTAG_REGNUM (tdep)))
6316  return -1;
6317  }
6318  else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6319  {
6320  if ((ir.modrm & 0x0f) <= 7)
6321  {
6322  if (i386_record_floats (gdbarch, &ir,
6323  I387_ST0_REGNUM (tdep) +
6324  (ir.modrm & 0x0f)))
6325  return -1;
6326  }
6327  else
6328  {
6329  if (i386_record_floats (gdbarch, &ir,
6331  return -1;
6332  }
6333  }
6334  break;
6335  case 0xde:
6336  if ((0x0c == ir.modrm >> 4)
6337  || (0x0e == ir.modrm >> 4)
6338  || (0x0f == ir.modrm >> 4)
6339  || (0xd9 == ir.modrm))
6340  {
6341  if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6342  return -1;
6343  }
6344  break;
6345  case 0xdf:
6346  if (0xe0 == ir.modrm)
6347  {
6349  I386_EAX_REGNUM))
6350  return -1;
6351  }
6352  else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4))
6353  {
6354  if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS))
6355  return -1;
6356  }
6357  break;
6358  }
6359  }
6360  break;
6361  /* string ops */
6362  case 0xa4: /* movsS */
6363  case 0xa5:
6364  case 0xaa: /* stosS */
6365  case 0xab:
6366  case 0x6c: /* insS */
6367  case 0x6d:
6370  &addr);
6371  if (addr)
6372  {
6373  ULONGEST es, ds;
6374 
6375  if ((opcode & 1) == 0)
6376  ir.ot = OT_BYTE;
6377  else
6378  ir.ot = ir.dflag + OT_WORD;
6381  &addr);
6382 
6385  &es);
6388  &ds);
6389  if (ir.aflag && (es != ds))
6390  {
6391  /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6393  {
6394  int q;
6395 
6397  q = yquery (_("\
6398 Process record ignores the memory change of instruction at address %s\n\
6399 because it can't get the value of the segment register.\n\
6400 Do you want to stop the program?"),
6401  paddress (gdbarch, ir.orig_addr));
6403  if (q)
6404  return -1;
6405  }
6406  }
6407  else
6408  {
6409  if (record_full_arch_list_add_mem (addr, 1 << ir.ot))
6410  return -1;
6411  }
6412 
6413  if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6415  if (opcode == 0xa4 || opcode == 0xa5)
6419  }
6420  break;
6421 
6422  case 0xa6: /* cmpsS */
6423  case 0xa7:
6426  if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6429  break;
6430 
6431  case 0xac: /* lodsS */
6432  case 0xad:
6435  if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6438  break;
6439 
6440  case 0xae: /* scasS */
6441  case 0xaf:
6443  if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6446  break;
6447 
6448  case 0x6e: /* outsS */
6449  case 0x6f:
6451  if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))
6454  break;
6455 
6456  case 0xe4: /* port I/O */
6457  case 0xe5:
6458  case 0xec:
6459  case 0xed:
6462  break;
6463 
6464  case 0xe6:
6465  case 0xe7:
6466  case 0xee:
6467  case 0xef:
6468  break;
6469 
6470  /* control */
6471  case 0xc2: /* ret im */
6472  case 0xc3: /* ret */
6475  break;
6476 
6477  case 0xca: /* lret im */
6478  case 0xcb: /* lret */
6479  case 0xcf: /* iret */
6483  break;
6484 
6485  case 0xe8: /* call im */
6486  if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6487  ir.dflag = 2;
6488  if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6489  return -1;
6490  break;
6491 
6492  case 0x9a: /* lcall im */
6493  if (ir.regmap[X86_RECORD_R8_REGNUM])
6494  {
6495  ir.addr -= 1;
6496  goto no_support;
6497  }
6499  if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6500  return -1;
6501  break;
6502 
6503  case 0xe9: /* jmp im */
6504  case 0xea: /* ljmp im */
6505  case 0xeb: /* jmp Jb */
6506  case 0x70: /* jcc Jb */
6507  case 0x71:
6508  case 0x72:
6509  case 0x73:
6510  case 0x74:
6511  case 0x75:
6512  case 0x76:
6513  case 0x77:
6514  case 0x78:
6515  case 0x79:
6516  case 0x7a:
6517  case 0x7b:
6518  case 0x7c:
6519  case 0x7d:
6520  case 0x7e:
6521  case 0x7f:
6522  case 0x0f80: /* jcc Jv */
6523  case 0x0f81:
6524  case 0x0f82:
6525  case 0x0f83:
6526  case 0x0f84:
6527  case 0x0f85:
6528  case 0x0f86:
6529  case 0x0f87:
6530  case 0x0f88:
6531  case 0x0f89:
6532  case 0x0f8a:
6533  case 0x0f8b:
6534  case 0x0f8c:
6535  case 0x0f8d:
6536  case 0x0f8e:
6537  case 0x0f8f:
6538  break;
6539 
6540  case 0x0f90: /* setcc Gv */
6541  case 0x0f91:
6542  case 0x0f92:
6543  case 0x0f93:
6544  case 0x0f94:
6545  case 0x0f95:
6546  case 0x0f96:
6547  case 0x0f97:
6548  case 0x0f98:
6549  case 0x0f99:
6550  case 0x0f9a:
6551  case 0x0f9b:
6552  case 0x0f9c:
6553  case 0x0f9d:
6554  case 0x0f9e:
6555  case 0x0f9f:
6557  ir.ot = OT_BYTE;
6558  if (i386_record_modrm (&ir))
6559  return -1;
6560  if (ir.mod == 3)
6562  : (ir.rm & 0x3));
6563  else
6564  {
6565  if (i386_record_lea_modrm (&ir))
6566  return -1;
6567  }
6568  break;
6569 
6570  case 0x0f40: /* cmov Gv, Ev */
6571  case 0x0f41:
6572  case 0x0f42:
6573  case 0x0f43:
6574  case 0x0f44:
6575  case 0x0f45:
6576  case 0x0f46:
6577  case 0x0f47:
6578  case 0x0f48:
6579  case 0x0f49:
6580  case 0x0f4a:
6581  case 0x0f4b:
6582  case 0x0f4c:
6583  case 0x0f4d:
6584  case 0x0f4e:
6585  case 0x0f4f:
6586  if (i386_record_modrm (&ir))
6587  return -1;
6588  ir.reg |= rex_r;
6589  if (ir.dflag == OT_BYTE)
6590  ir.reg &= 0x3;
6592  break;
6593 
6594  /* flags */
6595  case 0x9c: /* pushf */
6597  if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag)
6598  ir.dflag = 2;
6599  if (i386_record_push (&ir, 1 << (ir.dflag + 1)))
6600  return -1;
6601  break;
6602 
6603  case 0x9d: /* popf */
6606  break;
6607 
6608  case 0x9e: /* sahf */
6609  if (ir.regmap[X86_RECORD_R8_REGNUM])
6610  {
6611  ir.addr -= 1;
6612  goto no_support;
6613  }
6614  /* FALLTHROUGH */
6615  case 0xf5: /* cmc */
6616  case 0xf8: /* clc */
6617  case 0xf9: /* stc */
6618  case 0xfc: /* cld */
6619  case 0xfd: /* std */
6621  break;
6622 
6623  case 0x9f: /* lahf */
6624  if (ir.regmap[X86_RECORD_R8_REGNUM])
6625  {
6626  ir.addr -= 1;
6627  goto no_support;
6628  }
6631  break;
6632 
6633  /* bit operations */
6634  case 0x0fba: /* bt/bts/btr/btc Gv, im */
6635  ir.ot = ir.dflag + OT_WORD;
6636  if (i386_record_modrm (&ir))
6637  return -1;
6638  if (ir.reg < 4)
6639  {
6640  ir.addr -= 2;
6641  opcode = opcode << 8 | ir.modrm;
6642  goto no_support;
6643  }
6644  if (ir.reg != 4)
6645  {
6646  if (ir.mod == 3)
6648  else
6649  {
6650  if (i386_record_lea_modrm (&ir))
6651  return -1;
6652  }
6653  }
6655  break;
6656 
6657  case 0x0fa3: /* bt Gv, Ev */
6659  break;
6660 
6661  case 0x0fab: /* bts */
6662  case 0x0fb3: /* btr */
6663  case 0x0fbb: /* btc */
6664  ir.ot = ir.dflag + OT_WORD;
6665  if (i386_record_modrm (&ir))
6666  return -1;
6667  if (ir.mod == 3)
6669  else
6670  {
6671  uint64_t addr64;
6672  if (i386_record_lea_modrm_addr (&ir, &addr64))
6673  return -1;
6675  ir.regmap[ir.reg | rex_r],
6676  &addr);
6677  switch (ir.dflag)
6678  {
6679  case 0:
6680  addr64 += ((int16_t) addr >> 4) << 4;
6681  break;
6682  case 1:
6683  addr64 += ((int32_t) addr >> 5) << 5;
6684  break;
6685  case 2:
6686  addr64 += ((int64_t) addr >> 6) << 6;
6687  break;
6688  }
6689  if (record_full_arch_list_add_mem (addr64, 1 << ir.ot))
6690  return -1;
6691  if (i386_record_lea_modrm (&ir))
6692  return -1;
6693  }
6695  break;
6696 
6697  case 0x0fbc: /* bsf */
6698  case 0x0fbd: /* bsr */
6701  break;
6702 
6703  /* bcd */
6704  case 0x27: /* daa */
6705  case 0x2f: /* das */
6706  case 0x37: /* aaa */
6707  case 0x3f: /* aas */
6708  case 0xd4: /* aam */
6709  case 0xd5: /* aad */
6710  if (ir.regmap[X86_RECORD_R8_REGNUM])
6711  {
6712  ir.addr -= 1;
6713  goto no_support;
6714  }
6717  break;
6718 
6719  /* misc */
6720  case 0x90: /* nop */
6721  if (prefixes & PREFIX_LOCK)
6722  {
6723  ir.addr -= 1;
6724  goto no_support;
6725  }
6726  break;
6727 
6728  case 0x9b: /* fwait */
6729  if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
6730  return -1;
6731  opcode = (uint32_t) opcode8;
6732  ir.addr++;
6733  goto reswitch;
6734  break;
6735 
6736  /* XXX */
6737  case 0xcc: /* int3 */
6738  printf_unfiltered (_("Process record does not support instruction "
6739  "int3.\n"));
6740  ir.addr -= 1;
6741  goto no_support;
6742  break;
6743 
6744  /* XXX */
6745  case 0xcd: /* int */
6746  {
6747  int ret;
6748  uint8_t interrupt;
6749  if (record_read_memory (gdbarch, ir.addr, &interrupt, 1))
6750  return -1;
6751  ir.addr++;
6752  if (interrupt != 0x80
6753  || tdep->i386_intx80_record == NULL)
6754  {
6755  printf_unfiltered (_("Process record does not support "
6756  "instruction int 0x%02x.\n"),
6757  interrupt);
6758  ir.addr -= 2;
6759  goto no_support;
6760  }
6761  ret = tdep->i386_intx80_record (ir.regcache);
6762  if (ret)
6763  return ret;
6764  }
6765  break;
6766 
6767  /* XXX */
6768  case 0xce: /* into */
6769  printf_unfiltered (_("Process record does not support "
6770  "instruction into.\n"));
6771  ir.addr -= 1;
6772  goto no_support;
6773  break;
6774 
6775  case 0xfa: /* cli */
6776  case 0xfb: /* sti */
6777  break;
6778 
6779  case 0x62: /* bound */
6780  printf_unfiltered (_("Process record does not support "
6781  "instruction bound.\n"));
6782  ir.addr -= 1;
6783  goto no_support;
6784  break;
6785 
6786  case 0x0fc8: /* bswap reg */
6787  case 0x0fc9:
6788  case 0x0fca:
6789  case 0x0fcb:
6790  case 0x0fcc:
6791  case 0x0fcd:
6792  case 0x0fce:
6793  case 0x0fcf:
6794  I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b);
6795  break;
6796 
6797  case 0xd6: /* salc */
6798  if (ir.regmap[X86_RECORD_R8_REGNUM])
6799  {
6800  ir.addr -= 1;
6801  goto no_support;
6802  }
6805  break;
6806 
6807  case 0xe0: /* loopnz */
6808  case 0xe1: /* loopz */
6809  case 0xe2: /* loop */
6810  case 0xe3: /* jecxz */
6813  break;
6814 
6815  case 0x0f30: /* wrmsr */
6816  printf_unfiltered (_("Process record does not support "
6817  "instruction wrmsr.\n"));
6818  ir.addr -= 2;
6819  goto no_support;
6820  break;
6821 
6822  case 0x0f32: /* rdmsr */
6823  printf_unfiltered (_("Process record does not support "
6824  "instruction rdmsr.\n"));
6825  ir.addr -= 2;
6826  goto no_support;
6827  break;
6828 
6829  case 0x0f31: /* rdtsc */
6832  break;
6833 
6834  case 0x0f34: /* sysenter */
6835  {
6836  int ret;
6837  if (ir.regmap[X86_RECORD_R8_REGNUM])
6838  {
6839  ir.addr -= 2;
6840  goto no_support;
6841  }
6842  if (tdep->i386_sysenter_record == NULL)
6843  {
6844  printf_unfiltered (_("Process record does not support "
6845  "instruction sysenter.\n"));
6846  ir.addr -= 2;
6847  goto no_support;
6848  }
6849  ret = tdep->i386_sysenter_record (ir.regcache);
6850  if (ret)
6851  return ret;
6852  }
6853  break;
6854 
6855  case 0x0f35: /* sysexit */
6856  printf_unfiltered (_("Process record does not support "
6857  "instruction sysexit.\n"));
6858  ir.addr -= 2;
6859  goto no_support;
6860  break;
6861 
6862  case 0x0f05: /* syscall */
6863  {
6864  int ret;
6865  if (tdep->i386_syscall_record == NULL)
6866  {
6867  printf_unfiltered (_("Process record does not support "
6868  "instruction syscall.\n"));
6869  ir.addr -= 2;
6870  goto no_support;
6871  }
6872  ret = tdep->i386_syscall_record (ir.regcache);
6873  if (ret)
6874  return ret;
6875  }
6876  break;
6877 
6878  case 0x0f07: /* sysret */
6879  printf_unfiltered (_("Process record does not support "
6880  "instruction sysret.\n"));
6881  ir.addr -= 2;
6882  goto no_support;
6883  break;
6884 
6885  case 0x0fa2: /* cpuid */
6890  break;
6891 
6892  case 0xf4: /* hlt */
6893  printf_unfiltered (_("Process record does not support "
6894  "instruction hlt.\n"));
6895  ir.addr -= 1;
6896  goto no_support;
6897  break;
6898 
6899  case 0x0f00:
6900  if (i386_record_modrm (&ir))
6901  return -1;
6902  switch (ir.reg)
6903  {
6904  case 0: /* sldt */
6905  case 1: /* str */
6906  if (ir.mod == 3)
6908  else
6909  {
6910  ir.ot = OT_WORD;
6911  if (i386_record_lea_modrm (&ir))
6912  return -1;
6913  }
6914  break;
6915  case 2: /* lldt */
6916  case 3: /* ltr */
6917  break;
6918  case 4: /* verr */
6919  case 5: /* verw */
6921  break;
6922  default:
6923  ir.addr -= 3;
6924  opcode = opcode << 8 | ir.modrm;
6925  goto no_support;
6926  break;
6927  }
6928  break;
6929 
6930  case 0x0f01:
6931  if (i386_record_modrm (&ir))
6932  return -1;
6933  switch (ir.reg)
6934  {
6935  case 0: /* sgdt */
6936  {
6937  uint64_t addr64;
6938 
6939  if (ir.mod == 3)
6940  {
6941  ir.addr -= 3;
6942  opcode = opcode << 8 | ir.modrm;
6943  goto no_support;
6944  }
6945  if (ir.override >= 0)
6946  {
6948  {
6949  int q;
6950 
6952  q = yquery (_("\
6953 Process record ignores the memory change of instruction at address %s\n\
6954 because it can't get the value of the segment register.\n\
6955 Do you want to stop the program?"),
6956  paddress (gdbarch, ir.orig_addr));
6958  if (q)
6959  return -1;
6960  }
6961  }
6962  else
6963  {
6964  if (i386_record_lea_modrm_addr (&ir, &addr64))
6965  return -1;
6966  if (record_full_arch_list_add_mem (addr64, 2))
6967  return -1;
6968  addr64 += 2;
6969  if (ir.regmap[X86_RECORD_R8_REGNUM])
6970  {
6971  if (record_full_arch_list_add_mem (addr64, 8))
6972  return -1;
6973  }
6974  else
6975  {
6976  if (record_full_arch_list_add_mem (addr64, 4))
6977  return -1;
6978  }
6979  }
6980  }
6981  break;
6982  case 1:
6983  if (ir.mod == 3)
6984  {
6985  switch (ir.rm)
6986  {
6987  case 0: /* monitor */
6988  break;
6989  case 1: /* mwait */
6991  break;
6992  default:
6993  ir.addr -= 3;
6994  opcode = opcode << 8 | ir.modrm;
6995  goto no_support;
6996  break;
6997  }
6998  }
6999  else
7000  {
7001  /* sidt */
7002  if (ir.override >= 0)
7003  {
7005  {
7006  int q;
7007 
7009  q = yquery (_("\
7010 Process record ignores the memory change of instruction at address %s\n\
7011 because it can't get the value of the segment register.\n\
7012 Do you want to stop the program?"),
7013  paddress (gdbarch, ir.orig_addr));
7015  if (q)
7016  return -1;
7017  }
7018  }
7019  else
7020  {
7021  uint64_t addr64;
7022 
7023  if (i386_record_lea_modrm_addr (&ir, &addr64))
7024  return -1;
7025  if (record_full_arch_list_add_mem (addr64, 2))
7026  return -1;
7027  addr64 += 2;
7028  if (ir.regmap[X86_RECORD_R8_REGNUM])
7029  {
7030  if (record_full_arch_list_add_mem (addr64, 8))
7031  return -1;
7032  }
7033  else
7034  {
7035  if (record_full_arch_list_add_mem (addr64, 4))
7036  return -1;
7037  }
7038  }
7039  }
7040  break;
7041  case 2: /* lgdt */
7042  if (ir.mod == 3)
7043  {
7044  /* xgetbv */
7045  if (ir.rm == 0)
7046  {
7049  break;
7050  }
7051  /* xsetbv */
7052  else if (ir.rm == 1)
7053  break;
7054  }
7055  case 3: /* lidt */
7056  if (ir.mod == 3)
7057  {
7058  ir.addr -= 3;
7059  opcode = opcode << 8 | ir.modrm;
7060  goto no_support;
7061  }
7062  break;
7063  case 4: /* smsw */
7064  if (ir.mod == 3)
7065  {
7066  if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b))
7067  return -1;
7068  }
7069  else
7070  {
7071  ir.ot = OT_WORD;
7072  if (i386_record_lea_modrm (&ir))
7073  return -1;
7074  }
7076  break;
7077  case 6: /* lmsw */
7079  break;
7080  case 7: /* invlpg */
7081  if (ir.mod == 3)
7082  {
7083  if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM])
7085  else
7086  {
7087  ir.addr -= 3;
7088  opcode = opcode << 8 | ir.modrm;
7089  goto no_support;
7090  }
7091  }
7092  else
7094  break;
7095  default:
7096  ir.addr -= 3;
7097  opcode = opcode << 8 | ir.modrm;
7098  goto no_support;
7099  break;
7100  }
7101  break;
7102 
7103  case 0x0f08: /* invd */
7104  case 0x0f09: /* wbinvd */
7105  break;
7106 
7107  case 0x63: /* arpl */
7108  if (i386_record_modrm (&ir))
7109  return -1;
7110  if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM])
7111  {
7113  ? (ir.reg | rex_r) : ir.rm);
7114  }
7115  else
7116  {
7117  ir.ot = ir.dflag ? OT_LONG : OT_WORD;
7118  if (i386_record_lea_modrm (&ir))
7119  return -1;
7120  }
7121  if (!ir.regmap[X86_RECORD_R8_REGNUM])
7123  break;
7124 
7125  case 0x0f02: /* lar */
7126  case 0x0f03: /* lsl */
7127  if (i386_record_modrm (&ir))
7128  return -1;
7131  break;
7132 
7133  case 0x0f18:
7134  if (i386_record_modrm (&ir))
7135  return -1;
7136  if (ir.mod == 3 && ir.reg == 3)
7137  {
7138  ir.addr -= 3;
7139  opcode = opcode << 8 | ir.modrm;
7140  goto no_support;
7141  }
7142  break;
7143 
7144  case 0x0f19:
7145  case 0x0f1a:
7146  case 0x0f1b:
7147  case 0x0f1c:
7148  case 0x0f1d:
7149  case 0x0f1e:
7150  case 0x0f1f:
7151  /* nop (multi byte) */
7152  break;
7153 
7154  case 0x0f20: /* mov reg, crN */
7155  case 0x0f22: /* mov crN, reg */
7156  if (i386_record_modrm (&ir))
7157  return -1;
7158  if ((ir.modrm & 0xc0) != 0xc0)
7159  {
7160  ir.addr -= 3;
7161  opcode = opcode << 8 | ir.modrm;
7162  goto no_support;
7163  }
7164  switch (ir.reg)
7165  {
7166  case 0:
7167  case 2:
7168  case 3:
7169  case 4:
7170  case 8:
7171  if (opcode & 2)
7173  else
7175  break;
7176  default:
7177  ir.addr -= 3;
7178  opcode = opcode << 8 | ir.modrm;
7179  goto no_support;
7180  break;
7181  }
7182  break;
7183 
7184  case 0x0f21: /* mov reg, drN */
7185  case 0x0f23: /* mov drN, reg */
7186  if (i386_record_modrm (&ir))
7187  return -1;
7188  if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4
7189  || ir.reg == 5 || ir.reg >= 8)
7190  {
7191  ir.addr -= 3;
7192  opcode = opcode << 8 | ir.modrm;
7193  goto no_support;
7194  }
7195  if (opcode & 2)
7197  else
7199  break;
7200 
7201  case 0x0f06: /* clts */
7203  break;
7204 
7205  /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7206 
7207  case 0x0f0d: /* 3DNow! prefetch */
7208  break;
7209 
7210  case 0x0f0e: /* 3DNow! femms */
7211  case 0x0f77: /* emms */
7212  if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep)))
7213  goto no_support;
7215  break;
7216 
7217  case 0x0f0f: /* 3DNow! data */
7218  if (i386_record_modrm (&ir))
7219  return -1;
7220  if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7221  return -1;
7222  ir.addr++;
7223  switch (opcode8)
7224  {
7225  case 0x0c: /* 3DNow! pi2fw */
7226  case 0x0d: /* 3DNow! pi2fd */
7227  case 0x1c: /* 3DNow! pf2iw */
7228  case 0x1d: /* 3DNow! pf2id */
7229  case 0x8a: /* 3DNow! pfnacc */
7230  case 0x8e: /* 3DNow! pfpnacc */
7231  case 0x90: /* 3DNow! pfcmpge */
7232  case 0x94: /* 3DNow! pfmin */
7233  case 0x96: /* 3DNow! pfrcp */
7234  case 0x97: /* 3DNow! pfrsqrt */
7235  case 0x9a: /* 3DNow! pfsub */
7236  case 0x9e: /* 3DNow! pfadd */
7237  case 0xa0: /* 3DNow! pfcmpgt */
7238  case 0xa4: /* 3DNow! pfmax */
7239  case 0xa6: /* 3DNow! pfrcpit1 */
7240  case 0xa7: /* 3DNow! pfrsqit1 */
7241  case 0xaa: /* 3DNow! pfsubr */
7242  case 0xae: /* 3DNow! pfacc */
7243  case 0xb0: /* 3DNow! pfcmpeq */
7244  case 0xb4: /* 3DNow! pfmul */
7245  case 0xb6: /* 3DNow! pfrcpit2 */
7246  case 0xb7: /* 3DNow! pmulhrw */
7247  case 0xbb: /* 3DNow! pswapd */
7248  case 0xbf: /* 3DNow! pavgusb */
7249  if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7250  goto no_support_3dnow_data;
7252  break;
7253 
7254  default:
7255 no_support_3dnow_data:
7256  opcode = (opcode << 8) | opcode8;
7257  goto no_support;
7258  break;
7259  }
7260  break;
7261 
7262  case 0x0faa: /* rsm */
7272  break;
7273 
7274  case 0x0fae:
7275  if (i386_record_modrm (&ir))
7276  return -1;
7277  switch(ir.reg)
7278  {
7279  case 0: /* fxsave */
7280  {
7281  uint64_t tmpu64;
7282 
7284  if (i386_record_lea_modrm_addr (&ir, &tmpu64))
7285  return -1;
7286  if (record_full_arch_list_add_mem (tmpu64, 512))
7287  return -1;
7288  }
7289  break;
7290 
7291  case 1: /* fxrstor */
7292  {
7293  int i;
7294 
7296 
7297  for (i = I387_MM0_REGNUM (tdep);
7298  i386_mmx_regnum_p (gdbarch, i); i++)
7300 
7301  for (i = I387_XMM0_REGNUM (tdep);
7302  i386_xmm_regnum_p (gdbarch, i); i++)
7304 
7305  if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7307  I387_MXCSR_REGNUM(tdep));
7308 
7309  for (i = I387_ST0_REGNUM (tdep);
7310  i386_fp_regnum_p (gdbarch, i); i++)
7312 
7313  for (i = I387_FCTRL_REGNUM (tdep);
7314  i386_fpc_regnum_p (gdbarch, i); i++)
7316  }
7317  break;
7318 
7319  case 2: /* ldmxcsr */
7320  if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep)))
7321  goto no_support;
7323  break;
7324 
7325  case 3: /* stmxcsr */
7326  ir.ot = OT_LONG;
7327  if (i386_record_lea_modrm (&ir))
7328  return -1;
7329  break;
7330 
7331  case 5: /* lfence */
7332  case 6: /* mfence */
7333  case 7: /* sfence clflush */
7334  break;
7335 
7336  default:
7337  opcode = (opcode << 8) | ir.modrm;
7338  goto no_support;
7339  break;
7340  }
7341  break;
7342 
7343  case 0x0fc3: /* movnti */
7344  ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG;
7345  if (i386_record_modrm (&ir))
7346  return -1;
7347  if (ir.mod == 3)
7348  goto no_support;
7349  ir.reg |= rex_r;
7350  if (i386_record_lea_modrm (&ir))
7351  return -1;
7352  break;
7353 
7354  /* Add prefix to opcode. */
7355  case 0x0f10:
7356  case 0x0f11:
7357  case 0x0f12:
7358  case 0x0f13:
7359  case 0x0f14:
7360  case 0x0f15:
7361  case 0x0f16:
7362  case 0x0f17:
7363  case 0x0f28:
7364  case 0x0f29:
7365  case 0x0f2a:
7366  case 0x0f2b:
7367  case 0x0f2c:
7368  case 0x0f2d:
7369  case 0x0f2e:
7370  case 0x0f2f:
7371  case 0x0f38:
7372  case 0x0f39:
7373  case 0x0f3a:
7374  case 0x0f50:
7375  case 0x0f51:
7376  case 0x0f52:
7377  case 0x0f53:
7378  case 0x0f54:
7379  case 0x0f55:
7380  case 0x0f56:
7381  case 0x0f57:
7382  case 0x0f58:
7383  case 0x0f59:
7384  case 0x0f5a:
7385  case 0x0f5b:
7386  case 0x0f5c:
7387  case 0x0f5d:
7388  case 0x0f5e:
7389  case 0x0f5f:
7390  case 0x0f60:
7391  case 0x0f61:
7392  case 0x0f62:
7393  case 0x0f63:
7394  case 0x0f64:
7395  case 0x0f65:
7396  case 0x0f66:
7397  case 0x0f67:
7398  case 0x0f68:
7399  case 0x0f69:
7400  case 0x0f6a:
7401  case 0x0f6b:
7402  case 0x0f6c:
7403  case 0x0f6d:
7404  case 0x0f6e:
7405  case 0x0f6f:
7406  case 0x0f70:
7407  case 0x0f71:
7408  case 0x0f72:
7409  case 0x0f73:
7410  case 0x0f74:
7411  case 0x0f75:
7412  case 0x0f76:
7413  case 0x0f7c:
7414  case 0x0f7d:
7415  case 0x0f7e:
7416  case 0x0f7f:
7417  case 0x0fb8:
7418  case 0x0fc2:
7419  case 0x0fc4:
7420  case 0x0fc5:
7421  case 0x0fc6:
7422  case 0x0fd0:
7423  case 0x0fd1:
7424  case 0x0fd2:
7425  case 0x0fd3:
7426  case 0x0fd4:
7427  case 0x0fd5:
7428  case 0x0fd6:
7429  case 0x0fd7:
7430  case 0x0fd8:
7431  case 0x0fd9:
7432  case 0x0fda:
7433  case 0x0fdb:
7434  case 0x0fdc:
7435  case 0x0fdd:
7436  case 0x0fde:
7437  case 0x0fdf:
7438  case 0x0fe0:
7439  case 0x0fe1:
7440  case 0x0fe2:
7441  case 0x0fe3:
7442  case 0x0fe4:
7443  case 0x0fe5:
7444  case 0x0fe6:
7445  case 0x0fe7:
7446  case 0x0fe8:
7447  case 0x0fe9:
7448  case 0x0fea:
7449  case 0x0feb:
7450  case 0x0fec:
7451  case 0x0fed:
7452  case 0x0fee:
7453  case 0x0fef:
7454  case 0x0ff0:
7455  case 0x0ff1:
7456  case 0x0ff2:
7457  case 0x0ff3:
7458  case 0x0ff4:
7459  case 0x0ff5:
7460  case 0x0ff6:
7461  case 0x0ff7:
7462  case 0x0ff8:
7463  case 0x0ff9:
7464  case 0x0ffa:
7465  case 0x0ffb:
7466  case 0x0ffc:
7467  case 0x0ffd:
7468  case 0x0ffe:
7469  /* Mask out PREFIX_ADDR. */
7470  switch ((prefixes & ~PREFIX_ADDR))
7471  {
7472  case PREFIX_REPNZ:
7473  opcode |= 0xf20000;
7474  break;
7475  case PREFIX_DATA:
7476  opcode |= 0x660000;
7477  break;
7478  case PREFIX_REPZ:
7479  opcode |= 0xf30000;
7480  break;
7481  }
7482 reswitch_prefix_add:
7483  switch (opcode)
7484  {
7485  case 0x0f38:
7486  case 0x660f38:
7487  case 0xf20f38:
7488  case 0x0f3a:
7489  case 0x660f3a:
7490  if (record_read_memory (gdbarch, ir.addr, &opcode8, 1))
7491  return -1;
7492  ir.addr++;
7493  opcode = (uint32_t) opcode8 | opcode << 8;
7494  goto reswitch_prefix_add;
7495  break;
7496 
7497  case 0x0f10: /* movups */
7498  case 0x660f10: /* movupd */
7499  case 0xf30f10: /* movss */
7500  case 0xf20f10: /* movsd */
7501  case 0x0f12: /* movlps */
7502  case 0x660f12: /* movlpd */
7503  case 0xf30f12: /* movsldup */
7504  case 0xf20f12: /* movddup */
7505  case 0x0f14: /* unpcklps */
7506  case 0x660f14: /* unpcklpd */
7507  case 0x0f15: /* unpckhps */
7508  case 0x660f15: /* unpckhpd */
7509  case 0x0f16: /* movhps */
7510  case 0x660f16: /* movhpd */
7511  case 0xf30f16: /* movshdup */
7512  case 0x0f28: /* movaps */
7513  case 0x660f28: /* movapd */
7514  case 0x0f2a: /* cvtpi2ps */
7515  case 0x660f2a: /* cvtpi2pd */
7516  case 0xf30f2a: /* cvtsi2ss */
7517  case 0xf20f2a: /* cvtsi2sd */
7518  case 0x0f2c: /* cvttps2pi */
7519  case 0x660f2c: /* cvttpd2pi */
7520  case 0x0f2d: /* cvtps2pi */
7521  case 0x660f2d: /* cvtpd2pi */
7522  case 0x660f3800: /* pshufb */
7523  case 0x660f3801: /* phaddw */
7524  case 0x660f3802: /* phaddd */
7525  case 0x660f3803: /* phaddsw */
7526  case 0x660f3804: /* pmaddubsw */
7527  case 0x660f3805: /* phsubw */
7528  case 0x660f3806: /* phsubd */
7529  case 0x660f3807: /* phsubsw */
7530  case 0x660f3808: /* psignb */
7531  case 0x660f3809: /* psignw */
7532  case 0x660f380a: /* psignd */
7533  case 0x660f380b: /* pmulhrsw */
7534  case 0x660f3810: /* pblendvb */
7535  case 0x660f3814: /* blendvps */
7536  case 0x660f3815: /* blendvpd */
7537  case 0x660f381c: /* pabsb */
7538  case 0x660f381d: /* pabsw */
7539  case 0x660f381e: /* pabsd */
7540  case 0x660f3820: /* pmovsxbw */
7541  case 0x660f3821: /* pmovsxbd */
7542  case 0x660f3822: /* pmovsxbq */
7543  case 0x660f3823: /* pmovsxwd */
7544  case 0x660f3824: /* pmovsxwq */
7545  case 0x660f3825: /* pmovsxdq */
7546  case 0x660f3828: /* pmuldq */
7547  case 0x660f3829: /* pcmpeqq */
7548  case 0x660f382a: /* movntdqa */
7549  case 0x660f3a08: /* roundps */
7550  case 0x660f3a09: /* roundpd */
7551  case 0x660f3a0a: /* roundss */
7552  case 0x660f3a0b: /* roundsd */
7553  case 0x660f3a0c: /* blendps */
7554  case 0x660f3a0d: /* blendpd */
7555  case 0x660f3a0e: /* pblendw */
7556  case 0x660f3a0f: /* palignr */
7557  case 0x660f3a20: /* pinsrb */
7558  case 0x660f3a21: /* insertps */
7559  case 0x660f3a22: /* pinsrd pinsrq */
7560  case 0x660f3a40: /* dpps */
7561  case 0x660f3a41: /* dppd */
7562  case 0x660f3a42: /* mpsadbw */
7563  case 0x660f3a60: /* pcmpestrm */
7564  case 0x660f3a61: /* pcmpestri */
7565  case 0x660f3a62: /* pcmpistrm */
7566  case 0x660f3a63: /* pcmpistri */
7567  case 0x0f51: /* sqrtps */
7568  case 0x660f51: /* sqrtpd */
7569  case 0xf20f51: /* sqrtsd */
7570  case 0xf30f51: /* sqrtss */
7571  case 0x0f52: /* rsqrtps */
7572  case 0xf30f52: /* rsqrtss */
7573  case 0x0f53: /* rcpps */
7574  case 0xf30f53: /* rcpss */
7575  case 0x0f54: /* andps */
7576  case 0x660f54: /* andpd */
7577  case 0x0f55: /* andnps */
7578  case 0x660f55: /* andnpd */
7579  case 0x0f56: /* orps */
7580  case 0x660f56: /* orpd */
7581  case 0x0f57: /* xorps */
7582  case 0x660f57: /* xorpd */
7583  case 0x0f58: /* addps */
7584  case 0x660f58: /* addpd */
7585  case 0xf20f58: /* addsd */
7586  case 0xf30f58: /* addss */
7587  case 0x0f59: /* mulps */
7588  case 0x660f59: /* mulpd */
7589  case 0xf20f59: /* mulsd */
7590  case 0xf30f59: /* mulss */
7591  case 0x0f5a: /* cvtps2pd */
7592  case 0x660f5a: /* cvtpd2ps */
7593  case 0xf20f5a: /* cvtsd2ss */
7594  case 0xf30f5a: /* cvtss2sd */
7595  case 0x0f5b: /* cvtdq2ps */
7596  case 0x660f5b: /* cvtps2dq */
7597  case 0xf30f5b: /* cvttps2dq */
7598  case 0x0f5c: /* subps */
7599  case 0x660f5c: /* subpd */
7600  case 0xf20f5c: /* subsd */
7601  case 0xf30f5c: /* subss */
7602  case 0x0f5d: /* minps */
7603  case 0x660f5d: /* minpd */
7604  case 0xf20f5d: /* minsd */
7605  case 0xf30f5d: /* minss */
7606  case 0x0f5e: /* divps */
7607  case 0x660f5e: /* divpd */
7608  case 0xf20f5e: /* divsd */
7609  case 0xf30f5e: /* divss */
7610  case 0x0f5f: /* maxps */
7611  case 0x660f5f: /* maxpd */
7612  case 0xf20f5f: /* maxsd */
7613  case 0xf30f5f: /* maxss */
7614  case 0x660f60: /* punpcklbw */
7615  case 0x660f61: /* punpcklwd */
7616  case 0x660f62: /* punpckldq */
7617  case 0x660f63: /* packsswb */
7618  case 0x660f64: /* pcmpgtb */
7619  case 0x660f65: /* pcmpgtw */
7620  case 0x660f66: /* pcmpgtd */
7621  case 0x660f67: /* packuswb */
7622  case 0x660f68: /* punpckhbw */
7623  case 0x660f69: /* punpckhwd */
7624  case 0x660f6a: /* punpckhdq */
7625  case 0x660f6b: /* packssdw */
7626  case 0x660f6c: /* punpcklqdq */
7627  case 0x660f6d: /* punpckhqdq */
7628  case 0x660f6e: /* movd */
7629  case 0x660f6f: /* movdqa */
7630  case 0xf30f6f: /* movdqu */
7631  case 0x660f70: /* pshufd */
7632  case 0xf20f70: /* pshuflw */
7633  case 0xf30f70: /* pshufhw */
7634  case 0x660f74: /* pcmpeqb */
7635  case 0x660f75: /* pcmpeqw */
7636  case 0x660f76: /* pcmpeqd */
7637  case 0x660f7c: /* haddpd */
7638  case 0xf20f7c: /* haddps */
7639  case 0x660f7d: /* hsubpd */
7640  case 0xf20f7d: /* hsubps */
7641  case 0xf30f7e: /* movq */
7642  case 0x0fc2: /* cmpps */
7643  case 0x660fc2: /* cmppd */
7644  case 0xf20fc2: /* cmpsd */
7645  case 0xf30fc2: /* cmpss */
7646  case 0x660fc4: /* pinsrw */
7647  case 0x0fc6: /* shufps */
7648  case 0x660fc6: /* shufpd */
7649  case 0x660fd0: /* addsubpd */
7650  case 0xf20fd0: /* addsubps */
7651  case 0x660fd1: /* psrlw */
7652  case 0x660fd2: /* psrld */
7653  case 0x660fd3: /* psrlq */
7654  case 0x660fd4: /* paddq */
7655  case 0x660fd5: /* pmullw */
7656  case 0xf30fd6: /* movq2dq */
7657  case 0x660fd8: /* psubusb */
7658  case 0x660fd9: /* psubusw */
7659  case 0x660fda: /* pminub */
7660  case 0x660fdb: /* pand */
7661  case 0x660fdc: /* paddusb */
7662  case 0x660fdd: /* paddusw */
7663  case 0x660fde: /* pmaxub */
7664  case 0x660fdf: /* pandn */
7665  case 0x660fe0: /* pavgb */
7666  case 0x660fe1: /* psraw */
7667  case 0x660fe2: /* psrad */
7668  case 0x660fe3: /* pavgw */
7669  case 0x660fe4: /* pmulhuw */
7670  case 0x660fe5: /* pmulhw */
7671  case 0x660fe6: /* cvttpd2dq */
7672  case 0xf20fe6: /* cvtpd2dq */
7673  case 0xf30fe6: /* cvtdq2pd */
7674  case 0x660fe8: /* psubsb */
7675  case 0x660fe9: /* psubsw */
7676  case 0x660fea: /* pminsw */
7677  case 0x660feb: /* por */
7678  case 0x660fec: /* paddsb */
7679  case 0x660fed: /* paddsw */
7680  case 0x660fee: /* pmaxsw */
7681  case 0x660fef: /* pxor */
7682  case 0xf20ff0: /* lddqu */
7683  case 0x660ff1: /* psllw */
7684  case 0x660ff2: /* pslld */
7685  case 0x660ff3: /* psllq */
7686  case 0x660ff4: /* pmuludq */
7687  case 0x660ff5: /* pmaddwd */
7688  case 0x660ff6: /* psadbw */
7689  case 0x660ff8: /* psubb */
7690  case 0x660ff9: /* psubw */
7691  case 0x660ffa: /* psubd */
7692  case 0x660ffb: /* psubq */
7693  case 0x660ffc: /* paddb */
7694  case 0x660ffd: /* paddw */
7695  case 0x660ffe: /* paddd */
7696  if (i386_record_modrm (&ir))
7697  return -1;
7698  ir.reg |= rex_r;
7699  if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg))
7700  goto no_support;
7702  I387_XMM0_REGNUM (tdep) + ir.reg);
7703  if ((opcode & 0xfffffffc) == 0x660f3a60)
7705  break;
7706 
7707  case 0x0f11: /* movups */
7708  case 0x660f11: /* movupd */
7709  case 0xf30f11: /* movss */
7710  case 0xf20f11: /* movsd */
7711  case 0x0f13: /* movlps */
7712  case 0x660f13: /* movlpd */
7713  case 0x0f17: /* movhps */
7714  case 0x660f17: /* movhpd */
7715  case 0x0f29: /* movaps */
7716  case 0x660f29: /* movapd */
7717  case 0x660f3a14: /* pextrb */
7718  case 0x660f3a15: /* pextrw */
7719  case 0x660f3a16: /* pextrd pextrq */
7720  case 0x660f3a17: /* extractps */
7721  case 0x660f7f: /* movdqa */
7722  case 0xf30f7f: /* movdqu */
7723  if (i386_record_modrm (&ir))
7724  return -1;
7725  if (ir.mod == 3)
7726  {
7727  if (opcode == 0x0f13 || opcode == 0x660f13
7728  || opcode == 0x0f17 || opcode == 0x660f17)
7729  goto no_support;
7730  ir.rm |= ir.rex_b;
7731  if (!i386_xmm_regnum_p (gdbarch,
7732  I387_XMM0_REGNUM (tdep) + ir.rm))
7733  goto no_support;
7735  I387_XMM0_REGNUM (tdep) + ir.rm);
7736  }
7737  else
7738  {
7739  switch (opcode)
7740  {
7741  case 0x660f3a14:
7742  ir.ot = OT_BYTE;
7743  break;
7744  case 0x660f3a15:
7745  ir.ot = OT_WORD;
7746  break;
7747  case 0x660f3a16:
7748  ir.ot = OT_LONG;
7749  break;
7750  case 0x660f3a17:
7751  ir.ot = OT_QUAD;
7752  break;
7753  default:
7754  ir.ot = OT_DQUAD;
7755  break;
7756  }
7757  if (i386_record_lea_modrm (&ir))
7758  return -1;
7759  }
7760  break;
7761 
7762  case 0x0f2b: /* movntps */
7763  case 0x660f2b: /* movntpd */
7764  case 0x0fe7: /* movntq */
7765  case 0x660fe7: /* movntdq */
7766  if (ir.mod == 3)
7767  goto no_support;
7768  if (opcode == 0x0fe7)
7769  ir.ot = OT_QUAD;
7770  else
7771  ir.ot = OT_DQUAD;
7772  if (i386_record_lea_modrm (&ir))
7773  return -1;
7774  break;
7775 
7776  case 0xf30f2c: /* cvttss2si */
7777  case 0xf20f2c: /* cvttsd2si */
7778  case 0xf30f2d: /* cvtss2si */
7779  case 0xf20f2d: /* cvtsd2si */
7780  case 0xf20f38f0: /* crc32 */
7781  case 0xf20f38f1: /* crc32 */
7782  case 0x0f50: /* movmskps */
7783  case 0x660f50: /* movmskpd */
7784  case 0x0fc5: /* pextrw */
7785  case 0x660fc5: /* pextrw */
7786  case 0x0fd7: /* pmovmskb */
7787  case 0x660fd7: /* pmovmskb */
7789  break;
7790 
7791  case 0x0f3800: /* pshufb */
7792  case 0x0f3801: /* phaddw */
7793  case 0x0f3802: /* phaddd */
7794  case 0x0f3803: /* phaddsw */
7795  case 0x0f3804: /* pmaddubsw */
7796  case 0x0f3805: /* phsubw */
7797  case 0x0f3806: /* phsubd */
7798  case 0x0f3807: /* phsubsw */
7799  case 0x0f3808: /* psignb */
7800  case 0x0f3809: /* psignw */
7801  case 0x0f380a: /* psignd */
7802  case 0x0f380b: /* pmulhrsw */
7803  case 0x0f381c: /* pabsb */
7804  case 0x0f381d: /* pabsw */
7805  case 0x0f381e: /* pabsd */
7806  case 0x0f382b: /* packusdw */
7807  case 0x0f3830: /* pmovzxbw */
7808  case 0x0f3831: /* pmovzxbd */
7809  case 0x0f3832: /* pmovzxbq */
7810  case 0x0f3833: /* pmovzxwd */
7811  case 0x0f3834: /* pmovzxwq */
7812  case 0x0f3835: /* pmovzxdq */
7813  case 0x0f3837: /* pcmpgtq */
7814  case 0x0f3838: /* pminsb */
7815  case 0x0f3839: /* pminsd */
7816  case 0x0f383a: /* pminuw */
7817  case 0x0f383b: /* pminud */
7818  case 0x0f383c: /* pmaxsb */
7819  case 0x0f383d: /* pmaxsd */
7820  case 0x0f383e: /* pmaxuw */
7821  case 0x0f383f: /* pmaxud */
7822  case 0x0f3840: /* pmulld */
7823  case 0x0f3841: /* phminposuw */
7824  case 0x0f3a0f: /* palignr */
7825  case 0x0f60: /* punpcklbw */
7826  case 0x0f61: /* punpcklwd */
7827  case 0x0f62: /* punpckldq */
7828  case 0x0f63: /* packsswb */
7829  case 0x0f64: /* pcmpgtb */
7830  case 0x0f65: /* pcmpgtw */
7831  case 0x0f66: /* pcmpgtd */
7832  case 0x0f67: /* packuswb */
7833  case 0x0f68: /* punpckhbw */
7834  case 0x0f69: /* punpckhwd */
7835  case 0x0f6a: /* punpckhdq */
7836  case 0x0f6b: /* packssdw */
7837  case 0x0f6e: /* movd */
7838  case 0x0f6f: /* movq */
7839  case 0x0f70: /* pshufw */
7840  case 0x0f74: /* pcmpeqb */
7841  case 0x0f75: /* pcmpeqw */
7842  case 0x0f76: /* pcmpeqd */
7843  case 0x0fc4: /* pinsrw */
7844  case 0x0fd1: /* psrlw */
7845  case 0x0fd2: /* psrld */
7846  case 0x0fd3: /* psrlq */
7847  case 0x0fd4: /* paddq */
7848  case 0x0fd5: /* pmullw */
7849  case 0xf20fd6: /* movdq2q */
7850  case 0x0fd8: /* psubusb */
7851  case 0x0fd9: /* psubusw */
7852  case 0x0fda: /* pminub */
7853  case 0x0fdb: /* pand */
7854  case 0x0fdc: /* paddusb */
7855  case 0x0fdd: /* paddusw */
7856  case 0x0fde: /* pmaxub */
7857  case 0x0fdf: /* pandn */
7858  case 0x0fe0: /* pavgb */
7859  case 0x0fe1: /* psraw */
7860  case 0x0fe2: /* psrad */
7861  case 0x0fe3: /* pavgw */
7862  case 0x0fe4: /* pmulhuw */
7863  case 0x0fe5: /* pmulhw */
7864  case 0x0fe8: /* psubsb */
7865  case 0x0fe9: /* psubsw */
7866  case 0x0fea: /* pminsw */
7867  case 0x0feb: /* por */
7868  case 0x0fec: /* paddsb */
7869  case 0x0fed: /* paddsw */
7870  case 0x0fee: /* pmaxsw */
7871  case 0x0fef: /* pxor */
7872  case 0x0ff1: /* psllw */
7873  case 0x0ff2: /* pslld */
7874  case 0x0ff3: /* psllq */
7875  case 0x0ff4: /* pmuludq */
7876  case 0x0ff5: /* pmaddwd */
7877  case 0x0ff6: /* psadbw */
7878  case 0x0ff8: /* psubb */
7879  case 0x0ff9: /* psubw */
7880  case 0x0ffa: /* psubd */
7881  case 0x0ffb: /* psubq */
7882  case 0x0ffc: /* paddb */
7883  case 0x0ffd: /* paddw */
7884  case 0x0ffe: /* paddd */
7885  if (i386_record_modrm (&ir))
7886  return -1;
7887  if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg))
7888  goto no_support;
7890  I387_MM0_REGNUM (tdep) + ir.reg);
7891  break;
7892 
7893  case 0x0f71: /* psllw */
7894  case 0x0f72: /* pslld */
7895  case 0x0f73: /* psllq */
7896  if (i386_record_modrm (&ir))
7897  return -1;
7898  if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7899  goto no_support;
7901  I387_MM0_REGNUM (tdep) + ir.rm);
7902  break;
7903 
7904  case 0x660f71: /* psllw */
7905  case 0x660f72: /* pslld */
7906  case 0x660f73: /* psllq */
7907  if (i386_record_modrm (&ir))
7908  return -1;
7909  ir.rm |= ir.rex_b;
7910  if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm))
7911  goto no_support;
7913  I387_XMM0_REGNUM (tdep) + ir.rm);
7914  break;
7915 
7916  case 0x0f7e: /* movd */
7917  case 0x660f7e: /* movd */
7918  if (i386_record_modrm (&ir))
7919  return -1;
7920  if (ir.mod == 3)
7922  else
7923  {
7924  if (ir.dflag == 2)
7925  ir.ot = OT_QUAD;
7926  else
7927  ir.ot = OT_LONG;
7928  if (i386_record_lea_modrm (&ir))
7929  return -1;
7930  }
7931  break;
7932 
7933  case 0x0f7f: /* movq */
7934  if (i386_record_modrm (&ir))
7935  return -1;
7936  if (ir.mod == 3)
7937  {
7938  if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm))
7939  goto no_support;
7941  I387_MM0_REGNUM (tdep) + ir.rm);
7942  }
7943  else
7944  {
7945  ir.ot = OT_QUAD;
7946  if (i386_record_lea_modrm (&ir))
7947  return -1;
7948  }
7949  break;
7950 
7951  case 0xf30fb8: /* popcnt */
7952  if (i386_record_modrm (&ir))
7953  return -1;
7956  break;
7957 
7958  case 0x660fd6: /* movq */
7959  if (i386_record_modrm (&ir))
7960  return -1;
7961  if (ir.mod == 3)
7962  {
7963  ir.rm |= ir.rex_b;
7964  if (!i386_xmm_regnum_p (gdbarch,
7965  I387_XMM0_REGNUM (tdep) + ir.rm))
7966  goto no_support;
7968  I387_XMM0_REGNUM (tdep) + ir.rm);
7969  }
7970  else
7971  {
7972  ir.ot = OT_QUAD;
7973  if (i386_record_lea_modrm (&ir))
7974  return -1;
7975  }
7976  break;
7977 
7978  case 0x660f3817: /* ptest */
7979  case 0x0f2e: /* ucomiss */
7980  case 0x660f2e: /* ucomisd */
7981  case 0x0f2f: /* comiss */
7982  case 0x660f2f: /* comisd */
7984  break;
7985 
7986  case 0x0ff7: /* maskmovq */
7989  &addr);
7990  if (record_full_arch_list_add_mem (addr, 64))
7991  return -1;
7992  break;
7993 
7994  case 0x660ff7: /* maskmovdqu */
7997  &addr);
7998  if (record_full_arch_list_add_mem (addr, 128))
7999  return -1;
8000  break;
8001 
8002  default:
8003  goto no_support;
8004  break;
8005  }
8006  break;
8007 
8008  default:
8009  goto no_support;
8010  break;
8011  }
8012 
8013  /* In the future, maybe still need to deal with need_dasm. */
8016  return -1;
8017 
8018  return 0;
8019 
8020  no_support:
8021  printf_unfiltered (_("Process record does not support instruction 0x%02x "
8022  "at address %s.\n"),
8023  (unsigned int) (opcode),
8024  paddress (gdbarch, ir.orig_addr));
8025  return -1;
8026 }
8027 
8028 static const int i386_record_regmap[] =
8029 {
8032  0, 0, 0, 0, 0, 0, 0, 0,
8035 };
8036 
8037 /* Check that the given address appears suitable for a fast
8038  tracepoint, which on x86-64 means that we need an instruction of at
8039  least 5 bytes, so that we can overwrite it with a 4-byte-offset
8040  jump and not have to worry about program jumps to an address in the
8041  middle of the tracepoint jump. On x86, it may be possible to use
8042  4-byte jumps with a 2-byte offset to a trampoline located in the
8043  bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8044  of instruction to replace, and 0 if not, plus an explanatory
8045  string. */
8046 
8047 static int
8048 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch,
8049  CORE_ADDR addr, int *isize, char **msg)
8050 {
8051  int len, jumplen;
8052  static struct ui_file *gdb_null = NULL;
8053 
8054  /* Ask the target for the minimum instruction length supported. */
8056 
8057  if (jumplen < 0)
8058  {
8059  /* If the target does not support the get_min_fast_tracepoint_insn_len
8060  operation, assume that fast tracepoints will always be implemented
8061  using 4-byte relative jumps on both x86 and x86-64. */
8062  jumplen = 5;
8063  }
8064  else if (jumplen == 0)
8065  {
8066  /* If the target does support get_min_fast_tracepoint_insn_len but
8067  returns zero, then the IPA has not loaded yet. In this case,
8068  we optimistically assume that truncated 2-byte relative jumps
8069  will be available on x86, and compensate later if this assumption
8070  turns out to be incorrect. On x86-64 architectures, 4-byte relative
8071  jumps will always be used. */
8072  jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4;
8073  }
8074 
8075  /* Dummy file descriptor for the disassembler. */
8076  if (!gdb_null)
8077  gdb_null = ui_file_new ();
8078 
8079  /* Check for fit. */
8080  len = gdb_print_insn (gdbarch, addr, gdb_null, NULL);
8081  if (isize)
8082  *isize = len;
8083 
8084  if (len < jumplen)
8085  {
8086  /* Return a bit of target-specific detail to add to the caller's
8087  generic failure message. */
8088  if (msg)
8089  *msg = xstrprintf (_("; instruction is only %d bytes long, "
8090  "need at least %d bytes for the jump"),
8091  len, jumplen);
8092  return 0;
8093  }
8094  else
8095  {
8096  if (msg)
8097  *msg = NULL;
8098  return 1;
8099  }
8100 }
8101 
8102 static int
8104  struct tdesc_arch_data *tdesc_data)
8105 {
8106  const struct target_desc *tdesc = tdep->tdesc;
8107  const struct tdesc_feature *feature_core;
8108 
8109  const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx,
8110  *feature_avx512;
8111  int i, num_regs, valid_p;
8112 
8113  if (! tdesc_has_registers (tdesc))
8114  return 0;
8115 
8116  /* Get core registers. */
8117  feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core");
8118  if (feature_core == NULL)
8119  return 0;
8120 
8121  /* Get SSE registers. */
8122  feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse");
8123 
8124  /* Try AVX registers. */
8125  feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx");
8126 
8127  /* Try MPX registers. */
8128  feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx");
8129 
8130  /* Try AVX512 registers. */
8131  feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512");
8132 
8133  valid_p = 1;
8134 
8135  /* The XCR0 bits. */
8136  if (feature_avx512)
8137  {
8138  /* AVX512 register description requires AVX register description. */
8139  if (!feature_avx)
8140  return 0;
8141 
8143 
8144  /* It may have been set by OSABI initialization function. */
8145  if (tdep->k0_regnum < 0)
8146  {
8148  tdep->k0_regnum = I386_K0_REGNUM;
8149  }
8150 
8151  for (i = 0; i < I387_NUM_K_REGS; i++)
8152  valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8153  tdep->k0_regnum + i,
8154  i386_k_names[i]);
8155 
8156  if (tdep->num_zmm_regs == 0)
8157  {
8159  tdep->num_zmm_regs = 8;
8161  }
8162 
8163  for (i = 0; i < tdep->num_zmm_regs; i++)
8164  valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8165  tdep->zmm0h_regnum + i,
8166  tdep->zmmh_register_names[i]);
8167 
8168  for (i = 0; i < tdep->num_xmm_avx512_regs; i++)
8169  valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8170  tdep->xmm16_regnum + i,
8171  tdep->xmm_avx512_register_names[i]);
8172 
8173  for (i = 0; i < tdep->num_ymm_avx512_regs; i++)
8174  valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data,
8175  tdep->ymm16h_regnum + i,
8176  tdep->ymm16h_register_names[i]);
8177  }
8178  if (feature_avx)
8179  {
8180  /* AVX register description requires SSE register description. */
8181  if (!feature_sse)
8182  return 0;
8183 
8184  if (!feature_avx512)
8185  tdep->xcr0 = X86_XSTATE_AVX_MASK;
8186 
8187  /* It may have been set by OSABI initialization function. */
8188  if (tdep->num_ymm_regs == 0)
8189  {
8191  tdep->num_ymm_regs = 8;
8193  }
8194 
8195  for (i = 0; i < tdep->num_ymm_regs; i++)
8196  valid_p &= tdesc_numbered_register (feature_avx, tdesc_data,
8197  tdep->ymm0h_regnum + i,
8198  tdep->ymmh_register_names[i]);
8199  }
8200  else if (feature_sse)
8201  tdep->xcr0 = X86_XSTATE_SSE_MASK;
8202  else
8203  {
8204  tdep->xcr0 = X86_XSTATE_X87_MASK;
8205  tdep->num_xmm_regs = 0;
8206  }
8207 
8208  num_regs = tdep->num_core_regs;
8209  for (i = 0; i < num_regs; i++)
8210  valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i,
8211  tdep->register_names[i]);
8212 
8213  if (feature_sse)
8214  {
8215  /* Need to include %mxcsr, so add one. */
8216  num_regs += tdep->num_xmm_regs + 1;
8217  for (; i < num_regs; i++)
8218  valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i,
8219  tdep->register_names[i]);
8220  }
8221 
8222  if (feature_mpx)
8223  {
8224  tdep->xcr0 |= X86_XSTATE_MPX_MASK;
8225 
8226  if (tdep->bnd0r_regnum < 0)
8227  {
8231  }
8232 
8233  for (i = 0; i < I387_NUM_MPX_REGS; i++)
8234  valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data,
8235  I387_BND0R_REGNUM (tdep) + i,
8236  tdep->mpx_register_names[i]);
8237  }
8238 
8239  return valid_p;
8240 }
8241 
8242 
8243 static struct gdbarch *
8244 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
8245 {
8246  struct gdbarch_tdep *tdep;
8247  struct gdbarch *gdbarch;
8248  struct tdesc_arch_data *tdesc_data;
8249  const struct target_desc *tdesc;
8250  int mm0_regnum;
8251  int ymm0_regnum;
8252  int bnd0_regnum;
8253  int num_bnd_cooked;
8254  int k0_regnum;
8255  int zmm0_regnum;
8256 
8257  /* If there is already a candidate, use it. */
8258  arches = gdbarch_list_lookup_by_info (arches, &info);
8259  if (arches != NULL)
8260  return arches->gdbarch;
8261 
8262  /* Allocate space for the new architecture. */
8263  tdep = XCNEW (struct gdbarch_tdep);
8264  gdbarch = gdbarch_alloc (&info, tdep);
8265 
8266  /* General-purpose registers. */
8267  tdep->gregset_reg_offset = NULL;
8269  tdep->sizeof_gregset = 0;
8270 
8271  /* Floating-point registers. */
8273  tdep->fpregset = &i386_fpregset;
8274 
8275  /* The default settings include the FPU registers, the MMX registers
8276  and the SSE registers. This can be overridden for a specific ABI
8277  by adjusting the members `st0_regnum', `mm0_regnum' and
8278  `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8279  will show up in the output of "info all-registers". */
8280 
8281  tdep->st0_regnum = I386_ST0_REGNUM;
8282 
8283  /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8284  tdep->num_xmm_regs = I386_NUM_XREGS - 1;
8285 
8286  tdep->jb_pc_offset = -1;
8288  tdep->sigtramp_start = 0;
8289  tdep->sigtramp_end = 0;
8290  tdep->sigtramp_p = i386_sigtramp_p;
8291  tdep->sigcontext_addr = NULL;
8292  tdep->sc_reg_offset = NULL;
8293  tdep->sc_pc_offset = -1;
8294  tdep->sc_sp_offset = -1;
8295 
8296  tdep->xsave_xcr0_offset = -1;
8297 
8299 
8300  set_gdbarch_long_long_align_bit (gdbarch, 32);
8301 
8302  /* The format used for `long double' on almost all i386 targets is
8303  the i387 extended floating-point format. In fact, of all targets
8304  in the GCC 2.95 tree, only OSF/1 does it different, and insists
8305  on having a `long double' that's not `long' at all. */
8307 
8308  /* Although the i387 extended floating-point has only 80 significant
8309  bits, a `long double' actually takes up 96, probably to enforce
8310  alignment. */
8311  set_gdbarch_long_double_bit (gdbarch, 96);
8312 
8313  /* Register numbers of various important registers. */
8314  set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
8315  set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
8316  set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
8317  set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
8318 
8319  /* NOTE: kettenis/20040418: GCC does have two possible register
8320  numbering schemes on the i386: dbx and SVR4. These schemes
8321  differ in how they number %ebp, %esp, %eflags, and the
8322  floating-point registers, and are implemented by the arrays
8323  dbx_register_map[] and svr4_dbx_register_map in
8324  gcc/config/i386.c. GCC also defines a third numbering scheme in
8325  gcc/config/i386.c, which it designates as the "default" register
8326  map used in 64bit mode. This last register numbering scheme is
8327  implemented in dbx64_register_map, and is used for AMD64; see
8328  amd64-tdep.c.
8329 
8330  Currently, each GCC i386 target always uses the same register
8331  numbering scheme across all its supported debugging formats
8332  i.e. SDB (COFF), stabs and DWARF 2. This is because
8333  gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8334  DBX_REGISTER_NUMBER macro which is defined by each target's
8335  respective config header in a manner independent of the requested
8336  output debugging format.
8337 
8338  This does not match the arrangement below, which presumes that
8339  the SDB and stabs numbering schemes differ from the DWARF and
8340  DWARF 2 ones. The reason for this arrangement is that it is
8341  likely to get the numbering scheme for the target's
8342  default/native debug format right. For targets where GCC is the
8343  native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8344  targets where the native toolchain uses a different numbering
8345  scheme for a particular debug format (stabs-in-ELF on Solaris)
8346  the defaults below will have to be overridden, like
8347  i386_elf_init_abi() does. */
8348 
8349  /* Use the dbx register numbering scheme for stabs and COFF. */
8352 
8353  /* Use the SVR4 register numbering scheme for DWARF 2. */
8355 
8356  /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8357  be in use on any of the supported i386 targets. */
8358 
8360 
8362 
8363  /* Call dummy code. */
8368 
8372 
8374 
8376 
8377  /* Stack grows downward. */
8379 
8381  set_gdbarch_decr_pc_after_break (gdbarch, 1);
8383 
8384  set_gdbarch_frame_args_skip (gdbarch, 8);
8385 
8387 
8389 
8391 
8392  /* Add the i386 register groups. */
8393  i386_add_reggroups (gdbarch);
8395 
8396  /* Helper for function argument information. */
8398 
8399  /* Hook the function epilogue frame unwinder. This unwinder is
8400  appended to the list first, so that it supercedes the DWARF
8401  unwinder in function epilogues (where the DWARF unwinder
8402  currently fails). */
8403  frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind);
8404 
8405  /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8406  to the list before the prologue-based unwinders, so that DWARF
8407  CFI info will be used if it is available. */
8408  dwarf2_append_unwinders (gdbarch);
8409 
8410  frame_base_set_default (gdbarch, &i386_frame_base);
8411 
8412  /* Pseudo registers may be changed by amd64_init_abi. */
8416 
8419 
8420  /* Override the normal target description method to make the AVX
8421  upper halves anonymous. */
8423 
8424  /* Even though the default ABI only includes general-purpose registers,
8425  floating-point registers and the SSE registers, we have to leave a
8426  gap for the upper AVX, MPX and AVX512 registers. */
8428 
8430 
8431  /* Get the x86 target description from INFO. */
8432  tdesc = info.target_desc;
8433  if (! tdesc_has_registers (tdesc))
8434  tdesc = tdesc_i386;
8435  tdep->tdesc = tdesc;
8436 
8439 
8440  /* No upper YMM registers. */
8441  tdep->ymmh_register_names = NULL;
8442  tdep->ymm0h_regnum = -1;
8443 
8444  /* No upper ZMM registers. */
8445  tdep->zmmh_register_names = NULL;
8446  tdep->zmm0h_regnum = -1;
8447 
8448  /* No high XMM registers. */
8449  tdep->xmm_avx512_register_names = NULL;
8450  tdep->xmm16_regnum = -1;
8451 
8452  /* No upper YMM16-31 registers. */
8453  tdep->ymm16h_register_names = NULL;
8454  tdep->ymm16h_regnum = -1;
8455 
8456  tdep->num_byte_regs = 8;
8457  tdep->num_word_regs = 8;
8458  tdep->num_dword_regs = 0;
8459  tdep->num_mmx_regs = 8;
8460  tdep->num_ymm_regs = 0;
8461 
8462  /* No MPX registers. */
8463  tdep->bnd0r_regnum = -1;
8464  tdep->bndcfgu_regnum = -1;
8465 
8466  /* No AVX512 registers. */
8467  tdep->k0_regnum = -1;
8468  tdep->num_zmm_regs = 0;
8469  tdep->num_ymm_avx512_regs = 0;
8470  tdep->num_xmm_avx512_regs = 0;
8471 
8472  tdesc_data = tdesc_data_alloc ();
8473 
8475 
8477 
8481 
8482  /* Hook in ABI-specific overrides, if they have been registered. */
8483  info.tdep_info = (void *) tdesc_data;
8484  gdbarch_init_osabi (info, gdbarch);
8485 
8486  if (!i386_validate_tdesc_p (tdep, tdesc_data))
8487  {
8488  tdesc_data_cleanup (tdesc_data);
8489  xfree (tdep);
8490  gdbarch_free (gdbarch);
8491  return NULL;
8492  }
8493 
8494  num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0);
8495 
8496  /* Wire in pseudo registers. Number of pseudo registers may be
8497  changed. */
8499  + tdep->num_word_regs
8500  + tdep->num_dword_regs
8501  + tdep->num_mmx_regs
8502  + tdep->num_ymm_regs
8503  + num_bnd_cooked
8504  + tdep->num_ymm_avx512_regs
8505  + tdep->num_zmm_regs));
8506 
8507  /* Target description may be changed. */
8508  tdesc = tdep->tdesc;
8509 
8510  tdesc_use_registers (gdbarch, tdesc, tdesc_data);
8511 
8512  /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8514 
8515  /* Make %al the first pseudo-register. */
8516  tdep->al_regnum = gdbarch_num_regs (gdbarch);
8517  tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs;
8518 
8519  ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs;
8520  if (tdep->num_dword_regs)
8521  {
8522  /* Support dword pseudo-register if it hasn't been disabled. */
8523  tdep->eax_regnum = ymm0_regnum;
8524  ymm0_regnum += tdep->num_dword_regs;
8525  }
8526  else
8527  tdep->eax_regnum = -1;
8528 
8529  mm0_regnum = ymm0_regnum;
8530  if (tdep->num_ymm_regs)
8531  {
8532  /* Support YMM pseudo-register if it is available. */
8533  tdep->ymm0_regnum = ymm0_regnum;
8534  mm0_regnum += tdep->num_ymm_regs;
8535  }
8536  else
8537  tdep->ymm0_regnum = -1;
8538 
8539  if (tdep->num_ymm_avx512_regs)
8540  {
8541  /* Support YMM16-31 pseudo registers if available. */
8542  tdep->ymm16_regnum = mm0_regnum;
8543  mm0_regnum += tdep->num_ymm_avx512_regs;
8544  }
8545  else
8546  tdep->ymm16_regnum = -1;
8547 
8548  if (tdep->num_zmm_regs)
8549  {
8550  /* Support ZMM pseudo-register if it is available. */
8551  tdep->zmm0_regnum = mm0_regnum;
8552  mm0_regnum += tdep->num_zmm_regs;
8553  }
8554  else
8555  tdep->zmm0_regnum = -1;
8556 
8557  bnd0_regnum = mm0_regnum;
8558  if (tdep->num_mmx_regs != 0)
8559  {
8560  /* Support MMX pseudo-register if MMX hasn't been disabled. */
8561  tdep->mm0_regnum = mm0_regnum;
8562  bnd0_regnum += tdep->num_mmx_regs;
8563  }
8564  else
8565  tdep->mm0_regnum = -1;
8566 
8567  if (tdep->bnd0r_regnum > 0)
8568  tdep->bnd0_regnum = bnd0_regnum;
8569  else
8570  tdep-> bnd0_regnum = -1;
8571 
8572  /* Hook in the legacy prologue-based unwinders last (fallback). */
8573  frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind);
8574  frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind);
8575  frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind);
8576 
8577  /* If we have a register mapping, enable the generic core file
8578  support, unless it has already been enabled. */
8579  if (tdep->gregset_reg_offset
8583 
8586 
8587  return gdbarch;
8588 }
8589 
8590 static enum gdb_osabi
8592 {
8593  if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
8594  || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
8595  return GDB_OSABI_GO32;
8596 
8597  return GDB_OSABI_UNKNOWN;
8598 }
8599 
8600 
8601 /* Return the target description for a specified XSAVE feature mask. */
8602 
8603 const struct target_desc *
8605 {
8606  switch (xcr0 & X86_XSTATE_ALL_MASK)
8607  {
8610  return tdesc_i386_avx512;
8611  case X86_XSTATE_MPX_MASK:
8612  return tdesc_i386_mpx;
8613  case X86_XSTATE_AVX_MASK:
8614  return tdesc_i386_avx;
8615  default:
8616  return tdesc_i386;
8617  }
8618 }
8619 
8620 #define MPX_BASE_MASK (~(ULONGEST) 0xfff)
8621 
8622 /* Find the bound directory base address. */
8623 
8624 static unsigned long
8626 {
8627  struct regcache *rcache;
8628  struct gdbarch_tdep *tdep;
8629  ULONGEST ret;
8630  enum register_status regstatus;
8631  struct gdb_exception except;
8632 
8633  rcache = get_current_regcache ();
8634  tdep = gdbarch_tdep (get_regcache_arch (rcache));
8635 
8636  regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret);
8637 
8638  if (regstatus != REG_VALID)
8639  error (_("BNDCFGU register invalid, read status %d."), regstatus);
8640 
8641  return ret & MPX_BASE_MASK;
8642 }
8643 
8644 /* Check if the current target is MPX enabled. */
8645 
8646 static int
8648 {
8649  const struct gdbarch_tdep *tdep = gdbarch_tdep (get_current_arch ());
8650  const struct target_desc *tdesc = tdep->tdesc;
8651 
8652  return (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL);
8653 }
8654 
8655 #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */
8656 #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */
8657 #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */
8658 #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */
8659 
8660 /* Find the bound table entry given the pointer location and the base
8661  address of the table. */
8662 
8663 static CORE_ADDR
8665 {
8667  CORE_ADDR offset2;
8668  CORE_ADDR mpx_bd_mask, bd_ptr_r_shift, bd_ptr_l_shift;
8669  CORE_ADDR bt_mask, bt_select_r_shift, bt_select_l_shift;
8670  CORE_ADDR bd_entry_addr;
8671  CORE_ADDR bt_addr;
8672  CORE_ADDR bd_entry;
8673  struct gdbarch *gdbarch = get_current_arch ();
8674  struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8675 
8676 
8677  if (gdbarch_ptr_bit (gdbarch) == 64)
8678  {
8679  mpx_bd_mask = (CORE_ADDR) MPX_BD_MASK;
8680  bd_ptr_r_shift = 20;
8681  bd_ptr_l_shift = 3;
8682  bt_select_r_shift = 3;
8683  bt_select_l_shift = 5;
8684  bt_mask = (CORE_ADDR) MPX_BT_MASK;
8685 
8686  if ( sizeof (CORE_ADDR) == 4)
8687  error (_("operation not supported"));
8688  }
8689  else
8690  {
8691  mpx_bd_mask = MPX_BD_MASK_32;
8692  bd_ptr_r_shift = 12;
8693  bd_ptr_l_shift = 2;
8694  bt_select_r_shift = 2;
8695  bt_select_l_shift = 4;
8696  bt_mask = MPX_BT_MASK_32;
8697  }
8698 
8699  offset1 = ((ptr & mpx_bd_mask) >> bd_ptr_r_shift) << bd_ptr_l_shift;
8700  bd_entry_addr = bd_base + offset1;
8701  bd_entry = read_memory_typed_address (bd_entry_addr, data_ptr_type);
8702 
8703  if ((bd_entry & 0x1) == 0)
8704  error (_("Invalid bounds directory entry at %s."),
8705  paddress (get_current_arch (), bd_entry_addr));
8706 
8707  /* Clearing status bit. */
8708  bd_entry--;
8709  bt_addr = bd_entry & ~bt_select_r_shift;
8710  offset2 = ((ptr & bt_mask) >> bt_select_r_shift) << bt_select_l_shift;
8711 
8712  return bt_addr + offset2;
8713 }
8714 
8715 /* Print routine for the mpx bounds. */
8716 
8717 static void
8719 {
8720  struct ui_out *uiout = current_uiout;
8721  LONGEST size;
8722  struct gdbarch *gdbarch = get_current_arch ();
8723  CORE_ADDR onecompl = ~((CORE_ADDR) 0);
8724  int bounds_in_map = ((~bt_entry[1] == 0 && bt_entry[0] == onecompl) ? 1 : 0);
8725 
8726  if (bounds_in_map == 1)
8727  {
8728  ui_out_text (uiout, "Null bounds on map:");
8729  ui_out_text (uiout, " pointer value = ");
8730  ui_out_field_core_addr (uiout, "pointer-value", gdbarch, bt_entry[2]);
8731  ui_out_text (uiout, ".");
8732  ui_out_text (uiout, "\n");
8733  }
8734  else
8735  {
8736  ui_out_text (uiout, "{lbound = ");
8737  ui_out_field_core_addr (uiout, "lower-bound", gdbarch, bt_entry[0]);
8738  ui_out_text (uiout, ", ubound = ");
8739 
8740  /* The upper bound is stored in 1's complement. */
8741  ui_out_field_core_addr (uiout, "upper-bound", gdbarch, ~bt_entry[1]);
8742  ui_out_text (uiout, "}: pointer value = ");
8743  ui_out_field_core_addr (uiout, "pointer-value", gdbarch, bt_entry[2]);
8744 
8745  if (gdbarch_ptr_bit (gdbarch) == 64)
8746  size = ( (~(int64_t) bt_entry[1]) - (int64_t) bt_entry[0]);
8747  else
8748  size = ( ~((int32_t) bt_entry[1]) - (int32_t) bt_entry[0]);
8749 
8750  /* In case the bounds are 0x0 and 0xffff... the difference will be -1.
8751  -1 represents in this sense full memory access, and there is no need
8752  one to the size. */
8753 
8754  size = (size > -1 ? size + 1 : size);
8755  ui_out_text (uiout, ", size = ");
8756  ui_out_field_fmt (uiout, "size", "%s", plongest (size));
8757 
8758  ui_out_text (uiout, ", metadata = ");
8759  ui_out_field_core_addr (uiout, "metadata", gdbarch, bt_entry[3]);
8760  ui_out_text (uiout, "\n");
8761  }
8762 }
8763 
8764 /* Implement the command "show mpx bound". */
8765 
8766 static void
8767 i386_mpx_info_bounds (char *args, int from_tty)
8768 {
8769  CORE_ADDR bd_base = 0;
8770  CORE_ADDR addr;
8771  CORE_ADDR bt_entry_addr = 0;
8772  CORE_ADDR bt_entry[4];
8773  int i;
8774  struct gdbarch *gdbarch = get_current_arch ();
8775  struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8776 
8777  if (!i386_mpx_enabled ())
8778  {
8779  printf_unfiltered (_("Intel(R) Memory Protection Extensions not "
8780  "supported on this target.\n"));
8781  return;
8782  }
8783 
8784  if (args == NULL)
8785  {
8786  printf_unfiltered (_("Address of pointer variable expected.\n"));
8787  return;
8788  }
8789 
8790  addr = parse_and_eval_address (args);
8791 
8792  bd_base = i386_mpx_bd_base ();
8793  bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8794 
8795  memset (bt_entry, 0, sizeof (bt_entry));
8796 
8797  for (i = 0; i < 4; i++)
8798  bt_entry[i] = read_memory_typed_address (bt_entry_addr
8799  + i * data_ptr_type->length,
8800  data_ptr_type);
8801 
8802  i386_mpx_print_bounds (bt_entry);
8803 }
8804 
8805 /* Implement the command "set mpx bound". */
8806 
8807 static void
8808 i386_mpx_set_bounds (char *args, int from_tty)
8809 {
8810  CORE_ADDR bd_base = 0;
8811  CORE_ADDR addr, lower, upper;
8812  CORE_ADDR bt_entry_addr = 0;
8813  CORE_ADDR bt_entry[2];
8814  const char *input = args;
8815  int i;
8816  struct gdbarch *gdbarch = get_current_arch ();
8817  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8818  struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr;
8819 
8820  if (!i386_mpx_enabled ())
8821  error (_("Intel(R) Memory Protection Extensions not supported\
8822  on this target."));
8823 
8824  if (args == NULL)
8825  error (_("Pointer value expected."));
8826 
8827  addr = value_as_address (parse_to_comma_and_eval (&input));
8828 
8829  if (input[0] == ',')
8830  ++input;
8831  if (input[0] == '\0')
8832  error (_("wrong number of arguments: missing lower and upper bound."));
8833  lower = value_as_address (parse_to_comma_and_eval (&input));
8834 
8835  if (input[0] == ',')
8836  ++input;
8837  if (input[0] == '\0')
8838  error (_("Wrong number of arguments; Missing upper bound."));
8839  upper = value_as_address (parse_to_comma_and_eval (&input));
8840 
8841  bd_base = i386_mpx_bd_base ();
8842  bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base);
8843  for (i = 0; i < 2; i++)
8844  bt_entry[i] = read_memory_typed_address (bt_entry_addr
8845  + i * data_ptr_type->length,
8846  data_ptr_type);
8847  bt_entry[0] = (uint64_t) lower;
8848  bt_entry[1] = ~(uint64_t) upper;
8849 
8850  for (i = 0; i < 2; i++)
8851  write_memory_unsigned_integer (bt_entry_addr + i * data_ptr_type->length,
8852  data_ptr_type->length, byte_order,
8853  bt_entry[i]);
8854 }
8855 
8857 
8858 /* Helper function for the CLI commands. */
8859 
8860 static void
8861 set_mpx_cmd (char *args, int from_tty)
8862 {
8863  help_list (mpx_set_cmdlist, "set mpx ", all_commands, gdb_stdout);
8864 }
8865 
8866 /* Helper function for the CLI commands. */
8867 
8868 static void
8869 show_mpx_cmd (char *args, int from_tty)
8870 {
8871  cmd_show_list (mpx_show_cmdlist, from_tty, "");
8872 }
8873 
8874 /* Provide a prototype to silence -Wmissing-prototypes. */
8875 void _initialize_i386_tdep (void);
8876 
8877 void
8879 {
8880  register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
8881 
8882  /* Add the variable that controls the disassembly flavor. */
8883  add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors,
8884  &disassembly_flavor, _("\
8885 Set the disassembly flavor."), _("\
8886 Show the disassembly flavor."), _("\
8887 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
8888  NULL,
8889  NULL, /* FIXME: i18n: */
8890  &setlist, &showlist);
8891 
8892  /* Add the variable that controls the convention for returning
8893  structs. */
8894  add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions,
8895  &struct_convention, _("\
8896 Set the convention for returning small structs."), _("\
8897 Show the convention for returning small structs."), _("\
8898 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
8899 is \"default\"."),
8900  NULL,
8901  NULL, /* FIXME: i18n: */
8902  &setlist, &showlist);
8903 
8904  /* Add "mpx" prefix for the set commands. */
8905 
8907 Set Intel(R) Memory Protection Extensions specific variables."),
8908  &mpx_set_cmdlist, "set mpx ",
8909  0 /* allow-unknown */, &setlist);
8910 
8911  /* Add "mpx" prefix for the show commands. */
8912 
8914 Show Intel(R) Memory Protection Extensions specific variables."),
8915  &mpx_show_cmdlist, "show mpx ",
8916  0 /* allow-unknown */, &showlist);
8917 
8918  /* Add "bound" command for the show mpx commands list. */
8919 
8921  "Show the memory bounds for a given array/pointer storage\
8922  in the bound table.",
8923  &mpx_show_cmdlist);
8924 
8925  /* Add "bound" command for the set mpx commands list. */
8926 
8928  "Set the memory bounds for a given array/pointer storage\
8929  in the bound table.",
8930  &mpx_set_cmdlist);
8931 
8932  gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
8934 
8935  gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
8937  gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
8939 
8940  /* Initialize the i386-specific register groups. */
8942 
8943  /* Initialize the standard target descriptions. */
8949 
8950  /* Tell remote stub that we support XML target description. */
8951  register_remote_support_xml ("i386");
8952 }
int i386_zmm_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:226
void reggroup_add(struct gdbarch *gdbarch, struct reggroup *group)
Definition: reggroups.c:103
int i386_register_reggroup_p(struct gdbarch *gdbarch, int regnum, struct reggroup *group)
Definition: i386-tdep.c:4437
struct gdbarch * target_gdbarch(void)
Definition: gdbarch.c:5143
void set_gdbarch_num_regs(struct gdbarch *gdbarch, int num_regs)
Definition: gdbarch.c:1909
#define PREFIX_DATA
Definition: i386-tdep.c:4554
uint8_t mod
Definition: i386-tdep.c:4590
void set_gdbarch_frame_align(struct gdbarch *gdbarch, gdbarch_frame_align_ftype frame_align)
Definition: gdbarch.c:2935
#define X86_XSTATE_AVX_MASK
Definition: x86-xstate.h:41
void i387_collect_fsave(const struct regcache *regcache, int regnum, void *fsave)
Definition: i387-tdep.c:502
void set_gdbarch_value_to_register(struct gdbarch *gdbarch, gdbarch_value_to_register_ftype value_to_register)
Definition: gdbarch.c:2457
static int i386_record_lea_modrm(struct i386_record_s *irp)
Definition: i386-tdep.c:4820
void target_terminal_ours(void)
Definition: target.c:491
void i386_supply_gregset(const struct regset *regset, struct regcache *regcache, int regnum, const void *gregs, size_t len)
Definition: i386-tdep.c:3730
ULONGEST extract_unsigned_integer(const gdb_byte *, int, enum bfd_endian)
Definition: findvar.c:84
static CORE_ADDR i386_unwind_pc(struct gdbarch *gdbarch, struct frame_info *next_frame)
Definition: i386-tdep.c:1935
static void initialize_tdesc_i386_mmx(void)
Definition: i386-mmx.c:10
#define I386_NUM_GREGS
Definition: i386-tdep.h:320
struct cmd_list_element * add_prefix_cmd(const char *name, enum command_class theclass, cmd_cfunc_ftype *fun, const char *doc, struct cmd_list_element **prefixlist, const char *prefixname, int allow_unknown, struct cmd_list_element **list)
Definition: cli-decode.c:338
type_code
Definition: gdbtypes.h:85
static void i386_store_return_value(struct gdbarch *gdbarch, struct type *type, struct regcache *regcache, const gdb_byte *valbuf)
Definition: i386-tdep.c:2802
static void i386_go32_init_abi(struct gdbarch_info info, struct gdbarch *gdbarch)
Definition: i386-tdep.c:4383
int jb_pc_offset
Definition: i386-tdep.h:199
int xsave_xcr0_offset
Definition: i386-tdep.h:142
void set_gdbarch_ps_regnum(struct gdbarch *gdbarch, int ps_regnum)
Definition: gdbarch.c:2025
static int i386_svr4_reg_to_regnum(struct gdbarch *gdbarch, int reg)
Definition: i386-tdep.c:509
static struct i386_frame_cache * i386_frame_cache(struct frame_info *this_frame, void **this_cache)
Definition: i386-tdep.c:2048
struct frame_id frame_id_build(CORE_ADDR stack_addr, CORE_ADDR code_addr)
Definition: frame.c:554
#define I387_FOP_REGNUM(tdep)
Definition: i387-tdep.h:61
CORE_ADDR extract_typed_address(const gdb_byte *buf, struct type *type)
Definition: findvar.c:169
void set_gdbarch_get_longjmp_target(struct gdbarch *gdbarch, gdbarch_get_longjmp_target_ftype get_longjmp_target)
Definition: gdbarch.c:2390
int zmm0_regnum
Definition: i386-tdep.h:97
static struct i386_insn * i386_match_insn(CORE_ADDR pc, struct i386_insn *insn_patterns)
Definition: i386-tdep.c:1406
#define PREFIX_ADDR
Definition: i386-tdep.c:4555
struct type * i386_bnd_type
Definition: i386-tdep.h:228
LONGEST sp_offset
Definition: i386-tdep.c:1047
#define target_get_min_fast_tracepoint_insn_len()
Definition: target.h:2129
int xmm16_regnum
Definition: i386-tdep.h:128
CORE_ADDR pc
Definition: i386-tdep.c:1048
void set_tdesc_pseudo_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype *pseudo_name)
int num_core_regs
Definition: i386-tdep.h:119
static int i386_ymmh_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:252
CORE_ADDR get_frame_pc(struct frame_info *frame)
Definition: frame.c:2217
#define I387_NUM_MPX_CTRL_REGS
Definition: i387-tdep.h:45
CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]
Definition: i386-tdep.c:1051
static const char *const valid_conventions[]
Definition: i386-tdep.c:2868
void set_gdbarch_fp0_regnum(struct gdbarch *gdbarch, int fp0_regnum)
Definition: gdbarch.c:2042
#define MSYMBOL_LINKAGE_NAME(symbol)
Definition: symtab.h:409
unsigned short offset1
Definition: go32-nat.c:1070
#define X86_XSTATE_SSE_MASK
Definition: x86-xstate.h:40
struct type * arg_type
Definition: stap-probe.h:46
bfd_vma CORE_ADDR
Definition: common-types.h:41
int i386_k_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:239
const char ** mpx_register_names
Definition: i386-tdep.h:174
static int i386_stap_parse_special_token_three_arg_disp(struct gdbarch *gdbarch, struct stap_parse_info *p)
Definition: i386-tdep.c:4114
void gdbarch_init_osabi(struct gdbarch_info info, struct gdbarch *gdbarch)
Definition: osabi.c:341
void displaced_step_dump_bytes(struct ui_file *file, const gdb_byte *buf, size_t len)
Definition: infrun.c:1615
#define I386_NUM_SAVED_REGS
Definition: i386-tdep.c:1040
static const char att_flavor[]
Definition: i386-tdep.c:555
int target_write_memory(CORE_ADDR memaddr, const gdb_byte *myaddr, ssize_t len)
Definition: target.c:1474
struct reggroup * reggroup_new(const char *name, enum reggroup_type type)
Definition: reggroups.c:39
int i386_process_record(struct gdbarch *gdbarch, struct regcache *regcache, CORE_ADDR input_addr)
Definition: i386-tdep.c:4950
struct type * i386_pseudo_register_type(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:3186
static struct i386_frame_cache * i386_alloc_frame_cache(void)
Definition: i386-tdep.c:1063
int sc_num_regs
Definition: i386-tdep.h:216
#define I387_BND0R_REGNUM(tdep)
Definition: i387-tdep.h:39
const char * ptr
Definition: parser-defs.h:79
void set_gdbarch_stap_parse_special_token(struct gdbarch *gdbarch, gdbarch_stap_parse_special_token_ftype stap_parse_special_token)
Definition: gdbarch.c:4243
static int i386_syscall_p(const gdb_byte *insn, int *lengthp)
Definition: i386-tdep.c:716
void xfree(void *)
Definition: common-utils.c:97
int i386_dword_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:198
static const char default_struct_convention[]
Definition: i386-tdep.c:2865
CORE_ADDR addr
Definition: i386-tdep.c:4585
const char ** ymm16h_register_names
Definition: i386-tdep.h:159
int(* i386_intx80_record)(struct regcache *regcache)
Definition: i386-tdep.h:235
static int i386_stack_frame_destroyed_p(struct gdbarch *gdbarch, CORE_ADDR pc)
Definition: i386-tdep.c:2186
int i386_zmmh_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:213
void store_signed_integer(gdb_byte *, int, enum bfd_endian, LONGEST)
Definition: findvar.c:184
#define PREFIX_REPZ
Definition: i386-tdep.c:4551
int record_full_arch_list_add_reg(struct regcache *regcache, int regnum)
Definition: record-full.c:466
#define X86_XSTATE_MPX_MASK
Definition: x86-xstate.h:42
struct gdbarch * get_regcache_arch(const struct regcache *regcache)
Definition: regcache.c:297
struct value * frame_unwind_got_memory(struct frame_info *frame, int regnum, CORE_ADDR addr)
Definition: frame-unwind.c:228
void write_memory_unsigned_integer(CORE_ADDR addr, int len, enum bfd_endian byte_order, ULONGEST value)
Definition: corefile.c:412
void add_setshow_enum_cmd(const char *name, enum command_class theclass, const char *const *enumlist, const char **var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_sfunc_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
Definition: cli-decode.c:487
void set_tdesc_pseudo_register_type(struct gdbarch *gdbarch, gdbarch_register_type_ftype *pseudo_type)
CORE_ADDR sigtramp_start
Definition: i386-tdep.h:205
int ymm16_regnum
Definition: i386-tdep.h:134
void set_gdbarch_skip_trampoline_code(struct gdbarch *gdbarch, gdbarch_skip_trampoline_code_ftype skip_trampoline_code)
Definition: gdbarch.c:3084
#define MPX_BT_MASK
Definition: i386-tdep.c:8656
static int i386_convert_register_p(struct gdbarch *gdbarch, int regnum, struct type *type)
Definition: i386-tdep.c:3629
void set_gdbarch_relocate_instruction(struct gdbarch *gdbarch, gdbarch_relocate_instruction_ftype relocate_instruction)
Definition: gdbarch.c:3768
void warning(const char *fmt,...)
Definition: errors.c:26
static const char * i386_zmmh_names[]
Definition: i386-tdep.c:92
void set_gdbarch_gen_return_address(struct gdbarch *gdbarch, gdbarch_gen_return_address_ftype gen_return_address)
Definition: gdbarch.c:4491
CORE_ADDR base
Definition: i386-tdep.c:1045
gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]
Definition: i386-tdep.c:1366
void i387_supply_fxsave(struct regcache *regcache, int regnum, const void *fxsave)
Definition: i387-tdep.c:595
void set_gdbarch_stab_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_stab_reg_to_regnum_ftype stab_reg_to_regnum)
Definition: gdbarch.c:2059
#define TYPE_NAME(thistype)
Definition: gdbtypes.h:1227
static void i386_extract_return_value(struct gdbarch *gdbarch, struct type *type, struct regcache *regcache, gdb_byte *valbuf)
Definition: i386-tdep.c:2751
static const char * i386_zmm_names[]
Definition: i386-tdep.c:86
int num_mmx_regs
Definition: i386-tdep.h:72
int gdbarch_ptr_bit(struct gdbarch *gdbarch)
Definition: gdbarch.c:1690
void set_gdbarch_sdb_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_sdb_reg_to_regnum_ftype sdb_reg_to_regnum)
Definition: gdbarch.c:2093
void convert_typed_floating(const void *from, const struct type *from_type, void *to, const struct type *to_type)
Definition: doublest.c:862
void set_gdbarch_stap_register_prefixes(struct gdbarch *gdbarch, const char *const *stap_register_prefixes)
Definition: gdbarch.c:4110
void register_remote_support_xml(const char *xml)
Definition: remote.c:4207
static const char * i386_word_names[]
Definition: i386-tdep.c:146
static int i386_svr4_sigtramp_p(struct frame_info *this_frame)
Definition: i386-tdep.c:3917
struct target_desc * tdesc_i386_mmx
Definition: i386-mmx.c:8
struct ui_file * gdb_stdout
Definition: main.c:71
static unsigned long i386_mpx_bd_base(void)
Definition: i386-tdep.c:8625
const struct builtin_type * builtin_type(struct gdbarch *gdbarch)
Definition: gdbtypes.c:4766
const struct regset i386_fpregset
Definition: i386-tdep.c:3824
struct frame_id frame_id_build_unavailable_stack(CORE_ADDR code_addr)
Definition: frame.c:527
int(* i386_syscall_record)(struct regcache *regcache)
Definition: i386-tdep.h:239
void internal_error(const char *file, int line, const char *fmt,...)
Definition: errors.c:50
int num_word_regs
Definition: i386-tdep.h:106
void frame_unwind_register(struct frame_info *frame, int regnum, gdb_byte *buf)
Definition: frame.c:1065
struct displaced_step_closure * i386_displaced_step_copy_insn(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
Definition: i386-tdep.c:775
CORE_ADDR sigtramp_end
Definition: i386-tdep.h:206
const char * tdesc_register_name(struct gdbarch *gdbarch, int regno)
unsigned int record_debug
Definition: record.c:33
struct m32c_reg * pc
Definition: m32c-tdep.c:111
static struct reggroup * i386_sse_reggroup
Definition: i386-tdep.c:4412
return_value_convention
Definition: defs.h:206
const char * arg
Definition: stap-probe.h:32
#define I386_NUM_XREGS
Definition: i386-tdep.h:321
int i386_sigtramp_p(struct frame_info *this_frame)
Definition: i386-tdep.c:3879
#define I387_NUM_MPX_REGS
Definition: i387-tdep.h:43
static CORE_ADDR i386_skip_noop(CORE_ADDR pc)
Definition: i386-tdep.c:1513
int i386_stap_parse_special_token(struct gdbarch *gdbarch, struct stap_parse_info *p)
Definition: i386-tdep.c:4271
void gdbarch_register_osabi_sniffer(enum bfd_architecture arch, enum bfd_flavour flavour, enum gdb_osabi(*sniffer_fn)(bfd *))
Definition: osabi.c:225
void set_gdbarch_register_reggroup_p(struct gdbarch *gdbarch, gdbarch_register_reggroup_p_ftype register_reggroup_p)
Definition: gdbarch.c:3350
int i386_xmm_avx512_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:338
static int i386_print_insn(bfd_vma pc, struct disassemble_info *info)
Definition: i386-tdep.c:3893
#define I387_NUM_XMM_REGS(tdep)
Definition: i387-tdep.h:33
#define ON_STACK
Definition: inferior.h:258
#define I387_NUM_BND_REGS
Definition: i387-tdep.h:44
#define I386_MAX_MATCHED_INSN_LEN
Definition: i386-tdep.c:1359
CORE_ADDR(* sigcontext_addr)(struct frame_info *)
Definition: alpha-tdep.h:82
static void initialize_tdesc_i386(void)
Definition: i386.c:10
static const char pcc_struct_convention[]
Definition: i386-tdep.c:2866
int sc_pc_offset
Definition: alpha-tdep.h:95
static struct type * i386_ymm_type(struct gdbarch *gdbarch)
Definition: i386-tdep.c:3091
Definition: ax.h:95
unwind_stop_reason
Definition: frame.h:486
#define I386_AVX512_NUM_REGS
Definition: i386-tdep.h:326
int i386_fp_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:364
int yquery(const char *ctlstr,...)
Definition: utils.c:1347
struct type * arch_composite_type(struct gdbarch *gdbarch, char *name, enum type_code code)
Definition: gdbtypes.c:4682
struct gdbarch_list * gdbarch_list_lookup_by_info(struct gdbarch_list *arches, const struct gdbarch_info *info)
Definition: gdbarch.c:4985
void mark_value_bytes_unavailable(struct value *value, int offset, int length)
Definition: value.c:593
CORE_ADDR skip_prologue_using_sal(struct gdbarch *gdbarch, CORE_ADDR func_addr)
Definition: symtab.c:3882
static struct value * i386_frame_prev_register(struct frame_info *this_frame, void **this_cache, int regnum)
Definition: i386-tdep.c:2108
#define PREFIX_LOCK
Definition: i386-tdep.c:4553
struct reggroup *const restore_reggroup
Definition: reggroups.c:298
void i387_supply_fsave(struct regcache *regcache, int regnum, const void *fsave)
Definition: i387-tdep.c:447
void ax_reg(struct agent_expr *x, int reg)
Definition: ax-general.c:290
int num_zmm_regs
Definition: i386-tdep.h:93
int gdbarch_num_regs(struct gdbarch *gdbarch)
Definition: gdbarch.c:1898
int ymm0h_regnum
Definition: i386-tdep.h:149
static void i386_value_to_register(struct frame_info *frame, int regnum, struct type *type, const gdb_byte *from)
Definition: i386-tdep.c:3698
#define I387_ST0_REGNUM(tdep)
Definition: i387-tdep.h:32
struct reggroup *const all_reggroup
Definition: reggroups.c:296
uint8_t rex_x
Definition: i386-tdep.c:4592
#define _(String)
Definition: gdb_locale.h:40
size_t sizeof_fpregset
Definition: i386-tdep.h:64
static struct i386_frame_cache * i386_epilogue_frame_cache(struct frame_info *this_frame, void **this_cache)
Definition: i386-tdep.c:2217
static int i386_mpx_ctrl_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:404
void gdbarch_free(struct gdbarch *arch)
Definition: gdbarch.c:460
void set_gdbarch_dwarf2_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_dwarf2_reg_to_regnum_ftype dwarf2_reg_to_regnum)
Definition: gdbarch.c:2110
struct gdbarch_tdep_info * tdep_info
Definition: gdbarch.h:1560
void i386_displaced_step_fixup(struct gdbarch *gdbarch, struct displaced_step_closure *closure, CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
Definition: i386-tdep.c:812
struct gdbarch_tdep * gdbarch_tdep(struct gdbarch *gdbarch)
Definition: gdbarch.c:1402
uint8_t rex_b
Definition: i386-tdep.c:4593
void set_gdbarch_long_long_align_bit(struct gdbarch *gdbarch, int long_long_align_bit)
Definition: gdbarch.c:1551
static void i386_add_reggroups(struct gdbarch *gdbarch)
Definition: i386-tdep.c:4423
void set_gdbarch_gnu_triplet_regexp(struct gdbarch *gdbarch, gdbarch_gnu_triplet_regexp_ftype gnu_triplet_regexp)
Definition: gdbarch.c:4733
static int i386_fast_tracepoint_valid_at(struct gdbarch *gdbarch, CORE_ADDR addr, int *isize, char **msg)
Definition: i386-tdep.c:8048
static void initialize_tdesc_i386_avx512(void)
Definition: i386-avx512.c:10
static int i386_ret_p(const gdb_byte *insn)
Definition: i386-tdep.c:683
void tdesc_data_cleanup(void *data_untyped)
static void i386_init_reggroups(void)
Definition: i386-tdep.c:4416
#define TYPE_FIELD_TYPE(thistype, n)
Definition: gdbtypes.h:1368
#define END_CATCH
struct type * type
Definition: ax-gdb.h:82
void ui_out_field_fmt(struct ui_out *uiout, const char *fldname, const char *format,...)
Definition: ui-out.c:556
int num_ymm_regs
Definition: i386-tdep.h:79
#define VALUE_LVAL(val)
Definition: value.h:411
char ** register_names
Definition: frv-tdep.c:90
struct value * allocate_value(struct type *type)
Definition: value.c:962
void frame_unwind_append_unwinder(struct gdbarch *gdbarch, const struct frame_unwind *unwinder)
Definition: frame-unwind.c:78
Definition: ui-out.c:99
struct regcache * get_current_regcache(void)
Definition: regcache.c:541
struct type * builtin_int32
Definition: gdbtypes.h:1518
void ui_out_text(struct ui_out *uiout, const char *string)
Definition: ui-out.c:582
int ymm0_regnum
Definition: i386-tdep.h:83
int i386_fpc_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:376
static const char * i386_k_names[]
Definition: i386-tdep.c:98
#define I386_MAX_INSN_LEN
Definition: i386-tdep.h:370
int num_xmm_avx512_regs
Definition: i386-tdep.h:125
static enum unwind_stop_reason i386_frame_unwind_stop_reason(struct frame_info *this_frame, void **this_cache)
Definition: i386-tdep.c:2092
static void i386_relocate_instruction(struct gdbarch *gdbarch, CORE_ADDR *to, CORE_ADDR oldloc)
Definition: i386-tdep.c:951
#define FRAME_OBSTACK_ZALLOC(TYPE)
Definition: frame.h:660
static int i386_mmx_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:161
void store_unsigned_integer(gdb_byte *, int, enum bfd_endian, ULONGEST)
Definition: findvar.c:212
const char * paddress(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: utils.c:2743
static CORE_ADDR i386_analyze_struct_return(CORE_ADDR pc, CORE_ADDR current_pc, struct i386_frame_cache *cache)
Definition: i386-tdep.c:1149
void set_gdbarch_stap_register_indirection_suffixes(struct gdbarch *gdbarch, const char *const *stap_register_indirection_suffixes)
Definition: gdbarch.c:4161
struct value * frame_unwind_got_constant(struct frame_info *frame, int regnum, ULONGEST val)
Definition: frame-unwind.c:241
int i386_xmm_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:323
void i387_value_to_register(struct frame_info *frame, int regnum, struct type *type, const gdb_byte *from)
Definition: i387-tdep.c:390
ULONGEST read_code_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition: corefile.c:341
static struct i386_frame_cache * i386_sigtramp_frame_cache(struct frame_info *this_frame, void **this_cache)
Definition: i386-tdep.c:2400
struct compunit_symtab * find_pc_compunit_symtab(CORE_ADDR pc)
Definition: symtab.c:3051
int target_read_code(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition: target.c:1456
static int i386_match_pattern(CORE_ADDR pc, struct i386_insn pattern)
Definition: i386-tdep.c:1372
Definition: regset.h:34
int i386_byte_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:176
int i386_ymm_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:267
int gdbarch_num_pseudo_regs(struct gdbarch *gdbarch)
Definition: gdbarch.c:1916
#define TRY
void set_gdbarch_stap_integer_prefixes(struct gdbarch *gdbarch, const char *const *stap_integer_prefixes)
Definition: gdbarch.c:4076
struct type * i386_zmm_type
Definition: i386-tdep.h:226
int(* i386_sysenter_record)(struct regcache *regcache)
Definition: i386-tdep.h:237
static int i386_absolute_call_p(const gdb_byte *insn)
Definition: i386-tdep.c:662
struct parser_state pstate
Definition: stap-probe.h:35
struct reggroup *const float_reggroup
Definition: reggroups.c:293
static const char * disassembly_flavor
Definition: i386-tdep.c:563
static const char * i386_ymmh_names[]
Definition: i386-tdep.c:110
int tdesc_numbered_register(const struct tdesc_feature *feature, struct tdesc_arch_data *data, int regno, const char *name)
void frame_base_set_default(struct gdbarch *gdbarch, const struct frame_base *default_base)
Definition: frame-base.c:94
static int i386_16_byte_align_p(struct type *type)
Definition: i386-tdep.c:2606
static const char * i386_mmx_names[]
Definition: i386-tdep.c:130
struct cmd_list_element * setlist
Definition: cli-cmds.c:135
const char *const name
Definition: aarch64-tdep.c:68
static const char *const valid_flavors[]
Definition: i386-tdep.c:557
static const char * i386_register_name(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:419
struct type * builtin_int128
Definition: gdbtypes.h:1522
int * from
Definition: varobj.h:282
void write_exp_elt_longcst(struct parser_state *ps, LONGEST expelt)
Definition: parse.c:276
void set_gdbarch_pseudo_register_write(struct gdbarch *gdbarch, gdbarch_pseudo_register_write_ftype pseudo_register_write)
Definition: gdbarch.c:1891
void set_gdbarch_pseudo_register_read_value(struct gdbarch *gdbarch, gdbarch_pseudo_register_read_value_ftype pseudo_register_read_value)
Definition: gdbarch.c:1867
struct type * check_typedef(struct type *type)
Definition: gdbtypes.c:2217
LONGEST read_memory_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition: corefile.c:311
ULONGEST gdbarch_max_insn_length(struct gdbarch *gdbarch)
Definition: gdbarch.c:3632
int gdbarch_iterate_over_regset_sections_p(struct gdbarch *gdbarch)
Definition: gdbarch.c:3381
static CORE_ADDR i386_skip_prologue(struct gdbarch *gdbarch, CORE_ADDR start_pc)
Definition: i386-tdep.c:1799
#define CATCH(EXCEPTION, MASK)
struct reggroup *const general_reggroup
Definition: reggroups.c:292
void i387_collect_fxsave(const struct regcache *regcache, int regnum, void *fxsave)
Definition: i387-tdep.c:678
#define I387_FSTAT_REGNUM(tdep)
Definition: i387-tdep.h:55
uint8_t modrm
Definition: i386-tdep.c:4589
static int i386_jmp_p(const gdb_byte *insn)
Definition: i386-tdep.c:648
void i386_svr4_init_abi(struct gdbarch_info info, struct gdbarch *gdbarch)
Definition: i386-tdep.c:4362
static int i386_bndr_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:390
static int i386_insn_is_jump(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: i386-tdep.c:761
static const char reg_struct_convention[]
Definition: i386-tdep.c:2867
#define MPX_BD_MASK_32
Definition: i386-tdep.c:8657
enum struct_return struct_return
Definition: arm-tdep.h:197
static void initialize_tdesc_i386_avx(void)
Definition: i386-avx.c:10
int record_read_memory(struct gdbarch *gdbarch, CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition: record.c:97
void set_gdbarch_insn_is_ret(struct gdbarch *gdbarch, gdbarch_insn_is_ret_ftype insn_is_ret)
Definition: gdbarch.c:4607
CORE_ADDR i386_skip_main_prologue(struct gdbarch *gdbarch, CORE_ADDR pc)
Definition: i386-tdep.c:1901
static int i386_epilogue_frame_sniffer(const struct frame_unwind *self, struct frame_info *this_frame, void **this_prologue_cache)
Definition: i386-tdep.c:2205
register_status
Definition: regcache.h:50
CORE_ADDR find_solib_trampoline_target(struct frame_info *frame, CORE_ADDR pc)
Definition: minsyms.c:1394
static CORE_ADDR i386_push_dummy_code(struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, struct value **args, int nargs, struct type *value_type, CORE_ADDR *real_pc, CORE_ADDR *bp_addr, struct regcache *regcache)
Definition: i386-tdep.c:2631
static struct cmd_list_element * mpx_set_cmdlist
Definition: i386-tdep.c:8856
enum register_status regcache_cooked_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition: regcache.c:837
const char ** ymmh_register_names
Definition: i386-tdep.h:152
struct reggroup *const system_reggroup
Definition: reggroups.c:294
struct target_desc * tdesc_i386_avx
Definition: i386-avx.c:8
void set_gdbarch_sp_regnum(struct gdbarch *gdbarch, int sp_regnum)
Definition: gdbarch.c:1991
struct ui_file * ui_file_new(void)
Definition: ui-file.c:57
struct target_desc * tdesc_i386_avx512
Definition: i386-avx512.c:8
int debug_displaced
Definition: infrun.c:132
void set_gdbarch_decr_pc_after_break(struct gdbarch *gdbarch, CORE_ADDR decr_pc_after_break)
Definition: gdbarch.c:2764
static CORE_ADDR i386_push_dummy_call(struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr)
Definition: i386-tdep.c:2645
struct type * register_type(struct gdbarch *gdbarch, int regnum)
Definition: regcache.c:157
void set_gdbarch_dummy_id(struct gdbarch *gdbarch, gdbarch_dummy_id_ftype dummy_id)
Definition: gdbarch.c:2175
struct type * i387_ext_type
Definition: i386-tdep.h:227
void target_terminal_inferior(void)
Definition: target.c:470
void fprintf_unfiltered(struct ui_file *stream, const char *format,...)
Definition: utils.c:2361
#define I387_XMM0_REGNUM(tdep)
Definition: i387-tdep.h:62
mach_port_t mach_port_t name mach_port_t mach_port_t name error_t int status
Definition: gnu-nat.c:1816
int gdb_print_insn(struct gdbarch *gdbarch, CORE_ADDR memaddr, struct ui_file *stream, int *branch_delay_insns)
Definition: disasm.c:444
struct cmd_list_element * showlist
Definition: cli-cmds.c:143
struct_return
Definition: arm-tdep.h:148
const gdb_byte * value_contents_all(struct value *value)
Definition: value.c:1188
#define TYPE_VECTOR(t)
Definition: gdbtypes.h:287
struct type * builtin_int16
Definition: gdbtypes.h:1516
struct type * i387_ext_type(struct gdbarch *gdbarch)
Definition: i386-tdep.c:2984
struct cmd_list_element * add_cmd(const char *name, enum command_class theclass, cmd_cfunc_ftype *fun, const char *doc, struct cmd_list_element **list)
Definition: cli-decode.c:192
struct target_desc * tdesc_i386
Definition: i386.c:8
struct type * value_enclosing_type(struct value *value)
Definition: value.c:1098
enum bfd_endian gdbarch_byte_order(struct gdbarch *gdbarch)
Definition: gdbarch.c:1420
int num_ymm_avx512_regs
Definition: i386-tdep.h:131
#define I386_SAVE_FPU_ENV_REG_STACK
Definition: i386-tdep.c:4878
static const char * i386_gnu_triplet_regexp(struct gdbarch *gdbarch)
Definition: i386-tdep.c:4322
static CORE_ADDR i386_analyze_prologue(struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR current_pc, struct i386_frame_cache *cache)
Definition: i386-tdep.c:1783
void set_gdbarch_stap_register_indirection_prefixes(struct gdbarch *gdbarch, const char *const *stap_register_indirection_prefixes)
Definition: gdbarch.c:4144
static int i386_record_modrm(struct i386_record_s *irp)
Definition: i386-tdep.c:4603
static void i386_mpx_print_bounds(const CORE_ADDR bt_entry[4])
Definition: i386-tdep.c:8718
static struct type * i386_bnd_type(struct gdbarch *gdbarch)
Definition: i386-tdep.c:3002
Definition: gdbtypes.h:749
int find_pc_partial_function(CORE_ADDR pc, const char **name, CORE_ADDR *address, CORE_ADDR *endaddr)
Definition: blockframe.c:321
#define VALUE_REGNUM(val)
Definition: value.h:440
struct type * init_vector_type(struct type *elt_type, int n)
Definition: gdbtypes.c:1229
static void i386_sigtramp_frame_this_id(struct frame_info *this_frame, void **this_cache, struct frame_id *this_id)
Definition: i386-tdep.c:2463
static int i386_dbx_reg_to_regnum(struct gdbarch *gdbarch, int reg)
Definition: i386-tdep.c:462
static const char * i386_bnd_names[]
Definition: i386-tdep.c:123
static int i386_absolute_jmp_p(const gdb_byte *insn)
Definition: i386-tdep.c:625
static CORE_ADDR i386_follow_jump(struct gdbarch *gdbarch, CORE_ADDR pc)
Definition: i386-tdep.c:1094
void set_gdbarch_register_to_value(struct gdbarch *gdbarch, gdbarch_register_to_value_ftype register_to_value)
Definition: gdbarch.c:2440
static struct reggroup * i386_mmx_reggroup
Definition: i386-tdep.c:4413
void read_code(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition: corefile.c:283
#define I387_FTAG_REGNUM(tdep)
Definition: i387-tdep.h:56
void set_gdbarch_unwind_pc(struct gdbarch *gdbarch, gdbarch_unwind_pc_ftype unwind_pc)
Definition: gdbarch.c:2863
void set_gdbarch_breakpoint_from_pc(struct gdbarch *gdbarch, gdbarch_breakpoint_from_pc_ftype breakpoint_from_pc)
Definition: gdbarch.c:2672
const void * register_reggroup_p
Definition: i386-tdep.h:196
struct gdbarch * get_current_arch(void)
Definition: arch-utils.c:781
int default_frame_sniffer(const struct frame_unwind *self, struct frame_info *this_frame, void **this_prologue_cache)
Definition: frame-unwind.c:170
#define COMPUNIT_PRODUCER(cust)
Definition: symtab.h:1097
struct type * tdesc_find_type(struct gdbarch *gdbarch, const char *id)
#define gdb_assert(expr)
Definition: gdb_assert.h:33
#define I387_YMM0_REGNUM(tdep)
Definition: i387-tdep.h:66
static void show_mpx_cmd(char *args, int from_tty)
Definition: i386-tdep.c:8869
const char * saved_arg
Definition: stap-probe.h:40
#define X86_XSTATE_MPX_AVX512_MASK
Definition: x86-xstate.h:44
static const char * i386_register_names[]
Definition: i386-tdep.c:71
#define MPX_BD_MASK
Definition: i386-tdep.c:8655
int sc_sp_offset
Definition: i386-tdep.h:221
#define min(a, b)
Definition: defs.h:106
void ax_simple(struct agent_expr *x, enum agent_op op)
Definition: ax-general.c:140
#define HIGH_RETURN_REGNUM
Definition: i386-tdep.c:2745
static int startswith(const char *string, const char *pattern)
Definition: common-utils.h:75
enum register_status regcache_raw_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition: regcache.c:690
void _initialize_i386_tdep(void)
Definition: i386-tdep.c:8878
const char ** zmmh_register_names
Definition: i386-tdep.h:184
#define LOW_RETURN_REGNUM
Definition: i386-tdep.c:2744
static const char * struct_convention
Definition: i386-tdep.c:2875
static int i386_sigtramp_frame_sniffer(const struct frame_unwind *self, struct frame_info *this_frame, void **this_prologue_cache)
Definition: i386-tdep.c:2489
static void i386_mpx_info_bounds(char *args, int from_tty)
Definition: i386-tdep.c:8767
static int i386_mpx_enabled(void)
Definition: i386-tdep.c:8647
int num_byte_regs
Definition: i386-tdep.h:100
char * xstrprintf(const char *format,...)
Definition: common-utils.c:107
#define I387_YMM16H_REGNUM(tdep)
Definition: i387-tdep.h:52
struct gdbarch * gdbarch
Definition: gdbarch.h:1542
static int i386_stack_tramp_frame_sniffer(const struct frame_unwind *self, struct frame_info *this_frame, void **this_cache)
Definition: i386-tdep.c:2360
int regnum
Definition: aarch64-tdep.c:69
#define I387_XMM16_REGNUM(tdep)
Definition: i387-tdep.h:63
void printf_unfiltered(const char *format,...)
Definition: utils.c:2399
void read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition: corefile.c:244
static enum unwind_stop_reason i386_sigtramp_frame_unwind_stop_reason(struct frame_info *this_frame, void **this_cache)
Definition: i386-tdep.c:2450
void( iterate_over_regset_sections_cb)(const char *sect_name, int size, const struct regset *regset, const char *human_name, void *cb_data)
Definition: gdbarch.h:98
void set_gdbarch_insn_is_jump(struct gdbarch *gdbarch, gdbarch_insn_is_jump_ftype insn_is_jump)
Definition: gdbarch.c:4624
int i386_word_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:187
int user_reg_map_name_to_regnum(struct gdbarch *gdbarch, const char *name, int len)
Definition: user-regs.c:129
static int i386_call_p(const gdb_byte *insn)
Definition: i386-tdep.c:700
struct reggroup *const vector_reggroup
Definition: reggroups.c:295
static const char * i386_ymm_names[]
Definition: i386-tdep.c:104
ULONGEST get_frame_register_unsigned(struct frame_info *frame, int regnum)
Definition: frame.c:1194
static int i386_stap_parse_special_token_triplet(struct gdbarch *gdbarch, struct stap_parse_info *p)
Definition: i386-tdep.c:3968
void * xmalloc(YYSIZE_T)
int i387_convert_register_p(struct gdbarch *gdbarch, int regnum, struct type *type)
Definition: i387-tdep.c:338
struct ui_file * gdb_stdlog
Definition: main.c:73
int record_full_memory_query
Definition: record-full.c:159
void set_gdbarch_frame_args_skip(struct gdbarch *gdbarch, CORE_ADDR frame_args_skip)
Definition: gdbarch.c:2839
const char ** xmm_avx512_register_names
Definition: i386-tdep.h:187
#define MPX_BASE_MASK
Definition: i386-tdep.c:8620
void cmd_show_list(struct cmd_list_element *list, int from_tty, const char *prefix)
Definition: cli-setshow.c:672
static int i386_get_longjmp_target(struct frame_info *frame, CORE_ADDR *pc)
Definition: i386-tdep.c:2573
LONGEST read_code_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition: corefile.c:331
Definition: regdef.h:22
static void i386_epilogue_frame_this_id(struct frame_info *this_frame, void **this_cache, struct frame_id *this_id)
Definition: i386-tdep.c:2266
void put_frame_register(struct frame_info *frame, int regnum, const gdb_byte *buf)
Definition: frame.c:1220
int record_full_arch_list_add_mem(CORE_ADDR addr, int len)
Definition: record-full.c:489
static const struct frame_unwind i386_frame_unwind
Definition: i386-tdep.c:2167
const struct target_desc * target_desc
Definition: gdbarch.h:1566
static gdb_byte * i386_skip_prefixes(gdb_byte *insn, size_t max_len)
Definition: i386-tdep.c:595
Definition: value.c:172
int * gregset_reg_offset
Definition: i386-tdep.h:59
struct value * parse_to_comma_and_eval(const char **expp)
Definition: eval.c:141
#define I387_SIZEOF_FXSAVE
Definition: i387-tdep.h:112
static CORE_ADDR i386_svr4_sigcontext_addr(struct frame_info *this_frame)
Definition: i386-tdep.c:3932
void set_gdbarch_push_dummy_code(struct gdbarch *gdbarch, gdbarch_push_dummy_code_ftype push_dummy_code)
Definition: gdbarch.c:2257
#define I387_MM0_REGNUM(tdep)
Definition: i387-tdep.h:35
static struct value * i386_pseudo_register_read_value(struct gdbarch *gdbarch, struct regcache *regcache, int regnum)
Definition: i386-tdep.c:3432
void write_exp_elt_opcode(struct parser_state *ps, enum exp_opcode expelt)
Definition: parse.c:236
size_t len
Definition: i386-tdep.c:1364
void regcache_raw_write_part(struct regcache *regcache, int regnum, int offset, int len, const gdb_byte *buf)
Definition: regcache.c:1006
#define X86_XSTATE_X87_MASK
Definition: x86-xstate.h:39
static void i386_frame_this_id(struct frame_info *this_frame, void **this_cache, struct frame_id *this_id)
Definition: i386-tdep.c:2073
const char * i386_pseudo_register_name(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:439
static int i386_reg_struct_return_p(struct gdbarch *gdbarch, struct type *type)
Definition: i386-tdep.c:2882
static void append_insns(CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
Definition: i386-tdep.c:944
struct regcache * regcache
Definition: i386-tdep.c:4583
static int i386_ymmh_avx512_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:280
void throw_exception(struct gdb_exception exception)
void tdesc_use_registers(struct gdbarch *gdbarch, const struct target_desc *target_desc, struct tdesc_arch_data *early_data)
int st0_regnum
Definition: i386-tdep.h:69
int core_addr_lessthan(CORE_ADDR lhs, CORE_ADDR rhs)
Definition: arch-utils.c:138
bfd_byte gdb_byte
Definition: common-types.h:38
#define MPX_BT_MASK_32
Definition: i386-tdep.c:8658
#define I386_SAVE_FPU_REGS
Definition: i386-tdep.c:4876
unsigned length
Definition: gdbtypes.h:807
static int i386_mmx_regnum_to_fp_regnum(struct regcache *regcache, int regnum)
Definition: i386-tdep.c:3218
static enum gdb_osabi i386_coff_osabi_sniffer(bfd *abfd)
Definition: i386-tdep.c:8591
static struct type * i386_zmm_type(struct gdbarch *gdbarch)
Definition: i386-tdep.c:3038
void append_composite_type_field(struct type *t, char *name, struct type *field)
Definition: gdbtypes.c:4757
int ymm16h_regnum
Definition: i386-tdep.h:156
void help_list(struct cmd_list_element *list, const char *cmdtype, enum command_class theclass, struct ui_file *stream)
Definition: cli-decode.c:1023
const struct floatformat * floatformats_i387_ext[BFD_ENDIAN_UNKNOWN]
Definition: gdbtypes.c:82
int(* sigtramp_p)(struct frame_info *)
Definition: i386-tdep.h:209
ULONGEST align_up(ULONGEST v, int n)
Definition: utils.c:2963
gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]
Definition: i386-tdep.c:1365
#define X86_XSTATE_AVX512_MASK
Definition: x86-xstate.h:43
#define TYPE_TARGET_TYPE(thistype)
Definition: gdbtypes.h:1229
struct type * i386_ymm_type
Definition: i386-tdep.h:225
struct type * builtin_double
Definition: gdbtypes.h:1491
struct bound_minimal_symbol lookup_minimal_symbol_by_pc(CORE_ADDR pc)
Definition: minsyms.c:801
#define max(a, b)
Definition: defs.h:109
uint64_t xcr0
Definition: i386-tdep.h:139
static void i386_collect_gregset(const struct regset *regset, const struct regcache *regcache, int regnum, void *gregs, size_t len)
Definition: i386-tdep.c:3754
void set_gdbarch_convert_register_p(struct gdbarch *gdbarch, gdbarch_convert_register_p_ftype convert_register_p)
Definition: gdbarch.c:2423
static void set_mpx_cmd(char *args, int from_tty)
Definition: i386-tdep.c:8861
CORE_ADDR orig_addr
Definition: i386-tdep.c:4584
int deprecated_frame_register_read(struct frame_info *frame, int regnum, gdb_byte *myaddr)
Definition: frame.c:1258
static struct value * i386_sigtramp_frame_prev_register(struct frame_info *this_frame, void **this_cache, int regnum)
Definition: i386-tdep.c:2479
struct gdbarch * gdbarch
Definition: i386-tdep.c:4582
int frame_relative_level(struct frame_info *fi)
Definition: frame.c:2454
static void check(BOOL ok, const char *file, int line)
Definition: windows-nat.c:284
CORE_ADDR parse_and_eval_address(const char *exp)
Definition: eval.c:96
#define TYPE_CODE(thistype)
Definition: gdbtypes.h:1240
static void i386_collect_fpregset(const struct regset *regset, const struct regcache *regcache, int regnum, void *fpregs, size_t len)
Definition: i386-tdep.c:3800
enum register_status regcache_raw_read(struct regcache *regcache, int regnum, gdb_byte *buf)
Definition: regcache.c:637
struct type * i386_mmx_type
Definition: i386-tdep.h:224
const int * record_regmap
Definition: i386-tdep.h:233
struct value * frame_unwind_got_register(struct frame_info *frame, int regnum, int new_regnum)
Definition: frame-unwind.c:218
void regcache_cooked_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
Definition: regcache.c:871
static CORE_ADDR i386_mpx_get_bt_entry(CORE_ADDR ptr, CORE_ADDR bd_base)
Definition: i386-tdep.c:8664
void set_gdbarch_fast_tracepoint_valid_at(struct gdbarch *gdbarch, gdbarch_fast_tracepoint_valid_at_ftype fast_tracepoint_valid_at)
Definition: gdbarch.c:4407
int target_read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition: target.c:1393
static struct cmd_list_element * mpx_show_cmdlist
Definition: i386-tdep.c:8856
int num_xmm_regs
Definition: i386-tdep.h:122
static int i386_insn_is_ret(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: i386-tdep.c:748
struct type * builtin_data_ptr
Definition: gdbtypes.h:1533
struct minimal_symbol * minsym
Definition: minsyms.h:32
int i386_stap_is_single_operand(struct gdbarch *gdbarch, const char *s)
Definition: i386-tdep.c:3951
void set_gdbarch_stap_is_single_operand(struct gdbarch *gdbarch, gdbarch_stap_is_single_operand_ftype stap_is_single_operand)
Definition: gdbarch.c:4219
static CORE_ADDR i386_analyze_frame_setup(struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR limit, struct i386_frame_cache *cache)
Definition: i386-tdep.c:1567
static void i386_supply_fpregset(const struct regset *regset, struct regcache *regcache, int regnum, const void *fpregs, size_t len)
Definition: i386-tdep.c:3778
static int i386_validate_tdesc_p(struct gdbarch_tdep *tdep, struct tdesc_arch_data *tdesc_data)
Definition: i386-tdep.c:8103
void i386_elf_init_abi(struct gdbarch_info info, struct gdbarch *gdbarch)
Definition: i386-tdep.c:4332
int offset
Definition: agent.c:65
static int i386_match_insn_block(CORE_ADDR pc, struct i386_insn *insn_patterns)
Definition: i386-tdep.c:1423
void regcache_raw_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
Definition: regcache.c:723
int code
Definition: ser-unix.c:684
#define I387_BNDCFGU_REGNUM(tdep)
Definition: i387-tdep.h:40
void set_gdbarch_print_float_info(struct gdbarch *gdbarch, gdbarch_print_float_info_ftype print_float_info)
Definition: gdbarch.c:2291
static const char * i386_mpx_names[]
Definition: i386-tdep.c:116
void get_frame_register(struct frame_info *frame, int regnum, gdb_byte *buf)
Definition: frame.c:1085
#define TYPE_NFIELDS(thistype)
Definition: gdbtypes.h:1241
void set_gdbarch_num_pseudo_regs(struct gdbarch *gdbarch, int num_pseudo_regs)
Definition: gdbarch.c:1926
static int i386_next_regnum(int regnum)
Definition: i386-tdep.c:3600
#define I386_SAVE_FPU_ENV
Definition: i386-tdep.c:4877
void dwarf2_append_unwinders(struct gdbarch *gdbarch)
size_t sizeof_gregset
Definition: i386-tdep.h:61
static struct frame_id i386_dummy_id(struct gdbarch *gdbarch, struct frame_info *this_frame)
Definition: i386-tdep.c:2546
void set_gdbarch_fetch_pointer_argument(struct gdbarch *gdbarch, gdbarch_fetch_pointer_argument_ftype fetch_pointer_argument)
Definition: gdbarch.c:3374
int eax_regnum
Definition: i386-tdep.h:116
#define PREFIX_REPNZ
Definition: i386-tdep.c:4552
#define I387_SIZEOF_FSAVE
Definition: i387-tdep.h:111
struct m32c_reg regs[M32C_MAX_NUM_REGS]
Definition: m32c-tdep.c:105
static CORE_ADDR i386_frame_base_address(struct frame_info *this_frame, void **this_cache)
Definition: i386-tdep.c:2530
#define I387_MXCSR_REGNUM(tdep)
Definition: i387-tdep.h:64
static const gdb_byte * i386_breakpoint_from_pc(struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
Definition: i386-tdep.c:578
#define I386_MAX_REGISTER_SIZE
Definition: i386-tdep.h:329
static enum return_value_convention i386_return_value(struct gdbarch *gdbarch, struct value *function, struct type *type, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf)
Definition: i386-tdep.c:2916
const struct target_desc * tdesc
Definition: i386-tdep.h:193
int i386_ymm_avx512_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:293
void ax_const_l(struct agent_expr *x, LONGEST l)
Definition: ax-general.c:245
const struct regset * fpregset
Definition: i386-tdep.h:242
struct tdesc_arch_data * tdesc_data_alloc(void)
void regcache_raw_supply(struct regcache *regcache, int regnum, const void *buf)
Definition: regcache.c:1041
int get_frame_register_bytes(struct frame_info *frame, int regnum, CORE_ADDR offset, int len, gdb_byte *myaddr, int *optimizedp, int *unavailablep)
Definition: frame.c:1274
static struct value * i386_epilogue_frame_prev_register(struct frame_info *this_frame, void **this_cache, int regnum)
Definition: i386-tdep.c:2280
void set_gdbarch_call_dummy_location(struct gdbarch *gdbarch, int call_dummy_location)
Definition: gdbarch.c:2233
void i387_print_float_info(struct gdbarch *gdbarch, struct ui_file *file, struct frame_info *frame, const char *args)
Definition: i387-tdep.c:215
static CORE_ADDR i386_fetch_pointer_argument(struct frame_info *frame, int argi, struct type *type)
Definition: i386-tdep.c:4542
void ui_out_field_core_addr(struct ui_out *uiout, const char *fldname, struct gdbarch *gdbarch, CORE_ADDR address)
Definition: ui-out.c:499
int * sc_reg_offset
Definition: i386-tdep.h:215
unsigned long long ULONGEST
Definition: common-types.h:53
static CORE_ADDR i386_analyze_register_saves(CORE_ADDR pc, CORE_ADDR current_pc, struct i386_frame_cache *cache)
Definition: i386-tdep.c:1730
int i387_register_to_value(struct frame_info *frame, int regnum, struct type *type, gdb_byte *to, int *optimizedp, int *unavailablep)
Definition: i387-tdep.c:358
const struct tdesc_feature * tdesc_find_feature(const struct target_desc *target_desc, const char *name)
int register_size(struct gdbarch *gdbarch, int regnum)
Definition: regcache.c:169
void set_gdbarch_long_double_bit(struct gdbarch *gdbarch, int long_double_bit)
Definition: gdbarch.c:1667
static void i386_frame_cache_1(struct frame_info *this_frame, struct i386_frame_cache *cache)
Definition: i386-tdep.c:1947
struct type * value_type(const struct value *value)
Definition: value.c:1021
struct type * builtin_int64
Definition: gdbtypes.h:1520
static int i386_register_to_value(struct frame_info *frame, int regnum, struct type *type, gdb_byte *to, int *optimizedp, int *unavailablep)
Definition: i386-tdep.c:3660
#define I387_NUM_XMM_AVX512_REGS(tdep)
Definition: i387-tdep.h:34
void set_gdbarch_return_value(struct gdbarch *gdbarch, gdbarch_return_value_ftype return_value)
Definition: gdbarch.c:2556
void regcache_raw_collect(const struct regcache *regcache, int regnum, void *buf)
Definition: regcache.c:1071
int gdbarch_pc_regnum(struct gdbarch *gdbarch)
Definition: gdbarch.c:1998
CORE_ADDR value_as_address(struct value *val)
Definition: value.c:2679
static int i386_record_floats(struct gdbarch *gdbarch, struct i386_record_s *ir, uint32_t iregnum)
Definition: i386-tdep.c:4884
void set_gdbarch_long_double_format(struct gdbarch *gdbarch, const struct floatformat **long_double_format)
Definition: gdbarch.c:1683
const int * regmap
Definition: i386-tdep.c:4596
gdb_byte * value_contents_raw(struct value *value)
Definition: value.c:1084
int default_register_reggroup_p(struct gdbarch *gdbarch, int regnum, struct reggroup *group)
Definition: reggroups.c:184
struct reggroup *const save_reggroup
Definition: reggroups.c:297
#define I387_FCTRL_REGNUM(tdep)
Definition: i387-tdep.h:54
static void i386_gen_return_address(struct gdbarch *gdbarch, struct agent_expr *ax, struct axs_value *value, CORE_ADDR scope)
Definition: i386-tdep.c:2383
#define TYPE_LENGTH(thistype)
Definition: gdbtypes.h:1237
int int * to
Definition: varobj.h:282
static int i386_insn_is_call(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition: i386-tdep.c:735
int mm0_regnum
Definition: i386-tdep.h:76
void set_gdbarch_push_dummy_call(struct gdbarch *gdbarch, gdbarch_push_dummy_call_ftype push_dummy_call)
Definition: gdbarch.c:2216
static int i386_in_stack_tramp_p(CORE_ADDR pc)
Definition: i386-tdep.c:2336
#define COMPUNIT_EPILOGUE_UNWIND_VALID(cust)
Definition: symtab.h:1102
struct target_desc * tdesc_i386_mpx
Definition: i386-mpx.c:8
static struct gdbarch * i386_gdbarch_init(struct gdbarch_info info, struct gdbarch_list *arches)
Definition: i386-tdep.c:8244
ULONGEST read_memory_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition: corefile.c:321
void set_gdbarch_insn_is_call(struct gdbarch *gdbarch, gdbarch_insn_is_call_ftype insn_is_call)
Definition: gdbarch.c:4590
struct ui_out * current_uiout
Definition: ui-out.c:233
CORE_ADDR read_memory_typed_address(CORE_ADDR addr, struct type *type)
Definition: corefile.c:378
void set_gdbarch_iterate_over_regset_sections(struct gdbarch *gdbarch, gdbarch_iterate_over_regset_sections_ftype iterate_over_regset_sections)
Definition: gdbarch.c:3398
static int i386_mxcsr_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:351
void register_gdbarch_init(enum bfd_architecture bfd_architecture, gdbarch_init_ftype *init)
Definition: gdbarch.c:4975
static CORE_ADDR i386_frame_align(struct gdbarch *gdbarch, CORE_ADDR sp)
Definition: i386-tdep.c:2560
LONGEST extract_signed_integer(const gdb_byte *, int, enum bfd_endian)
Definition: findvar.c:49
void write_memory(CORE_ADDR memaddr, const bfd_byte *myaddr, ssize_t len)
Definition: corefile.c:389
void set_gdbarch_skip_prologue(struct gdbarch *gdbarch, gdbarch_skip_prologue_ftype skip_prologue)
Definition: gdbarch.c:2590
const char ** k_register_names
Definition: i386-tdep.h:181
int k0_regnum
Definition: i386-tdep.h:90
struct type * builtin_int8
Definition: gdbtypes.h:1514
void i386_pseudo_register_read_into_value(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, struct value *result_value)
Definition: i386-tdep.c:3238
void set_gdbarch_has_dos_based_file_system(struct gdbarch *gdbarch, int has_dos_based_file_system)
Definition: gdbarch.c:4474
static struct gdbarch_data * tdesc_data
static void initialize_tdesc_i386_mpx(void)
Definition: i386-mpx.c:10
const int num_lower_zmm_regs
Definition: i386-tdep.c:156
#define I387_NUM_REGS
Definition: i387-tdep.h:30
CORE_ADDR saved_sp
Definition: i386-tdep.c:1052
enum axs_lvalue_kind kind
Definition: ax-gdb.h:77
int gregset_num_regs
Definition: i386-tdep.h:60
enum bfd_endian byte_order
Definition: gdbarch.c:128
void i386_iterate_over_regset_sections(struct gdbarch *gdbarch, iterate_over_regset_sections_cb *cb, void *cb_data, const struct regcache *regcache)
Definition: i386-tdep.c:3832
void set_gdbarch_pc_regnum(struct gdbarch *gdbarch, int pc_regnum)
Definition: gdbarch.c:2008
void set_gdbarch_max_insn_length(struct gdbarch *gdbarch, ULONGEST max_insn_length)
Definition: gdbarch.c:3643
void write_exp_string(struct parser_state *ps, struct stoken str)
Definition: parse.c:349
static const char * i386_byte_names[]
Definition: i386-tdep.c:138
int record_full_arch_list_add_end(void)
Definition: record-full.c:520
int tdesc_has_registers(const struct target_desc *target_desc)
static enum unwind_stop_reason i386_epilogue_frame_unwind_stop_reason(struct frame_info *this_frame, void **this_cache)
Definition: i386-tdep.c:2253
void write_exp_elt_type(struct parser_state *ps, struct type *expelt)
Definition: parse.c:308
void set_gdbarch_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype register_name)
Definition: gdbarch.c:2127
CORE_ADDR get_frame_func(struct frame_info *this_frame)
Definition: frame.c:920
void gdbarch_register_osabi(enum bfd_architecture arch, unsigned long machine, enum gdb_osabi osabi, void(*init_osabi)(struct gdbarch_info, struct gdbarch *))
Definition: osabi.c:148
int bnd0r_regnum
Definition: i386-tdep.h:163
static CORE_ADDR i386_skip_probe(CORE_ADDR pc)
Definition: i386-tdep.c:1201
void error(const char *fmt,...)
Definition: errors.c:38
size_t size
Definition: go32-nat.c:242
struct gdbarch * gdbarch_alloc(const struct gdbarch_info *info, struct gdbarch_tdep *tdep)
Definition: gdbarch.c:339
void set_gdbarch_inner_than(struct gdbarch *gdbarch, gdbarch_inner_than_ftype inner_than)
Definition: gdbarch.c:2655
struct type * lookup_pointer_type(struct type *type)
Definition: gdbtypes.c:368
int i386_bnd_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition: i386-tdep.c:308
int bnd0_regnum
Definition: i386-tdep.h:167
CORE_ADDR i386_pe_skip_trampoline_code(struct frame_info *frame, CORE_ADDR pc, char *name)
Definition: i386-tdep.c:3848
struct gdbarch * get_frame_arch(struct frame_info *this_frame)
Definition: frame.c:2535
static void i386_mpx_set_bounds(char *args, int from_tty)
Definition: i386-tdep.c:8808
const struct target_desc * i386_target_description(uint64_t xcr0)
Definition: i386-tdep.c:8604
long long LONGEST
Definition: common-types.h:52
int gdb_buffered_insn_length(struct gdbarch *gdbarch, const gdb_byte *insn, int max_len, CORE_ADDR addr)
Definition: disasm.c:525
static int i386_record_lea_modrm_addr(struct i386_record_s *irp, uint64_t *addr)
Definition: i386-tdep.c:4622
#define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum)
Definition: i386-tdep.c:4946
static const char intel_flavor[]
Definition: i386-tdep.c:556
void i386_pseudo_register_write(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buf)
Definition: i386-tdep.c:3448
gdb_osabi
Definition: defs.h:540
void regcache_cooked_write(struct regcache *regcache, int regnum, const gdb_byte *buf)
Definition: regcache.c:930
int zmm0h_regnum
Definition: i386-tdep.h:178
#define I387_NUM_K_REGS
Definition: i387-tdep.h:46
uint8_t reg
Definition: i386-tdep.c:4590
int num_dword_regs
Definition: i386-tdep.h:112
int length
Definition: parser-defs.h:81
void set_gdbarch_print_insn(struct gdbarch *gdbarch, gdbarch_print_insn_ftype print_insn)
Definition: gdbarch.c:3067
static int i386_record_push(struct i386_record_s *irp, int size)
Definition: i386-tdep.c:4858
static CORE_ADDR i386_analyze_stack_align(CORE_ADDR pc, CORE_ADDR current_pc, struct i386_frame_cache *cache)
Definition: i386-tdep.c:1248
struct type * builtin_float
Definition: gdbtypes.h:1490
static struct type * i386_mmx_type(struct gdbarch *gdbarch)
Definition: i386-tdep.c:3142
static const int i386_record_regmap[]
Definition: i386-tdep.c:8028
void regcache_raw_write(struct regcache *regcache, int regnum, const gdb_byte *buf)
Definition: regcache.c:885
const ULONGEST const LONGEST len
Definition: target.h:309
uint8_t rm
Definition: i386-tdep.c:4590
#define X86_XSTATE_ALL_MASK
Definition: x86-xstate.h:46
int bndcfgu_regnum
Definition: i386-tdep.h:171