31 #include "floatformat.h"
51 #include "xtensa-isa.h"
53 #include "xtensa-config.h"
58 #define DEBUGWARN(args...) \
59 if (xtensa_debug_level > 0) \
60 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
62 #define DEBUGINFO(args...) \
63 if (xtensa_debug_level > 1) \
64 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
66 #define DEBUGTRACE(args...) \
67 if (xtensa_debug_level > 2) \
68 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
70 #define DEBUGVERB(args...) \
71 if (xtensa_debug_level > 3) \
72 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
76 #define SP_ALIGNMENT 16
81 #define ARGS_NUM_REGS 6
82 #define REGISTER_SIZE 4
86 #define PS_CALLINC_SHIFT 16
87 #define PS_CALLINC_MASK 0x00030000
88 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
89 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
97 #define ARG_NOF(gdbarch) \
98 (gdbarch_tdep (gdbarch)->call_abi \
99 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
100 #define ARG_1ST(gdbarch) \
101 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
102 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
103 : (gdbarch_tdep (gdbarch)->a0_base + 6))
108 #define XTENSA_IS_ENTRY(gdbarch, op1) \
109 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
110 ? ((op1) == 0x6c) : ((op1) == 0x36))
112 #define XTENSA_ENTRY_LENGTH 3
118 #define PS_WOE (1<<18)
119 #define PS_EXC (1<<4)
139 arreg = a_regnum - tdep->
a0_base;
149 areg_number (
struct gdbarch *gdbarch,
int ar_regnum,
unsigned int wb)
154 areg = ar_regnum - tdep->
ar_base;
157 areg = (areg - wb * 4) & (tdep->
num_aregs - 1);
158 return (areg > 15) ? -1 : areg;
168 return (
unsigned long) value;
197 DEBUGTRACE (
"extract_call_winsize (pc = 0x%08x)\n", (
int) pc);
211 if (byte_order == BFD_ENDIAN_LITTLE)
213 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
214 winsize = (insn & 0x30) >> 2;
218 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
219 winsize = (insn >> 16) & 0xc;
267 && regnum < tdep->
a0_base + 16))
271 || regnum == tdep->
a0_base + 1)
313 if (tp->
size == size)
334 internal_error (__FILE__, __LINE__,
_(
"invalid register number %d"), regnum);
348 if (regnum >= 0 && regnum < 16)
358 _(
"invalid dwarf/stabs register number %d"), regnum);
378 unsigned int *ptr =
value;
379 unsigned int regval,
m, mem = 0;
382 int bitsize = bytesize * 8;
385 DEBUGTRACE (
"xtensa_register_write_masked ()\n");
389 for (i = 0; i < bytesize; i++)
392 mem |= (buffer[bytesize - i - 1] << 24);
397 for (i = 0; i < bytesize; i++)
400 mem |= (buffer[i] << 24);
409 *ptr = mem >> (((0 - bytesize) & 3) * 8);
414 for (i = 0; i < mask->count; i++)
416 start = mask->mask[i].bit_start;
417 size = mask->mask[i].bit_size;
418 regval = mem >> shift;
420 if ((shift += size) > bitsize)
421 error (
_(
"size of all masks is larger than the register"));
430 regval |= mem << (size - shift);
434 r = mask->mask[i].reg_num;
435 if (r >= 0 && size > 0)
440 m = 0xffffffff >> (32 -
size) << start;
442 regval = (regval &
m) | (old_val & ~m);
462 unsigned int *ptr =
value;
463 unsigned int regval, mem = 0;
466 int bitsize = bytesize * 8;
469 DEBUGTRACE (
"xtensa_register_read_masked (reg \"%s\", ...)\n",
473 for (i = 0; i < mask->count; i++)
475 int r = mask->mask[i].reg_num;
484 regval = (
unsigned int) val;
489 start = mask->mask[i].bit_start;
490 size = mask->mask[i].bit_size;
495 regval &= (0xffffffff >> (32 -
size));
497 mem |= regval << shift;
499 if ((shift += size) > bitsize)
500 error (
_(
"size of all masks is larger than the register"));
511 mem = regval >> (size - shift);
523 for (i = 0; i < bytesize; i++)
527 buffer[bytesize - i - 1] = mem & 0xff;
531 for (i = 0; i < bytesize; i++)
535 buffer[i] = mem & 0xff;
553 DEBUGTRACE (
"xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
602 warning (
_(
"cannot read register %s"),
614 warning (
_(
"cannot read register"));
621 warning (
_(
"cannot read register"));
635 _(
"invalid register number %d"), regnum);
649 DEBUGTRACE (
"xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
692 warning (
_(
"cannot write register %s"),
704 warning (
_(
"cannot write register"));
712 warning (
_(
"cannot write register"));
729 _(
"invalid register number %d"), regnum);
741 char cpname[] =
"cp0";
783 if (group == xtensa_cp[i])
789 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
790 | XTENSA_REGISTER_FLAGS_WRITABLE \
791 | XTENSA_REGISTER_FLAGS_VOLATILE)
793 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
794 | XTENSA_REGISTER_FLAGS_WRITABLE)
818 if (group == xtensa_ar_reggroup)
820 if (group == xtensa_user_reggroup)
856 DEBUGTRACE (
"xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum);
862 if (regnum ==
gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1)
865 if (regnum ==
gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1)
868 if (regnum ==
gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1)
870 (
char *) ®s->
lbeg);
871 if (regnum ==
gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1)
873 (
char *) ®s->
lend);
874 if (regnum ==
gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1)
877 if (regnum ==
gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1)
879 (
char *) ®s->
sar);
885 (gdbarch)->ar_base]);
886 else if (regnum == -1)
890 (
char *) ®s->
ar[i]);
913 DEBUGTRACE (
"xtensa_iterate_over_regset_sections\n");
923 #define XTENSA_NUM_SAVED_AREGS 12
1015 DEBUGTRACE (
"xtensa_alloc_frame_cache ()\n");
1024 cache->
call0 = !windowed;
1058 return address & ~15;
1068 DEBUGTRACE (
"xtensa_unwind_pc (next_frame = %s)\n",
1074 DEBUGINFO (
"[xtensa_unwind_pc] pc = 0x%08x\n", (
unsigned int) pc);
1105 if (byte_order == BFD_ENDIAN_BIG)
1108 code = insn & 0xf000ff00;
1109 if ((code == 0x00009000) || (code == 0x00009400))
1112 code = insn & 0xffffff00;
1113 return ((code == 0x00430000) || (code == 0x00530000));
1118 code = insn & 0x00ff000f;
1119 if ((code == 0x090000) || (code == 0x490000))
1122 code = insn & 0x00ffffff;
1123 return ((code == 0x00003400) || (code == 0x00003500));
1130 #define XTENSA_ISA_BSZ 32
1131 #define XTENSA_ISA_BADPC ((CORE_ADDR)0)
1136 #define RETURN_FP goto done
1141 xtensa_insnbuf ins, slot;
1145 int ilen, islots, is;
1147 const char *opcname;
1150 if (start_addr == 0)
1157 ins = xtensa_insnbuf_alloc (isa);
1158 slot = xtensa_insnbuf_alloc (isa);
1161 for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen)
1163 if (ia + xtensa_isa_maxlength (isa) > bt)
1172 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
1173 ifmt = xtensa_format_decode (isa, ins);
1174 if (ifmt == XTENSA_UNDEFINED)
1176 ilen = xtensa_format_length (isa, ifmt);
1177 if (ilen == XTENSA_UNDEFINED)
1179 islots = xtensa_format_num_slots (isa, ifmt);
1180 if (islots == XTENSA_UNDEFINED)
1183 for (is = 0; is < islots; ++is)
1185 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
1188 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
1189 if (opc == XTENSA_UNDEFINED)
1192 opcname = xtensa_opcode_name (isa, opc);
1194 if (strcasecmp (opcname,
"mov.n") == 0
1195 || strcasecmp (opcname,
"or") == 0)
1197 unsigned int register_operand;
1202 if (xtensa_operand_get_field (isa, opc, 1, ifmt,
1203 is, slot, ®ister_operand) != 0)
1205 if (xtensa_operand_decode (isa, opc, 1, ®ister_operand) != 0)
1207 if (register_operand == 1)
1209 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot,
1210 ®ister_operand) != 0)
1212 if (xtensa_operand_decode (isa, opc, 0,
1213 ®ister_operand) != 0)
1225 || strcasecmp (opcname,
"ill") == 0
1226 || strcasecmp (opcname,
"ill.n") == 0
1228 || strcasecmp (opcname,
"break") == 0
1229 || strcasecmp (opcname,
"break.n") == 0
1231 || xtensa_opcode_is_branch (isa, opc) > 0
1232 || xtensa_opcode_is_jump (isa, opc) > 0
1233 || xtensa_opcode_is_loop (isa, opc) > 0
1234 || xtensa_opcode_is_call (isa, opc) > 0
1235 || strcasecmp (opcname,
"simcall") == 0
1236 || strcasecmp (opcname,
"syscall") == 0)
1242 xtensa_insnbuf_free(isa, slot);
1243 xtensa_insnbuf_free(isa, ins);
1277 ps = (ps_regnum >= 0
1284 *this_cache = cache;
1301 (this_frame,
gdbarch_tdep (gdbarch)->a0_base + callinc * 4);
1317 cache->
ra = (cache->
pc & 0xc0000000) | (ra & 0x3fffffff);
1331 cache->
wd.
ws = ws & ~(1 << wb);
1334 cache->
ra = (pc & 0xc0000000) | (ra & 0x3fffffff);
1339 if (cache->
wd.
ws == 0)
1345 (this_frame,
gdbarch_tdep (gdbarch)->a0_base + 1) - 16;
1347 for (i = 0; i < 4; i++, sp += 4)
1361 for ( i = 4; i < cache->
wd.
callsize; i++, sp += 4)
1368 if ((cache->
prev_sp == 0) && ( ra != 0 ))
1372 if ((cache->
wd.
ws & (1 << cache->
wd.
wb)) == 0)
1420 \nUnrecognised function prologue. Stack trace cannot be resolved. \
1421 This message will not be repeated in this session.\n"));
1441 static struct value *
1451 if (*this_cache == NULL)
1453 cache = *this_cache;
1456 saved_reg = cache->
ra;
1457 else if (regnum ==
gdbarch_tdep (gdbarch)->a0_base + 1)
1459 else if (!cache->
call0)
1462 saved_reg = cache->
wd.
ws;
1464 saved_reg = cache->
wd.
wb;
1466 saved_reg = cache->
ps;
1493 && cache->
wd.
aregs[areg] != -1)
1557 xtensa_frame_base_address
1567 bfd_byte *valbuf = dst;
1573 DEBUGTRACE (
"xtensa_extract_return_value (...)\n");
1584 if (len > (callsize > 8 ? 8 : 16))
1586 _(
"cannot extract return value of %d bytes long"),
1602 DEBUGINFO (
"[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1607 for (; len > 0; len -= 4, areg++, valbuf += 4)
1623 const bfd_byte *valbuf = dst;
1630 DEBUGTRACE (
"xtensa_store_return_value (...)\n");
1639 if (len > (callsize > 8 ? 8 : 16))
1641 _(
"unimplemented for this length: %d"),
1646 DEBUGTRACE (
"[xtensa_store_return_value] callsize %d wb %d\n",
1647 callsize, (
int) wb);
1657 for (; len > 0; len -= 4, areg++, valbuf += 4)
1669 struct value *
function,
1670 struct type *valtype,
1687 if (writebuf != NULL)
1692 if (readbuf != NULL)
1705 struct value *
function,
1709 struct value **args,
1716 int size, onstack_size;
1719 struct argument_info
1721 const bfd_byte *contents;
1732 struct argument_info *arg_info =
1733 (
struct argument_info *) alloca (nargs *
sizeof (
struct argument_info));
1737 DEBUGTRACE (
"xtensa_push_dummy_call (...)\n");
1742 DEBUGINFO (
"[xtensa_push_dummy_call] nargs = %d\n", nargs);
1743 DEBUGINFO (
"[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1744 "struct_addr=0x%x\n",
1745 (
int) sp, (
int) struct_return, (
int) struct_addr);
1747 for (i = 0; i < nargs; i++)
1749 struct value *arg = args[i];
1783 for (i = 0; i < nargs; i++)
1785 struct argument_info *info = &arg_info[i];
1786 struct value *arg = args[i];
1827 size = (size + info->align - 1) & ~(info->align - 1);
1828 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1833 info->u.offset = onstack_size;
1834 onstack_size += info->length;
1841 size += info->length;
1863 for (i = 0; i < nargs; i++)
1865 struct argument_info *info = &arg_info[i];
1869 int n = info->length;
1885 int n = info->length;
1886 const bfd_byte *cp = info->contents;
1887 int r = info->u.regno;
1928 ra = (bp_addr & 0x3fffffff) | 0x40000000;
1930 ps = (
unsigned long) val & ~0x00030000;
1966 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1967 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1968 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1969 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1971 static const unsigned char *
1980 DEBUGTRACE (
"xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (
int) *pcptr);
1982 if (
gdbarch_tdep (gdbarch)->isa_use_density_instructions)
1986 *lenptr =
sizeof (density_big_breakpoint);
1987 return density_big_breakpoint;
1991 *lenptr =
sizeof (density_little_breakpoint);
1992 return density_little_breakpoint;
1999 *lenptr =
sizeof (big_breakpoint);
2000 return big_breakpoint;
2004 *lenptr =
sizeof (little_breakpoint);
2005 return little_breakpoint;
2017 #define RETURN_RET goto done
2019 xtensa_insnbuf ins, slot;
2023 int ilen, islots, is;
2025 const char *opcname;
2030 ins = xtensa_insnbuf_alloc (isa);
2031 slot = xtensa_insnbuf_alloc (isa);
2034 for (ia = start_pc, bt = ia; ia < finish_pc ; ia += ilen)
2036 if (ia + xtensa_isa_maxlength (isa) > bt)
2045 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2046 ifmt = xtensa_format_decode (isa, ins);
2047 if (ifmt == XTENSA_UNDEFINED)
2049 ilen = xtensa_format_length (isa, ifmt);
2050 if (ilen == XTENSA_UNDEFINED)
2052 islots = xtensa_format_num_slots (isa, ifmt);
2053 if (islots == XTENSA_UNDEFINED)
2056 for (is = 0; is < islots; ++is)
2058 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2061 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2062 if (opc == XTENSA_UNDEFINED)
2065 opcname = xtensa_opcode_name (isa, opc);
2067 if ((strcasecmp (opcname,
"ret.n") == 0)
2068 || (strcasecmp (opcname,
"ret") == 0))
2076 xtensa_insnbuf_free(isa, slot);
2077 xtensa_insnbuf_free(isa, ins);
2114 char ch = *opcname++;
2116 if ((ch !=
'r') && (ch !=
'w') && (ch !=
'x'))
2118 if (*opcname++ !=
's')
2120 if (*opcname++ !=
'r')
2122 if (*opcname++ !=
'.')
2133 const char *opcname;
2136 DEBUGTRACE (
"call0_classify_opcode (..., opc = %d)\n", opc);
2140 opcname = xtensa_opcode_name (isa, opc);
2143 || strcasecmp (opcname,
"ill") == 0
2144 || strcasecmp (opcname,
"ill.n") == 0)
2146 else if (strcasecmp (opcname,
"break") == 0
2147 || strcasecmp (opcname,
"break.n") == 0)
2149 else if (strcasecmp (opcname,
"entry") == 0)
2151 else if (strcasecmp (opcname,
"rfwo") == 0)
2153 else if (strcasecmp (opcname,
"rfwu") == 0)
2155 else if (xtensa_opcode_is_branch (isa, opc) > 0
2156 || xtensa_opcode_is_jump (isa, opc) > 0
2157 || xtensa_opcode_is_loop (isa, opc) > 0
2158 || xtensa_opcode_is_call (isa, opc) > 0
2159 || strcasecmp (opcname,
"simcall") == 0
2160 || strcasecmp (opcname,
"syscall") == 0)
2164 else if (strcasecmp (opcname,
"add") == 0
2165 || strcasecmp (opcname,
"add.n") == 0)
2167 else if (strcasecmp (opcname,
"and") == 0)
2169 else if (strcasecmp (opcname,
"addi") == 0
2170 || strcasecmp (opcname,
"addi.n") == 0
2171 || strcasecmp (opcname,
"addmi") == 0)
2173 else if (strcasecmp (opcname,
"sub") == 0)
2175 else if (strcasecmp (opcname,
"mov.n") == 0
2176 || strcasecmp (opcname,
"or") == 0)
2178 else if (strcasecmp (opcname,
"movi") == 0
2179 || strcasecmp (opcname,
"movi.n") == 0)
2181 else if (strcasecmp (opcname,
"l32r") == 0)
2183 else if (strcasecmp (opcname,
"s32i") == 0
2184 || strcasecmp (opcname,
"s32i.n") == 0)
2186 else if (strcasecmp (opcname,
"l32e") == 0)
2188 else if (strcasecmp (opcname,
"s32e") == 0)
2209 unsigned litbase, litaddr, litval;
2222 if (src[odv[1]].fr_reg ==
C0_CONST)
2227 else if (src[odv[2]].fr_reg ==
C0_CONST)
2240 if ((src[odv[0]].fr_reg == spreg) && (src[odv[1]].fr_reg == spreg))
2242 if (src[odv[2]].fr_reg ==
C0_CONST)
2246 else if ((src[odv[0]].fr_reg == spreg)
2247 && (src[odv[2]].fr_reg == spreg))
2249 if (src[odv[1]].fr_reg ==
C0_CONST)
2255 if (src[odv[1]].fr_reg ==
C0_CONST)
2260 else if (src[odv[2]].fr_reg ==
C0_CONST)
2270 if (src[odv[2]].fr_reg ==
C0_CONST)
2294 dst[odv[0]].
fr_ofs = odv[1];
2303 litaddr = litbase & 1
2304 ? (litbase & ~1) + (
signed)odv[1]
2305 : (pc + 3 + (signed)odv[1]) & ~3;
2308 dst[odv[0]].
fr_ofs = litval;
2316 && (odv[1] == spreg)
2320 if (src[odv[1]].fr_reg == spreg
2321 && (src[odv[1]].fr_ofs & 3) == 0
2322 && src[odv[0]].fr_reg >= 0
2323 && src[odv[0]].fr_ofs == 0
2324 && src[src[odv[0]].fr_reg].to_stk ==
C0_NOSTK)
2380 xtensa_insnbuf ins, slot;
2382 int ilen, islots, is;
2395 DEBUGTRACE (
"call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2396 (
int)start, (
int)pc);
2412 if (prologue_sal.
line != 0)
2413 body_pc = prologue_sal.
end;
2420 body_pc =
min (end_pc, body_pc);
2423 body_pc =
min (pc, body_pc);
2432 ins = xtensa_insnbuf_alloc (isa);
2433 slot = xtensa_insnbuf_alloc (isa);
2435 for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
2441 if (ia + xtensa_isa_maxlength (isa) > bt)
2446 error (
_(
"Unable to read target memory ..."));
2451 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2452 ifmt = xtensa_format_decode (isa, ins);
2453 if (ifmt == XTENSA_UNDEFINED)
2458 ilen = xtensa_format_length (isa, ifmt);
2459 if (ilen == XTENSA_UNDEFINED)
2464 islots = xtensa_format_num_slots (isa, ifmt);
2465 if (islots == XTENSA_UNDEFINED)
2475 for (j = 0; j < nregs; ++j)
2478 for (is = 0; is < islots; ++is)
2482 fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
2486 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2487 DEBUGVERB (
"[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2489 if (opc == XTENSA_UNDEFINED)
2522 nods = xtensa_opcode_num_operands (isa, opc);
2523 if (nods == XTENSA_UNDEFINED)
2531 fail = xtensa_operand_get_field (isa, opc, j, ifmt,
2536 fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
2544 if (odv[2] == odv[1])
2547 if ((odv[0] == 1) && (odv[1] != 1))
2561 opclass, nods, odv, ia, 1, cache);
2567 DEBUGVERB (
"[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2568 (
unsigned)ia, fail ?
"failed" :
"succeeded");
2569 xtensa_insnbuf_free(isa, slot);
2570 xtensa_insnbuf_free(isa, ins);
2585 int fp_regnum =
C0_SP, c0_hasfp = 0, c0_frmsz = 0, prev_sp = 0, to_stk;
2602 goto finish_frame_analysis;
2645 goto finish_frame_analysis;
2657 prev_sp = unaligned_sp + c0_frmsz;
2660 prev_sp = fp + c0_frmsz;
2669 c0_frmsz += fp - sp;
2716 finish_frame_analysis:
2717 cache->
pc = start_pc;
2720 cache->
prev_sp = (ra != 0) ? prev_sp : 0;
2741 unsigned int spilled_value
2777 #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
2792 xtensa_insnbuf ins, slot;
2796 int ilen, islots, is;
2805 int WindowUnderflow12 = (current_pc & 0x1ff) >= 0x140;
2809 ins = xtensa_insnbuf_alloc (isa);
2810 slot = xtensa_insnbuf_alloc (isa);
2821 if (ia + xtensa_isa_maxlength (isa) > bt)
2828 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2829 ifmt = xtensa_format_decode (isa, ins);
2830 if (ifmt == XTENSA_UNDEFINED)
2832 ilen = xtensa_format_length (isa, ifmt);
2833 if (ilen == XTENSA_UNDEFINED)
2835 islots = xtensa_format_num_slots (isa, ifmt);
2836 if (islots == XTENSA_UNDEFINED)
2838 for (is = 0; is < islots; ++is)
2840 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2842 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2843 if (opc == XTENSA_UNDEFINED)
2874 if (WindowUnderflow12)
2897 if ( xtensa_opcode_num_operands (isa, opc) != 3 )
2899 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, &at))
2901 if (xtensa_operand_decode (isa, opc, 0, &at))
2903 if (xtensa_operand_get_field (isa, opc, 1, ifmt, is, slot, &as))
2905 if (xtensa_operand_decode (isa, opc, 1, &as))
2907 if (xtensa_operand_get_field (isa, opc, 2, ifmt, is, slot, &offset))
2909 if (xtensa_operand_decode (isa, opc, 2, &offset))
2912 (*func) (gdbarch, at, as,
offset, wb);
2929 int epc1_regnum, i,
regnum;
2944 Unable to decode Xtensa Window Interrupt Handler's code."));
2954 cache->
wd.
ws = ws ^ (1 << wb);
2956 cache->
wd.
ws = ws | (1 << wb);
2958 cache->
wd.
wb = (ps & 0xf00) >> 8;
2973 if (epc1_regnum < 0)
2974 error(
_(
"Unable to read Xtensa register EPC1"));
3023 DEBUGTRACE (
"xtensa_skip_prologue (start_pc = 0x%08x)\n", (
int) start_pc);
3025 #if DONT_SKIP_PROLOGUE
3032 if (prologue_sal.
line != 0)
3049 if (end_func != start_pc)
3052 return prologue_sal.
end;
3058 return body_pc != 0 ? body_pc : start_pc;
3078 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
3105 _(
"the following are invalid: %s"), buf);
3116 int n, max_size = 4;
3122 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
3190 static struct gdbarch *
3194 struct gdbarch *gdbarch;
3195 struct xtensa_abi_handler *abi_handler;
3200 info.
byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
3282 error (
_(
"xtensa_dump_tdep(): not implemented"));
3299 _(
"Set Xtensa debugging."),
3300 _(
"Show Xtensa debugging."),
_(
"\
3301 When non-zero, Xtensa-specific debugging is enabled. \
3302 Can be 1, 2, 3, or 4 indicating the level of debugging."),
struct xtensa_frame_cache xtensa_frame_cache_t
void reggroup_add(struct gdbarch *gdbarch, struct reggroup *group)
void set_gdbarch_num_regs(struct gdbarch *gdbarch, int num_regs)
void set_gdbarch_frame_align(struct gdbarch *gdbarch, gdbarch_frame_align_ftype frame_align)
void set_gdbarch_have_nonsteppable_watchpoint(struct gdbarch *gdbarch, int have_nonsteppable_watchpoint)
#define DEBUGINFO(args...)
ULONGEST extract_unsigned_integer(const gdb_byte *, int, enum bfd_endian)
static enum register_status xtensa_register_read_masked(struct regcache *regcache, xtensa_register_t *reg, gdb_byte *buffer)
xtensa_isa xtensa_default_isa
void set_gdbarch_ps_regnum(struct gdbarch *gdbarch, int ps_regnum)
static enum return_value_convention xtensa_return_value(struct gdbarch *gdbarch, struct value *function, struct type *valtype, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf)
static CORE_ADDR xtensa_frame_base_address(struct frame_info *this_frame, void **this_cache)
struct frame_id frame_id_build(CORE_ADDR stack_addr, CORE_ADDR code_addr)
CORE_ADDR extract_typed_address(const gdb_byte *buf, struct type *type)
static int xtensa_find_register_by_name(struct gdbarch *gdbarch, char *name)
static int rwx_special_register(const char *opcname)
struct type * virtual_type
CORE_ADDR get_frame_pc(struct frame_info *frame)
void add_setshow_zuinteger_cmd(const char *name, enum command_class theclass, unsigned int *var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_sfunc_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
struct reggroup * reggroup_new(const char *name, enum reggroup_type type)
static void xtensa_supply_gregset(const struct regset *regset, struct regcache *rc, int regnum, const void *gregs, size_t len)
static int windowing_enabled(struct gdbarch *gdbarch, unsigned int ps)
struct gdbarch * get_regcache_arch(const struct regcache *regcache)
struct value * frame_unwind_got_memory(struct frame_info *frame, int regnum, CORE_ADDR addr)
void write_memory_unsigned_integer(CORE_ADDR addr, int len, enum bfd_endian byte_order, ULONGEST value)
struct xtensa_call0_frame_cache xtensa_call0_frame_cache_t
static struct xtensa_frame_cache * xtensa_alloc_frame_cache(int windowed)
void warning(const char *fmt,...)
#define DENSITY_BIG_BREAKPOINT
void set_gdbarch_stab_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_stab_reg_to_regnum_ftype stab_reg_to_regnum)
char * ui_file_xstrdup(struct ui_file *file, long *length)
ULONGEST align_down(ULONGEST v, int n)
const struct builtin_type * builtin_type(struct gdbarch *gdbarch)
struct gdbarch_tdep xtensa_tdep
unsigned int isa_use_windowed_registers
void internal_error(const char *file, int line, const char *fmt,...)
static struct xtensa_frame_cache * xtensa_frame_cache(struct frame_info *this_frame, void **this_cache)
void frame_unwind_register(struct frame_info *frame, int regnum, gdb_byte *buf)
static int arreg_number(struct gdbarch *gdbarch, int a_regnum, ULONGEST wb)
static int xtensa_register_reggroup_p(struct gdbarch *gdbarch, int regnum, struct reggroup *group)
struct type * builtin_uint8
static int extract_call_winsize(struct gdbarch *gdbarch, CORE_ADDR pc)
static CORE_ADDR xtensa_skip_prologue(struct gdbarch *gdbarch, CORE_ADDR start_pc)
struct type * builtin_uint16
void set_gdbarch_register_reggroup_p(struct gdbarch *gdbarch, gdbarch_register_reggroup_p_ftype register_reggroup_p)
xtensa_register_t * regmap
static enum register_status xtensa_pseudo_register_read(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, gdb_byte *buffer)
struct link_map_offsets * svr4_ilp32_fetch_link_map_offsets(void)
static unsigned int xtensa_scan_prologue(struct gdbarch *gdbarch, CORE_ADDR current_pc)
xtensa_call0_frame_cache_t c0
struct xtensa_c0reg xtensa_c0reg_t
static struct reggroup * xtensa_user_reggroup
static struct type * xtensa_register_type(struct gdbarch *gdbarch, int regnum)
struct reggroup *const restore_reggroup
int gdbarch_num_regs(struct gdbarch *gdbarch)
xtensa_windowed_frame_cache_t wd
struct reggroup *const all_reggroup
static struct reggroup * xtensa_vectra_reggroup
void set_gdbarch_dwarf2_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_dwarf2_reg_to_regnum_ftype dwarf2_reg_to_regnum)
struct gdbarch_tdep * gdbarch_tdep(struct gdbarch *gdbarch)
int gdbarch_ps_regnum(struct gdbarch *gdbarch)
void frame_unwind_append_unwinder(struct gdbarch *gdbarch, const struct frame_unwind *unwinder)
int max_register_virtual_size
struct regcache * get_current_regcache(void)
#define XTENSA_MAX_COPROCESSOR
#define FRAME_OBSTACK_ZALLOC(TYPE)
void store_unsigned_integer(gdb_byte *, int, enum bfd_endian, ULONGEST)
struct ctype_cache * next
static struct reggroup * xtensa_ar_reggroup
struct value * frame_unwind_got_constant(struct frame_info *frame, int regnum, ULONGEST val)
void gdbarch_register(enum bfd_architecture bfd_architecture, gdbarch_init_ftype *init, gdbarch_dump_tdep_ftype *dump_tdep)
static void warning_once(void)
mach_port_t kern_return_t mach_port_t msgports mach_port_t kern_return_t pid_t pid mach_port_t kern_return_t mach_port_t task mach_port_t kern_return_t int flags
int gdbarch_num_pseudo_regs(struct gdbarch *gdbarch)
struct reggroup *const float_reggroup
void frame_base_set_default(struct gdbarch *gdbarch, const struct frame_base *default_base)
void set_gdbarch_pseudo_register_write(struct gdbarch *gdbarch, gdbarch_pseudo_register_write_ftype pseudo_register_write)
static CORE_ADDR xtensa_unwind_pc(struct gdbarch *gdbarch, struct frame_info *next_frame)
static void xtensa_iterate_over_regset_sections(struct gdbarch *gdbarch, iterate_over_regset_sections_cb *cb, void *cb_data, const struct regcache *regcache)
void set_gdbarch_register_type(struct gdbarch *gdbarch, gdbarch_register_type_ftype register_type)
struct type * check_typedef(struct type *type)
LONGEST read_memory_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
unsigned int isa_use_exceptions
const gdb_byte * value_contents(struct value *value)
struct reggroup *const general_reggroup
enum register_status regcache_raw_read_part(struct regcache *regcache, int regnum, int offset, int len, gdb_byte *buf)
static void xtensa_add_reggroups(struct gdbarch *gdbarch)
void initialize_file_ftype(void)
struct symtab_and_line find_pc_line(CORE_ADDR pc, int notcurrent)
static void xtensa_derive_tdep(struct gdbarch_tdep *tdep)
#define XTENSA_DBREGN_SREG(n)
enum register_status regcache_cooked_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
struct reggroup *const system_reggroup
void set_gdbarch_sp_regnum(struct gdbarch *gdbarch, int sp_regnum)
static const char * xtensa_register_name(struct gdbarch *gdbarch, int regnum)
void set_gdbarch_decr_pc_after_break(struct gdbarch *gdbarch, CORE_ADDR decr_pc_after_break)
xtensa_elf_greg_t windowstart
void set_gdbarch_dummy_id(struct gdbarch *gdbarch, gdbarch_dummy_id_ftype dummy_id)
void fprintf_unfiltered(struct ui_file *stream, const char *format,...)
mach_port_t mach_port_t name mach_port_t mach_port_t name error_t int status
static CORE_ADDR xtensa_push_dummy_call(struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr)
void set_gdbarch_believe_pcc_promotion(struct gdbarch *gdbarch, int believe_pcc_promotion)
xtensa_exception_handler_t
enum bfd_endian gdbarch_byte_order(struct gdbarch *gdbarch)
struct cleanup * make_cleanup(make_cleanup_ftype *function, void *arg)
static const unsigned char * xtensa_breakpoint_from_pc(struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
static void execute_l32e(struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
void set_solib_svr4_fetch_link_map_offsets(struct gdbarch *gdbarch, struct link_map_offsets *(*flmo)(void))
xtensa_register_group_t group
int find_pc_partial_function(CORE_ADDR pc, const char **name, CORE_ADDR *address, CORE_ADDR *endaddr)
static void call0_frame_cache(struct frame_info *this_frame, xtensa_frame_cache_t *cache, CORE_ADDR pc)
static void xtensa_init_reggroups(void)
unsigned int num_nopriv_regs
void set_gdbarch_unwind_pc(struct gdbarch *gdbarch, gdbarch_unwind_pc_ftype unwind_pc)
void set_gdbarch_breakpoint_from_pc(struct gdbarch *gdbarch, gdbarch_breakpoint_from_pc_ftype breakpoint_from_pc)
struct type * builtin_uint32
int default_frame_sniffer(const struct frame_unwind *self, struct frame_info *this_frame, void **this_prologue_cache)
xtensa_c0reg_t c0_rt[C0_NREGS]
static xtensa_exception_handler_t execute_code(struct gdbarch *gdbarch, CORE_ADDR current_pc, CORE_ADDR wb)
struct type * builtin_long
struct value * value_cast(struct type *type, struct value *arg2)
enum register_status regcache_raw_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
static const struct frame_unwind xtensa_unwind
xtensa_elf_greg_t windowbase
static CORE_ADDR call0_analyze_prologue(struct gdbarch *gdbarch, CORE_ADDR start, CORE_ADDR pc, int nregs, xtensa_frame_cache_t *cache)
static int xtensa_window_interrupt_insn(struct gdbarch *gdbarch, CORE_ADDR pc)
static CORE_ADDR a0_saved
char * xstrprintf(const char *format,...)
struct type * arch_integer_type(struct gdbarch *gdbarch, int bit, int unsigned_p, char *name)
struct cmd_list_element * setdebuglist
void read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
void( iterate_over_regset_sections_cb)(const char *sect_name, int size, const struct regset *regset, const char *human_name, void *cb_data)
struct reggroup *const vector_reggroup
ULONGEST get_frame_register_unsigned(struct frame_info *frame, int regnum)
struct ui_file * gdb_stdlog
struct ui_file * mem_fileopen(void)
static void xtensa_dump_tdep(struct gdbarch *gdbarch, struct ui_file *file)
struct type * builtin_uint128
void set_gdbarch_frame_args_skip(struct gdbarch *gdbarch, CORE_ADDR frame_args_skip)
CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS]
int max_register_raw_size
static void xtensa_write_register(int regnum, ULONGEST value)
static int call0_track_op(struct gdbarch *gdbarch, xtensa_c0reg_t dst[], xtensa_c0reg_t src[], xtensa_insn_kind opclass, int nods, unsigned odv[], CORE_ADDR pc, int spreg, xtensa_frame_cache_t *cache)
static CORE_ADDR xtensa_frame_align(struct gdbarch *gdbarch, CORE_ADDR address)
static CORE_ADDR a7_saved
void regcache_raw_write_part(struct regcache *regcache, int regnum, int offset, int len, const gdb_byte *buf)
static void execute_s32e(struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
unsigned int target_number
const char const char int
int core_addr_lessthan(CORE_ADDR lhs, CORE_ADDR rhs)
void set_gdbarch_pseudo_register_read(struct gdbarch *gdbarch, gdbarch_pseudo_register_read_ftype pseudo_register_read)
static int areg_number(struct gdbarch *gdbarch, int ar_regnum, unsigned int wb)
struct cleanup * make_cleanup_ui_file_delete(struct ui_file *arg)
#define DEBUGVERB(args...)
unsigned int target_flags
#define TYPE_CODE(thistype)
enum register_status regcache_raw_read(struct regcache *regcache, int regnum, gdb_byte *buf)
static struct value * xtensa_frame_prev_register(struct frame_info *this_frame, void **this_cache, int regnum)
struct value * frame_unwind_got_register(struct frame_info *frame, int regnum, int new_regnum)
void regcache_cooked_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
#define LITTLE_BREAKPOINT
int target_read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
struct type * builtin_data_ptr
const char * host_address_to_string(const void *addr)
const xtensa_mask_t * mask
static void xtensa_frame_this_id(struct frame_info *this_frame, void **this_cache, struct frame_id *this_id)
static void xtensa_verify_config(struct gdbarch *gdbarch)
xtensa_register_type_t type
void regcache_raw_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
void set_gdbarch_num_pseudo_regs(struct gdbarch *gdbarch, int num_pseudo_regs)
static xtensa_insn_kind call0_classify_opcode(xtensa_isa isa, xtensa_opcode opc)
void dwarf2_append_unwinders(struct gdbarch *gdbarch)
struct ctype_cache * type_entries
static void xtensa_store_return_value(struct type *type, struct regcache *regcache, const void *dst)
#define DENSITY_LITTLE_BREAKPOINT
static int xtensa_reg_to_regnum(struct gdbarch *gdbarch, int regnum)
#define XTENSA_NUM_SAVED_AREGS
void regcache_raw_supply(struct regcache *regcache, int regnum, const void *buf)
static void xtensa_window_interrupt_frame_cache(struct frame_info *this_frame, xtensa_frame_cache_t *cache, CORE_ADDR pc)
unsigned long long ULONGEST
enum unwind_stop_reason default_frame_unwind_stop_reason(struct frame_info *this_frame, void **this_cache)
static unsigned int xtensa_debug_level
struct type * value_type(const struct value *value)
void set_gdbarch_return_value(struct gdbarch *gdbarch, gdbarch_return_value_ftype return_value)
struct cmd_list_element * showdebuglist
int gdbarch_pc_regnum(struct gdbarch *gdbarch)
static CORE_ADDR a11_saved
static void xtensa_pseudo_register_write(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buffer)
struct reggroup *const save_reggroup
#define TYPE_LENGTH(thistype)
static void xtensa_extract_return_value(struct type *type, struct regcache *regcache, void *dst)
static int xtensa_coprocessor_register_group(struct reggroup *group)
void set_gdbarch_push_dummy_call(struct gdbarch *gdbarch, gdbarch_push_dummy_call_ftype push_dummy_call)
static struct gdbarch * xtensa_gdbarch_init(struct gdbarch_info info, struct gdbarch_list *arches)
#define XTENSA_IS_ENTRY(gdbarch, op1)
ULONGEST read_memory_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
struct type * builtin_uint64
void set_gdbarch_iterate_over_regset_sections(struct gdbarch *gdbarch, gdbarch_iterate_over_regset_sections_ftype iterate_over_regset_sections)
unsigned int num_pseudo_regs
#define DEBUGTRACE(args...)
void write_memory(CORE_ADDR memaddr, const bfd_byte *myaddr, ssize_t len)
void set_gdbarch_skip_prologue(struct gdbarch *gdbarch, gdbarch_skip_prologue_ftype skip_prologue)
#define XTENSA_REGISTER_FLAGS_PRIVILEGED
static unsigned long xtensa_read_register(int regnum)
enum bfd_endian byte_order
static struct frame_id xtensa_dummy_id(struct gdbarch *gdbarch, struct frame_info *this_frame)
struct xtensa_windowed_frame_cache xtensa_windowed_frame_cache_t
enum bfd_endian byte_order
void set_gdbarch_pc_regnum(struct gdbarch *gdbarch, int pc_regnum)
void set_gdbarch_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype register_name)
CORE_ADDR get_frame_func(struct frame_info *this_frame)
void error(const char *fmt,...)
struct gdbarch * gdbarch_alloc(const struct gdbarch_info *info, struct gdbarch_tdep *tdep)
void set_gdbarch_inner_than(struct gdbarch *gdbarch, gdbarch_inner_than_ftype inner_than)
struct gdbarch * get_frame_arch(struct frame_info *this_frame)
static void xtensa_register_write_masked(struct regcache *regcache, xtensa_register_t *reg, const gdb_byte *buffer)
static int xtensa_session_once_reported
void do_cleanups(struct cleanup *old_chain)
void regcache_cooked_write(struct regcache *regcache, int regnum, const gdb_byte *buf)
#define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN
initialize_file_ftype _initialize_xtensa_tdep
static int call0_ret(CORE_ADDR start_pc, CORE_ADDR finish_pc)
void set_gdbarch_print_insn(struct gdbarch *gdbarch, gdbarch_print_insn_ftype print_insn)
struct type * builtin_int
void regcache_raw_write(struct regcache *regcache, int regnum, const gdb_byte *buf)
const ULONGEST const LONGEST len