GDB (xrefs)
/tmp/gdb-7.10/gdb/mep-tdep.c
Go to the documentation of this file.
1 /* Target-dependent code for the Toshiba MeP for GDB, the GNU debugger.
2 
3  Copyright (C) 2001-2015 Free Software Foundation, Inc.
4 
5  Contributed by Red Hat, Inc.
6 
7  This file is part of GDB.
8 
9  This program is free software; you can redistribute it and/or modify
10  it under the terms of the GNU General Public License as published by
11  the Free Software Foundation; either version 3 of the License, or
12  (at your option) any later version.
13 
14  This program is distributed in the hope that it will be useful,
15  but WITHOUT ANY WARRANTY; without even the implied warranty of
16  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17  GNU General Public License for more details.
18 
19  You should have received a copy of the GNU General Public License
20  along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 
22 #include "defs.h"
23 #include "frame.h"
24 #include "frame-unwind.h"
25 #include "frame-base.h"
26 #include "symtab.h"
27 #include "gdbtypes.h"
28 #include "gdbcmd.h"
29 #include "gdbcore.h"
30 #include "value.h"
31 #include "inferior.h"
32 #include "dis-asm.h"
33 #include "symfile.h"
34 #include "objfiles.h"
35 #include "language.h"
36 #include "arch-utils.h"
37 #include "regcache.h"
38 #include "remote.h"
39 #include "floatformat.h"
40 #include "sim-regno.h"
41 #include "disasm.h"
42 #include "trad-frame.h"
43 #include "reggroups.h"
44 #include "elf-bfd.h"
45 #include "elf/mep.h"
46 #include "prologue-value.h"
47 #include "cgen/bitset.h"
48 #include "infcall.h"
49 
50 /* Get the user's customized MeP coprocessor register names from
51  libopcodes. */
52 #include "opcodes/mep-desc.h"
53 #include "opcodes/mep-opc.h"
54 
55 
56 /* The gdbarch_tdep structure. */
57 
58 /* A quick recap for GDB hackers not familiar with the whole Toshiba
59  Media Processor story:
60 
61  The MeP media engine is a configureable processor: users can design
62  their own coprocessors, implement custom instructions, adjust cache
63  sizes, select optional standard facilities like add-and-saturate
64  instructions, and so on. Then, they can build custom versions of
65  the GNU toolchain to support their customized chips. The
66  MeP-Integrator program (see utils/mep) takes a GNU toolchain source
67  tree, and a config file pointing to various files provided by the
68  user describing their customizations, and edits the source tree to
69  produce a compiler that can generate their custom instructions, an
70  assembler that can assemble them and recognize their custom
71  register names, and so on.
72 
73  Furthermore, the user can actually specify several of these custom
74  configurations, called 'me_modules', and get a toolchain which can
75  produce code for any of them, given a compiler/assembler switch;
76  you say something like 'gcc -mconfig=mm_max' to generate code for
77  the me_module named 'mm_max'.
78 
79  GDB, in particular, needs to:
80 
81  - use the coprocessor control register names provided by the user
82  in their hardware description, in expressions, 'info register'
83  output, and disassembly,
84 
85  - know the number, names, and types of the coprocessor's
86  general-purpose registers, adjust the 'info all-registers' output
87  accordingly, and print error messages if the user refers to one
88  that doesn't exist
89 
90  - allow access to the control bus space only when the configuration
91  actually has a control bus, and recognize which regions of the
92  control bus space are actually populated,
93 
94  - disassemble using the user's provided mnemonics for their custom
95  instructions, and
96 
97  - recognize whether the $hi and $lo registers are present, and
98  allow access to them only when they are actually there.
99 
100  There are three sources of information about what sort of me_module
101  we're actually dealing with:
102 
103  - A MeP executable file indicates which me_module it was compiled
104  for, and libopcodes has tables describing each module. So, given
105  an executable file, we can find out about the processor it was
106  compiled for.
107 
108  - There are SID command-line options to select a particular
109  me_module, overriding the one specified in the ELF file. SID
110  provides GDB with a fake read-only register, 'module', which
111  indicates which me_module GDB is communicating with an instance
112  of.
113 
114  - There are SID command-line options to enable or disable certain
115  optional processor features, overriding the defaults for the
116  selected me_module. The MeP $OPT register indicates which
117  options are present on the current processor. */
118 
119 
120 struct gdbarch_tdep
121 {
122  /* A CGEN cpu descriptor for this BFD architecture and machine.
123 
124  Note: this is *not* customized for any particular me_module; the
125  MeP libopcodes machinery actually puts off module-specific
126  customization until the last minute. So this contains
127  information about all supported me_modules. */
128  CGEN_CPU_DESC cpu_desc;
129 
130  /* The me_module index from the ELF file we used to select this
131  architecture, or CONFIG_NONE if there was none.
132 
133  Note that we should prefer to use the me_module number available
134  via the 'module' register, whenever we're actually talking to a
135  real target.
136 
137  In the absence of live information, we'd like to get the
138  me_module number from the ELF file. But which ELF file: the
139  executable file, the core file, ... ? The answer is, "the last
140  ELF file we used to set the current architecture". Thus, we
141  create a separate instance of the gdbarch structure for each
142  me_module value mep_gdbarch_init sees, and store the me_module
143  value from the ELF file here. */
144  CONFIG_ATTR me_module;
145 };
146 
147 
148 
149 /* Getting me_module information from the CGEN tables. */
150 
151 
152 /* Find an entry in the DESC's hardware table whose name begins with
153  PREFIX, and whose ISA mask intersects COPRO_ISA_MASK, but does not
154  intersect with GENERIC_ISA_MASK. If there is no matching entry,
155  return zero. */
156 static const CGEN_HW_ENTRY *
158  const char *prefix,
159  CGEN_BITSET *copro_isa_mask,
160  CGEN_BITSET *generic_isa_mask)
161 {
162  int prefix_len = strlen (prefix);
163  int i;
164 
165  for (i = 0; i < desc->hw_table.num_entries; i++)
166  {
167  const CGEN_HW_ENTRY *hw = desc->hw_table.entries[i];
168  if (strncmp (prefix, hw->name, prefix_len) == 0)
169  {
170  CGEN_BITSET *hw_isa_mask
171  = ((CGEN_BITSET *)
172  &CGEN_ATTR_CGEN_HW_ISA_VALUE (CGEN_HW_ATTRS (hw)));
173 
174  if (cgen_bitset_intersect_p (hw_isa_mask, copro_isa_mask)
175  && ! cgen_bitset_intersect_p (hw_isa_mask, generic_isa_mask))
176  return hw;
177  }
178  }
179 
180  return 0;
181 }
182 
183 
184 /* Find an entry in DESC's hardware table whose type is TYPE. Return
185  zero if there is none. */
186 static const CGEN_HW_ENTRY *
187 find_hw_entry_by_type (CGEN_CPU_DESC desc, CGEN_HW_TYPE type)
188 {
189  int i;
190 
191  for (i = 0; i < desc->hw_table.num_entries; i++)
192  {
193  const CGEN_HW_ENTRY *hw = desc->hw_table.entries[i];
194 
195  if (hw->type == type)
196  return hw;
197  }
198 
199  return 0;
200 }
201 
202 
203 /* Return the CGEN hardware table entry for the coprocessor register
204  set for ME_MODULE, whose name prefix is PREFIX. If ME_MODULE has
205  no such register set, return zero. If ME_MODULE is the generic
206  me_module CONFIG_NONE, return the table entry for the register set
207  whose hardware type is GENERIC_TYPE. */
208 static const CGEN_HW_ENTRY *
209 me_module_register_set (CONFIG_ATTR me_module,
210  const char *prefix,
211  CGEN_HW_TYPE generic_type)
212 {
213  /* This is kind of tricky, because the hardware table is constructed
214  in a way that isn't very helpful. Perhaps we can fix that, but
215  here's how it works at the moment:
216 
217  The configuration map, `mep_config_map', is indexed by me_module
218  number, and indicates which coprocessor and core ISAs that
219  me_module supports. The 'core_isa' mask includes all the core
220  ISAs, and the 'cop_isa' mask includes all the coprocessor ISAs.
221  The entry for the generic me_module, CONFIG_NONE, has an empty
222  'cop_isa', and its 'core_isa' selects only the standard MeP
223  instruction set.
224 
225  The CGEN CPU descriptor's hardware table, desc->hw_table, has
226  entries for all the register sets, for all me_modules. Each
227  entry has a mask indicating which ISAs use that register set.
228  So, if an me_module supports some coprocessor ISA, we can find
229  applicable register sets by scanning the hardware table for
230  register sets whose masks include (at least some of) those ISAs.
231 
232  Each hardware table entry also has a name, whose prefix says
233  whether it's a general-purpose ("h-cr") or control ("h-ccr")
234  coprocessor register set. It might be nicer to have an attribute
235  indicating what sort of register set it was, that we could use
236  instead of pattern-matching on the name.
237 
238  When there is no hardware table entry whose mask includes a
239  particular coprocessor ISA and whose name starts with a given
240  prefix, then that means that that coprocessor doesn't have any
241  registers of that type. In such cases, this function must return
242  a null pointer.
243 
244  Coprocessor register sets' masks may or may not include the core
245  ISA for the me_module they belong to. Those generated by a2cgen
246  do, but the sample me_module included in the unconfigured tree,
247  'ccfx', does not.
248 
249  There are generic coprocessor register sets, intended only for
250  use with the generic me_module. Unfortunately, their masks
251  include *all* ISAs --- even those for coprocessors that don't
252  have such register sets. This makes detecting the case where a
253  coprocessor lacks a particular register set more complicated.
254 
255  So, here's the approach we take:
256 
257  - For CONFIG_NONE, we return the generic coprocessor register set.
258 
259  - For any other me_module, we search for a register set whose
260  mask contains any of the me_module's coprocessor ISAs,
261  specifically excluding the generic coprocessor register sets. */
262 
263  CGEN_CPU_DESC desc = gdbarch_tdep (target_gdbarch ())->cpu_desc;
264  const CGEN_HW_ENTRY *hw;
265 
266  if (me_module == CONFIG_NONE)
267  hw = find_hw_entry_by_type (desc, generic_type);
268  else
269  {
270  CGEN_BITSET *cop = &mep_config_map[me_module].cop_isa;
271  CGEN_BITSET *core = &mep_config_map[me_module].core_isa;
272  CGEN_BITSET *generic = &mep_config_map[CONFIG_NONE].core_isa;
273  CGEN_BITSET *cop_and_core;
274 
275  /* The coprocessor ISAs include the ISA for the specific core which
276  has that coprocessor. */
277  cop_and_core = cgen_bitset_copy (cop);
278  cgen_bitset_union (cop, core, cop_and_core);
279  hw = find_hw_entry_by_prefix_and_isa (desc, prefix, cop_and_core, generic);
280  }
281 
282  return hw;
283 }
284 
285 
286 /* Given a hardware table entry HW representing a register set, return
287  a pointer to the keyword table with all the register names. If HW
288  is NULL, return NULL, to propage the "no such register set" info
289  along. */
290 static CGEN_KEYWORD *
291 register_set_keyword_table (const CGEN_HW_ENTRY *hw)
292 {
293  if (! hw)
294  return NULL;
295 
296  /* Check that HW is actually a keyword table. */
297  gdb_assert (hw->asm_type == CGEN_ASM_KEYWORD);
298 
299  /* The 'asm_data' field of a register set's hardware table entry
300  refers to a keyword table. */
301  return (CGEN_KEYWORD *) hw->asm_data;
302 }
303 
304 
305 /* Given a keyword table KEYWORD and a register number REGNUM, return
306  the name of the register, or "" if KEYWORD contains no register
307  whose number is REGNUM. */
308 static char *
309 register_name_from_keyword (CGEN_KEYWORD *keyword_table, int regnum)
310 {
311  const CGEN_KEYWORD_ENTRY *entry
312  = cgen_keyword_lookup_value (keyword_table, regnum);
313 
314  if (entry)
315  {
316  char *name = entry->name;
317 
318  /* The CGEN keyword entries for register names include the
319  leading $, which appears in MeP assembly as well as in GDB.
320  But we don't want to return that; GDB core code adds that
321  itself. */
322  if (name[0] == '$')
323  name++;
324 
325  return name;
326  }
327  else
328  return "";
329 }
330 
331 
332 /* Masks for option bits in the OPT special-purpose register. */
333 enum {
334  MEP_OPT_DIV = 1 << 25, /* 32-bit divide instruction option */
335  MEP_OPT_MUL = 1 << 24, /* 32-bit multiply instruction option */
336  MEP_OPT_BIT = 1 << 23, /* bit manipulation instruction option */
337  MEP_OPT_SAT = 1 << 22, /* saturation instruction option */
338  MEP_OPT_CLP = 1 << 21, /* clip instruction option */
339  MEP_OPT_MIN = 1 << 20, /* min/max instruction option */
340  MEP_OPT_AVE = 1 << 19, /* average instruction option */
341  MEP_OPT_ABS = 1 << 18, /* absolute difference instruction option */
342  MEP_OPT_LDZ = 1 << 16, /* leading zero instruction option */
343  MEP_OPT_VL64 = 1 << 6, /* 64-bit VLIW operation mode option */
344  MEP_OPT_VL32 = 1 << 5, /* 32-bit VLIW operation mode option */
345  MEP_OPT_COP = 1 << 4, /* coprocessor option */
346  MEP_OPT_DSP = 1 << 2, /* DSP option */
347  MEP_OPT_UCI = 1 << 1, /* UCI option */
348  MEP_OPT_DBG = 1 << 0, /* DBG function option */
349 };
350 
351 
352 /* Given the option_mask value for a particular entry in
353  mep_config_map, produce the value the processor's OPT register
354  would use to represent the same set of options. */
355 static unsigned int
356 opt_from_option_mask (unsigned int option_mask)
357 {
358  /* A table mapping OPT register bits onto CGEN config map option
359  bits. */
360  struct {
361  unsigned int opt_bit, option_mask_bit;
362  } bits[] = {
363  { MEP_OPT_DIV, 1 << CGEN_INSN_OPTIONAL_DIV_INSN },
364  { MEP_OPT_MUL, 1 << CGEN_INSN_OPTIONAL_MUL_INSN },
365  { MEP_OPT_DIV, 1 << CGEN_INSN_OPTIONAL_DIV_INSN },
366  { MEP_OPT_DBG, 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN },
367  { MEP_OPT_LDZ, 1 << CGEN_INSN_OPTIONAL_LDZ_INSN },
368  { MEP_OPT_ABS, 1 << CGEN_INSN_OPTIONAL_ABS_INSN },
369  { MEP_OPT_AVE, 1 << CGEN_INSN_OPTIONAL_AVE_INSN },
370  { MEP_OPT_MIN, 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN },
371  { MEP_OPT_CLP, 1 << CGEN_INSN_OPTIONAL_CLIP_INSN },
372  { MEP_OPT_SAT, 1 << CGEN_INSN_OPTIONAL_SAT_INSN },
373  { MEP_OPT_UCI, 1 << CGEN_INSN_OPTIONAL_UCI_INSN },
374  { MEP_OPT_DSP, 1 << CGEN_INSN_OPTIONAL_DSP_INSN },
375  { MEP_OPT_COP, 1 << CGEN_INSN_OPTIONAL_CP_INSN },
376  };
377 
378  int i;
379  unsigned int opt = 0;
380 
381  for (i = 0; i < (sizeof (bits) / sizeof (bits[0])); i++)
382  if (option_mask & bits[i].option_mask_bit)
383  opt |= bits[i].opt_bit;
384 
385  return opt;
386 }
387 
388 
389 /* Return the value the $OPT register would use to represent the set
390  of options for ME_MODULE. */
391 static unsigned int
392 me_module_opt (CONFIG_ATTR me_module)
393 {
394  return opt_from_option_mask (mep_config_map[me_module].option_mask);
395 }
396 
397 
398 /* Return the width of ME_MODULE's coprocessor data bus, in bits.
399  This is either 32 or 64. */
400 static int
401 me_module_cop_data_bus_width (CONFIG_ATTR me_module)
402 {
403  if (mep_config_map[me_module].option_mask
404  & (1 << CGEN_INSN_OPTIONAL_CP64_INSN))
405  return 64;
406  else
407  return 32;
408 }
409 
410 
411 /* Return true if ME_MODULE is big-endian, false otherwise. */
412 static int
413 me_module_big_endian (CONFIG_ATTR me_module)
414 {
415  return mep_config_map[me_module].big_endian;
416 }
417 
418 
419 /* Return the name of ME_MODULE, or NULL if it has no name. */
420 static const char *
421 me_module_name (CONFIG_ATTR me_module)
422 {
423  /* The default me_module has "" as its name, but it's easier for our
424  callers to test for NULL. */
425  if (! mep_config_map[me_module].name
426  || mep_config_map[me_module].name[0] == '\0')
427  return NULL;
428  else
429  return mep_config_map[me_module].name;
430 }
431 
432 /* Register set. */
433 
434 
435 /* The MeP spec defines the following registers:
436  16 general purpose registers (r0-r15)
437  32 control/special registers (csr0-csr31)
438  32 coprocessor general-purpose registers (c0 -- c31)
439  64 coprocessor control registers (ccr0 -- ccr63)
440 
441  For the raw registers, we assign numbers here explicitly, instead
442  of letting the enum assign them for us; the numbers are a matter of
443  external protocol, and shouldn't shift around as things are edited.
444 
445  We access the control/special registers via pseudoregisters, to
446  enforce read-only portions that some registers have.
447 
448  We access the coprocessor general purpose and control registers via
449  pseudoregisters, to make sure they appear in the proper order in
450  the 'info all-registers' command (which uses the register number
451  ordering), and also to allow them to be renamed and resized
452  depending on the me_module in use.
453 
454  The MeP allows coprocessor general-purpose registers to be either
455  32 or 64 bits long, depending on the configuration. Since we don't
456  want the format of the 'g' packet to vary from one core to another,
457  the raw coprocessor GPRs are always 64 bits. GDB doesn't allow the
458  types of registers to change (see the implementation of
459  register_type), so we have four banks of pseudoregisters for the
460  coprocessor gprs --- 32-bit vs. 64-bit, and integer
461  vs. floating-point --- and we show or hide them depending on the
462  configuration. */
463 enum
464 {
466 
483  MEP_TP_REGNUM = MEP_R13_REGNUM, /* (r13) Tiny data pointer */
485  MEP_GP_REGNUM = MEP_R14_REGNUM, /* (r14) Global pointer */
487  MEP_SP_REGNUM = MEP_R15_REGNUM, /* (r15) Stack pointer */
489 
490  /* The raw control registers. These are the values as received via
491  the remote protocol, directly from the target; we only let user
492  code touch the via the pseudoregisters, which enforce read-only
493  bits. */
495  MEP_RAW_PC_REGNUM = 16, /* Program counter */
496  MEP_RAW_LP_REGNUM = 17, /* Link pointer */
497  MEP_RAW_SAR_REGNUM = 18, /* Raw shift amount */
498  MEP_RAW_CSR3_REGNUM = 19, /* csr3: reserved */
499  MEP_RAW_RPB_REGNUM = 20, /* Raw repeat begin address */
500  MEP_RAW_RPE_REGNUM = 21, /* Repeat end address */
501  MEP_RAW_RPC_REGNUM = 22, /* Repeat count */
502  MEP_RAW_HI_REGNUM = 23, /* Upper 32 bits of result of 64 bit mult/div */
503  MEP_RAW_LO_REGNUM = 24, /* Lower 32 bits of result of 64 bit mult/div */
504  MEP_RAW_CSR9_REGNUM = 25, /* csr3: reserved */
505  MEP_RAW_CSR10_REGNUM = 26, /* csr3: reserved */
506  MEP_RAW_CSR11_REGNUM = 27, /* csr3: reserved */
507  MEP_RAW_MB0_REGNUM = 28, /* Raw modulo begin address 0 */
508  MEP_RAW_ME0_REGNUM = 29, /* Raw modulo end address 0 */
509  MEP_RAW_MB1_REGNUM = 30, /* Raw modulo begin address 1 */
510  MEP_RAW_ME1_REGNUM = 31, /* Raw modulo end address 1 */
511  MEP_RAW_PSW_REGNUM = 32, /* Raw program status word */
512  MEP_RAW_ID_REGNUM = 33, /* Raw processor ID/revision */
513  MEP_RAW_TMP_REGNUM = 34, /* Temporary */
514  MEP_RAW_EPC_REGNUM = 35, /* Exception program counter */
515  MEP_RAW_EXC_REGNUM = 36, /* Raw exception cause */
516  MEP_RAW_CFG_REGNUM = 37, /* Raw processor configuration*/
517  MEP_RAW_CSR22_REGNUM = 38, /* csr3: reserved */
518  MEP_RAW_NPC_REGNUM = 39, /* Nonmaskable interrupt PC */
519  MEP_RAW_DBG_REGNUM = 40, /* Raw debug */
520  MEP_RAW_DEPC_REGNUM = 41, /* Debug exception PC */
521  MEP_RAW_OPT_REGNUM = 42, /* Raw options */
522  MEP_RAW_RCFG_REGNUM = 43, /* Raw local ram config */
523  MEP_RAW_CCFG_REGNUM = 44, /* Raw cache config */
524  MEP_RAW_CSR29_REGNUM = 45, /* csr3: reserved */
525  MEP_RAW_CSR30_REGNUM = 46, /* csr3: reserved */
526  MEP_RAW_CSR31_REGNUM = 47, /* csr3: reserved */
528 
529  /* The raw coprocessor general-purpose registers. These are all 64
530  bits wide. */
533 
536 
537  /* The module number register. This is the index of the me_module
538  of which the current target is an instance. (This is not a real
539  MeP-specified register; it's provided by SID.) */
541 
543 
545 
546  /* Pseudoregisters. See mep_pseudo_register_read and
547  mep_pseudo_register_write. */
549 
550  /* We have a pseudoregister for every control/special register, to
551  implement registers with read-only bits. */
553  MEP_PC_REGNUM = MEP_FIRST_CSR_REGNUM, /* Program counter */
554  MEP_LP_REGNUM, /* Link pointer */
555  MEP_SAR_REGNUM, /* shift amount */
556  MEP_CSR3_REGNUM, /* csr3: reserved */
557  MEP_RPB_REGNUM, /* repeat begin address */
558  MEP_RPE_REGNUM, /* Repeat end address */
559  MEP_RPC_REGNUM, /* Repeat count */
560  MEP_HI_REGNUM, /* Upper 32 bits of the result of 64 bit mult/div */
561  MEP_LO_REGNUM, /* Lower 32 bits of the result of 64 bit mult/div */
562  MEP_CSR9_REGNUM, /* csr3: reserved */
563  MEP_CSR10_REGNUM, /* csr3: reserved */
564  MEP_CSR11_REGNUM, /* csr3: reserved */
565  MEP_MB0_REGNUM, /* modulo begin address 0 */
566  MEP_ME0_REGNUM, /* modulo end address 0 */
567  MEP_MB1_REGNUM, /* modulo begin address 1 */
568  MEP_ME1_REGNUM, /* modulo end address 1 */
569  MEP_PSW_REGNUM, /* program status word */
570  MEP_ID_REGNUM, /* processor ID/revision */
571  MEP_TMP_REGNUM, /* Temporary */
572  MEP_EPC_REGNUM, /* Exception program counter */
573  MEP_EXC_REGNUM, /* exception cause */
574  MEP_CFG_REGNUM, /* processor configuration*/
575  MEP_CSR22_REGNUM, /* csr3: reserved */
576  MEP_NPC_REGNUM, /* Nonmaskable interrupt PC */
577  MEP_DBG_REGNUM, /* debug */
578  MEP_DEPC_REGNUM, /* Debug exception PC */
579  MEP_OPT_REGNUM, /* options */
580  MEP_RCFG_REGNUM, /* local ram config */
581  MEP_CCFG_REGNUM, /* cache config */
582  MEP_CSR29_REGNUM, /* csr3: reserved */
583  MEP_CSR30_REGNUM, /* csr3: reserved */
584  MEP_CSR31_REGNUM, /* csr3: reserved */
586 
587  /* The 32-bit integer view of the coprocessor GPR's. */
590 
591  /* The 32-bit floating-point view of the coprocessor GPR's. */
594 
595  /* The 64-bit integer view of the coprocessor GPR's. */
598 
599  /* The 64-bit floating-point view of the coprocessor GPR's. */
602 
605 
607 
609 
611 };
612 
613 
614 #define IN_SET(set, n) \
615  (MEP_FIRST_ ## set ## _REGNUM <= (n) && (n) <= MEP_LAST_ ## set ## _REGNUM)
616 
617 #define IS_GPR_REGNUM(n) (IN_SET (GPR, (n)))
618 #define IS_RAW_CSR_REGNUM(n) (IN_SET (RAW_CSR, (n)))
619 #define IS_RAW_CR_REGNUM(n) (IN_SET (RAW_CR, (n)))
620 #define IS_RAW_CCR_REGNUM(n) (IN_SET (RAW_CCR, (n)))
621 
622 #define IS_CSR_REGNUM(n) (IN_SET (CSR, (n)))
623 #define IS_CR32_REGNUM(n) (IN_SET (CR32, (n)))
624 #define IS_FP_CR32_REGNUM(n) (IN_SET (FP_CR32, (n)))
625 #define IS_CR64_REGNUM(n) (IN_SET (CR64, (n)))
626 #define IS_FP_CR64_REGNUM(n) (IN_SET (FP_CR64, (n)))
627 #define IS_CR_REGNUM(n) (IS_CR32_REGNUM (n) || IS_FP_CR32_REGNUM (n) \
628  || IS_CR64_REGNUM (n) || IS_FP_CR64_REGNUM (n))
629 #define IS_CCR_REGNUM(n) (IN_SET (CCR, (n)))
630 
631 #define IS_RAW_REGNUM(n) (IN_SET (RAW, (n)))
632 #define IS_PSEUDO_REGNUM(n) (IN_SET (PSEUDO, (n)))
633 
634 #define NUM_REGS_IN_SET(set) \
635  (MEP_LAST_ ## set ## _REGNUM - MEP_FIRST_ ## set ## _REGNUM + 1)
636 
637 #define MEP_GPR_SIZE (4) /* Size of a MeP general-purpose register. */
638 #define MEP_PSW_SIZE (4) /* Size of the PSW register. */
639 #define MEP_LP_SIZE (4) /* Size of the LP register. */
640 
641 
642 /* Many of the control/special registers contain bits that cannot be
643  written to; some are entirely read-only. So we present them all as
644  pseudoregisters.
645 
646  The following table describes the special properties of each CSR. */
648 {
649  /* The number of this CSR's raw register. */
650  int raw;
651 
652  /* The number of this CSR's pseudoregister. */
653  int pseudo;
654 
655  /* A mask of the bits that are writeable: if a bit is set here, then
656  it can be modified; if the bit is clear, then it cannot. */
658 };
659 
660 
661 /* mep_csr_registers[i] describes the i'th CSR.
662  We just list the register numbers here explicitly to help catch
663  typos. */
664 #define CSR(name) MEP_RAW_ ## name ## _REGNUM, MEP_ ## name ## _REGNUM
665 struct mep_csr_register mep_csr_registers[] = {
666  { CSR(PC), 0xffffffff }, /* manual says r/o, but we can write it */
667  { CSR(LP), 0xffffffff },
668  { CSR(SAR), 0x0000003f },
669  { CSR(CSR3), 0xffffffff },
670  { CSR(RPB), 0xfffffffe },
671  { CSR(RPE), 0xffffffff },
672  { CSR(RPC), 0xffffffff },
673  { CSR(HI), 0xffffffff },
674  { CSR(LO), 0xffffffff },
675  { CSR(CSR9), 0xffffffff },
676  { CSR(CSR10), 0xffffffff },
677  { CSR(CSR11), 0xffffffff },
678  { CSR(MB0), 0x0000ffff },
679  { CSR(ME0), 0x0000ffff },
680  { CSR(MB1), 0x0000ffff },
681  { CSR(ME1), 0x0000ffff },
682  { CSR(PSW), 0x000003ff },
683  { CSR(ID), 0x00000000 },
684  { CSR(TMP), 0xffffffff },
685  { CSR(EPC), 0xffffffff },
686  { CSR(EXC), 0x000030f0 },
687  { CSR(CFG), 0x00c0001b },
688  { CSR(CSR22), 0xffffffff },
689  { CSR(NPC), 0xffffffff },
690  { CSR(DBG), 0x00000580 },
691  { CSR(DEPC), 0xffffffff },
692  { CSR(OPT), 0x00000000 },
693  { CSR(RCFG), 0x00000000 },
694  { CSR(CCFG), 0x00000000 },
695  { CSR(CSR29), 0xffffffff },
696  { CSR(CSR30), 0xffffffff },
697  { CSR(CSR31), 0xffffffff },
698 };
699 
700 
701 /* If R is the number of a raw register, then mep_raw_to_pseudo[R] is
702  the number of the corresponding pseudoregister. Otherwise,
703  mep_raw_to_pseudo[R] == R. */
704 static int mep_raw_to_pseudo[MEP_NUM_REGS];
705 
706 /* If R is the number of a pseudoregister, then mep_pseudo_to_raw[R]
707  is the number of the underlying raw register. Otherwise
708  mep_pseudo_to_raw[R] == R. */
709 static int mep_pseudo_to_raw[MEP_NUM_REGS];
710 
711 static void
713 {
714  int i;
715 
716  /* Verify that mep_csr_registers covers all the CSRs, in order. */
717  gdb_assert (ARRAY_SIZE (mep_csr_registers) == NUM_REGS_IN_SET (CSR));
718  gdb_assert (ARRAY_SIZE (mep_csr_registers) == NUM_REGS_IN_SET (RAW_CSR));
719 
720  /* Verify that the raw and pseudo ranges have matching sizes. */
722  gdb_assert (NUM_REGS_IN_SET (RAW_CR) == NUM_REGS_IN_SET (CR32));
723  gdb_assert (NUM_REGS_IN_SET (RAW_CR) == NUM_REGS_IN_SET (CR64));
724  gdb_assert (NUM_REGS_IN_SET (RAW_CCR) == NUM_REGS_IN_SET (CCR));
725 
726  for (i = 0; i < ARRAY_SIZE (mep_csr_registers); i++)
727  {
728  struct mep_csr_register *r = &mep_csr_registers[i];
729 
732  }
733 
734  /* Set up the initial raw<->pseudo mappings. */
735  for (i = 0; i < MEP_NUM_REGS; i++)
736  {
737  mep_raw_to_pseudo[i] = i;
738  mep_pseudo_to_raw[i] = i;
739  }
740 
741  /* Add the CSR raw<->pseudo mappings. */
742  for (i = 0; i < ARRAY_SIZE (mep_csr_registers); i++)
743  {
744  struct mep_csr_register *r = &mep_csr_registers[i];
745 
746  mep_raw_to_pseudo[r->raw] = r->pseudo;
747  mep_pseudo_to_raw[r->pseudo] = r->raw;
748  }
749 
750  /* Add the CR raw<->pseudo mappings. */
751  for (i = 0; i < NUM_REGS_IN_SET (RAW_CR); i++)
752  {
753  int raw = MEP_FIRST_RAW_CR_REGNUM + i;
754  int pseudo32 = MEP_FIRST_CR32_REGNUM + i;
755  int pseudofp32 = MEP_FIRST_FP_CR32_REGNUM + i;
756  int pseudo64 = MEP_FIRST_CR64_REGNUM + i;
757  int pseudofp64 = MEP_FIRST_FP_CR64_REGNUM + i;
758 
759  /* Truly, the raw->pseudo mapping depends on the current module.
760  But we use the raw->pseudo mapping when we read the debugging
761  info; at that point, we don't know what module we'll actually
762  be running yet. So, we always supply the 64-bit register
763  numbers; GDB knows how to pick a smaller value out of a
764  larger register properly. */
765  mep_raw_to_pseudo[raw] = pseudo64;
766  mep_pseudo_to_raw[pseudo32] = raw;
767  mep_pseudo_to_raw[pseudofp32] = raw;
768  mep_pseudo_to_raw[pseudo64] = raw;
769  mep_pseudo_to_raw[pseudofp64] = raw;
770  }
771 
772  /* Add the CCR raw<->pseudo mappings. */
773  for (i = 0; i < NUM_REGS_IN_SET (CCR); i++)
774  {
775  int raw = MEP_FIRST_RAW_CCR_REGNUM + i;
776  int pseudo = MEP_FIRST_CCR_REGNUM + i;
777  mep_raw_to_pseudo[raw] = pseudo;
778  mep_pseudo_to_raw[pseudo] = raw;
779  }
780 }
781 
782 
783 static int
784 mep_debug_reg_to_regnum (struct gdbarch *gdbarch, int debug_reg)
785 {
786  /* The debug info uses the raw register numbers. */
787  return mep_raw_to_pseudo[debug_reg];
788 }
789 
790 
791 /* Return the size, in bits, of the coprocessor pseudoregister
792  numbered PSEUDO. */
793 static int
794 mep_pseudo_cr_size (int pseudo)
795 {
796  if (IS_CR32_REGNUM (pseudo)
797  || IS_FP_CR32_REGNUM (pseudo))
798  return 32;
799  else if (IS_CR64_REGNUM (pseudo)
800  || IS_FP_CR64_REGNUM (pseudo))
801  return 64;
802  else
803  gdb_assert_not_reached ("unexpected coprocessor pseudo register");
804 }
805 
806 
807 /* If the coprocessor pseudoregister numbered PSEUDO is a
808  floating-point register, return non-zero; if it is an integer
809  register, return zero. */
810 static int
812 {
813  return (IS_FP_CR32_REGNUM (pseudo)
814  || IS_FP_CR64_REGNUM (pseudo));
815 }
816 
817 
818 /* Given a coprocessor GPR pseudoregister number, return its index
819  within that register bank. */
820 static int
822 {
823  if (IS_CR32_REGNUM (pseudo))
824  return pseudo - MEP_FIRST_CR32_REGNUM;
825  else if (IS_FP_CR32_REGNUM (pseudo))
826  return pseudo - MEP_FIRST_FP_CR32_REGNUM;
827  else if (IS_CR64_REGNUM (pseudo))
828  return pseudo - MEP_FIRST_CR64_REGNUM;
829  else if (IS_FP_CR64_REGNUM (pseudo))
830  return pseudo - MEP_FIRST_FP_CR64_REGNUM;
831  else
832  gdb_assert_not_reached ("unexpected coprocessor pseudo register");
833 }
834 
835 
836 /* Return the me_module index describing the current target.
837 
838  If the current target has registers (e.g., simulator, remote
839  target), then this uses the value of the 'module' register, raw
840  register MEP_MODULE_REGNUM. Otherwise, this retrieves the value
841  from the ELF header's e_flags field of the current executable
842  file. */
843 static CONFIG_ATTR
845 {
847  {
848  ULONGEST regval;
850  MEP_MODULE_REGNUM, &regval);
851  return regval;
852  }
853  else
855 }
856 
857 
858 /* Return the set of options for the current target, in the form that
859  the OPT register would use.
860 
861  If the current target has registers (e.g., simulator, remote
862  target), then this is the actual value of the OPT register. If the
863  current target does not have registers (e.g., an executable file),
864  then use the 'module_opt' field we computed when we build the
865  gdbarch object for this module. */
866 static unsigned int
868 {
870  {
871  ULONGEST regval;
873  MEP_OPT_REGNUM, &regval);
874  return regval;
875  }
876  else
877  return me_module_opt (current_me_module ());
878 }
879 
880 
881 /* Return the width of the current me_module's coprocessor data bus,
882  in bits. This is either 32 or 64. */
883 static int
885 {
887 }
888 
889 
890 /* Return the keyword table of coprocessor general-purpose register
891  names appropriate for the me_module we're dealing with. */
892 static CGEN_KEYWORD *
894 {
895  const CGEN_HW_ENTRY *hw
896  = me_module_register_set (current_me_module (), "h-cr-", HW_H_CR);
897 
898  return register_set_keyword_table (hw);
899 }
900 
901 
902 /* Return non-zero if the coprocessor general-purpose registers are
903  floating-point values, zero otherwise. */
904 static int
906 {
907  const CGEN_HW_ENTRY *hw
908  = me_module_register_set (current_me_module (), "h-cr-", HW_H_CR);
909 
910  return CGEN_ATTR_CGEN_HW_IS_FLOAT_VALUE (CGEN_HW_ATTRS (hw));
911 }
912 
913 
914 /* Return the keyword table of coprocessor control register names
915  appropriate for the me_module we're dealing with. */
916 static CGEN_KEYWORD *
918 {
919  const CGEN_HW_ENTRY *hw
920  = me_module_register_set (current_me_module (), "h-ccr-", HW_H_CCR);
921 
922  return register_set_keyword_table (hw);
923 }
924 
925 
926 static const char *
927 mep_register_name (struct gdbarch *gdbarch, int regnr)
928 {
929  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
930 
931  /* General-purpose registers. */
932  static const char *gpr_names[] = {
933  "r0", "r1", "r2", "r3", /* 0 */
934  "r4", "r5", "r6", "r7", /* 4 */
935  "fp", "r9", "r10", "r11", /* 8 */
936  "r12", "tp", "gp", "sp" /* 12 */
937  };
938 
939  /* Special-purpose registers. */
940  static const char *csr_names[] = {
941  "pc", "lp", "sar", "", /* 0 csr3: reserved */
942  "rpb", "rpe", "rpc", "hi", /* 4 */
943  "lo", "", "", "", /* 8 csr9-csr11: reserved */
944  "mb0", "me0", "mb1", "me1", /* 12 */
945 
946  "psw", "id", "tmp", "epc", /* 16 */
947  "exc", "cfg", "", "npc", /* 20 csr22: reserved */
948  "dbg", "depc", "opt", "rcfg", /* 24 */
949  "ccfg", "", "", "" /* 28 csr29-csr31: reserved */
950  };
951 
952  if (IS_GPR_REGNUM (regnr))
953  return gpr_names[regnr - MEP_R0_REGNUM];
954  else if (IS_CSR_REGNUM (regnr))
955  {
956  /* The 'hi' and 'lo' registers are only present on processors
957  that have the 'MUL' or 'DIV' instructions enabled. */
958  if ((regnr == MEP_HI_REGNUM || regnr == MEP_LO_REGNUM)
959  && (! (current_options () & (MEP_OPT_MUL | MEP_OPT_DIV))))
960  return "";
961 
962  return csr_names[regnr - MEP_FIRST_CSR_REGNUM];
963  }
964  else if (IS_CR_REGNUM (regnr))
965  {
966  CGEN_KEYWORD *names;
967  int cr_size;
968  int cr_is_float;
969 
970  /* Does this module have a coprocessor at all? */
971  if (! (current_options () & MEP_OPT_COP))
972  return "";
973 
974  names = current_cr_names ();
975  if (! names)
976  /* This module's coprocessor has no general-purpose registers. */
977  return "";
978 
979  cr_size = current_cop_data_bus_width ();
980  if (cr_size != mep_pseudo_cr_size (regnr))
981  /* This module's coprocessor's GPR's are of a different size. */
982  return "";
983 
984  cr_is_float = current_cr_is_float ();
985  /* The extra ! operators ensure we get boolean equality, not
986  numeric equality. */
987  if (! cr_is_float != ! mep_pseudo_cr_is_float (regnr))
988  /* This module's coprocessor's GPR's are of a different type. */
989  return "";
990 
991  return register_name_from_keyword (names, mep_pseudo_cr_index (regnr));
992  }
993  else if (IS_CCR_REGNUM (regnr))
994  {
995  /* Does this module have a coprocessor at all? */
996  if (! (current_options () & MEP_OPT_COP))
997  return "";
998 
999  {
1000  CGEN_KEYWORD *names = current_ccr_names ();
1001 
1002  if (! names)
1003  /* This me_module's coprocessor has no control registers. */
1004  return "";
1005 
1006  return register_name_from_keyword (names, regnr-MEP_FIRST_CCR_REGNUM);
1007  }
1008  }
1009 
1010  /* It might be nice to give the 'module' register a name, but that
1011  would affect the output of 'info all-registers', which would
1012  disturb the test suites. So we leave it invisible. */
1013  else
1014  return NULL;
1015 }
1016 
1017 
1018 /* Custom register groups for the MeP. */
1019 static struct reggroup *mep_csr_reggroup; /* control/special */
1020 static struct reggroup *mep_cr_reggroup; /* coprocessor general-purpose */
1021 static struct reggroup *mep_ccr_reggroup; /* coprocessor control */
1022 
1023 
1024 static int
1026  struct reggroup *group)
1027 {
1028  /* Filter reserved or unused register numbers. */
1029  {
1030  const char *name = mep_register_name (gdbarch, regnum);
1031 
1032  if (! name || name[0] == '\0')
1033  return 0;
1034  }
1035 
1036  /* We could separate the GPRs and the CSRs. Toshiba has approved of
1037  the existing behavior, so we'd want to run that by them. */
1038  if (group == general_reggroup)
1039  return (IS_GPR_REGNUM (regnum)
1040  || IS_CSR_REGNUM (regnum));
1041 
1042  /* Everything is in the 'all' reggroup, except for the raw CSR's. */
1043  else if (group == all_reggroup)
1044  return (IS_GPR_REGNUM (regnum)
1045  || IS_CSR_REGNUM (regnum)
1046  || IS_CR_REGNUM (regnum)
1047  || IS_CCR_REGNUM (regnum));
1048 
1049  /* All registers should be saved and restored, except for the raw
1050  CSR's.
1051 
1052  This is probably right if the coprocessor is something like a
1053  floating-point unit, but would be wrong if the coprocessor is
1054  something that does I/O, where register accesses actually cause
1055  externally-visible actions. But I get the impression that the
1056  coprocessor isn't supposed to do things like that --- you'd use a
1057  hardware engine, perhaps. */
1058  else if (group == save_reggroup || group == restore_reggroup)
1059  return (IS_GPR_REGNUM (regnum)
1060  || IS_CSR_REGNUM (regnum)
1061  || IS_CR_REGNUM (regnum)
1062  || IS_CCR_REGNUM (regnum));
1063 
1064  else if (group == mep_csr_reggroup)
1065  return IS_CSR_REGNUM (regnum);
1066  else if (group == mep_cr_reggroup)
1067  return IS_CR_REGNUM (regnum);
1068  else if (group == mep_ccr_reggroup)
1069  return IS_CCR_REGNUM (regnum);
1070  else
1071  return 0;
1072 }
1073 
1074 
1075 static struct type *
1076 mep_register_type (struct gdbarch *gdbarch, int reg_nr)
1077 {
1078  /* Coprocessor general-purpose registers may be either 32 or 64 bits
1079  long. So for them, the raw registers are always 64 bits long (to
1080  keep the 'g' packet format fixed), and the pseudoregisters vary
1081  in length. */
1082  if (IS_RAW_CR_REGNUM (reg_nr))
1083  return builtin_type (gdbarch)->builtin_uint64;
1084 
1085  /* Since GDB doesn't allow registers to change type, we have two
1086  banks of pseudoregisters for the coprocessor general-purpose
1087  registers: one that gives a 32-bit view, and one that gives a
1088  64-bit view. We hide or show one or the other depending on the
1089  current module. */
1090  if (IS_CR_REGNUM (reg_nr))
1091  {
1092  int size = mep_pseudo_cr_size (reg_nr);
1093  if (size == 32)
1094  {
1095  if (mep_pseudo_cr_is_float (reg_nr))
1096  return builtin_type (gdbarch)->builtin_float;
1097  else
1098  return builtin_type (gdbarch)->builtin_uint32;
1099  }
1100  else if (size == 64)
1101  {
1102  if (mep_pseudo_cr_is_float (reg_nr))
1103  return builtin_type (gdbarch)->builtin_double;
1104  else
1105  return builtin_type (gdbarch)->builtin_uint64;
1106  }
1107  else
1108  gdb_assert_not_reached ("unexpected cr size");
1109  }
1110 
1111  /* All other registers are 32 bits long. */
1112  else
1113  return builtin_type (gdbarch)->builtin_uint32;
1114 }
1115 
1116 
1117 static CORE_ADDR
1119 {
1120  ULONGEST pc;
1122  return pc;
1123 }
1124 
1125 static enum register_status
1127  struct regcache *regcache,
1128  int cookednum,
1129  void *buf)
1130 {
1131  enum register_status status;
1132  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1133  /* Read the raw register into a 64-bit buffer, and then return the
1134  appropriate end of that buffer. */
1135  int rawnum = mep_pseudo_to_raw[cookednum];
1136  gdb_byte buf64[8];
1137 
1138  gdb_assert (TYPE_LENGTH (register_type (gdbarch, rawnum)) == sizeof (buf64));
1139  gdb_assert (TYPE_LENGTH (register_type (gdbarch, cookednum)) == 4);
1140  status = regcache_raw_read (regcache, rawnum, buf64);
1141  if (status == REG_VALID)
1142  {
1143  /* Slow, but legible. */
1144  store_unsigned_integer (buf, 4, byte_order,
1145  extract_unsigned_integer (buf64, 8, byte_order));
1146  }
1147  return status;
1148 }
1149 
1150 
1151 static enum register_status
1153  struct regcache *regcache,
1154  int cookednum,
1155  void *buf)
1156 {
1157  return regcache_raw_read (regcache, mep_pseudo_to_raw[cookednum], buf);
1158 }
1159 
1160 
1161 static enum register_status
1163  struct regcache *regcache,
1164  int cookednum,
1165  gdb_byte *buf)
1166 {
1167  if (IS_CSR_REGNUM (cookednum)
1168  || IS_CCR_REGNUM (cookednum))
1169  return regcache_raw_read (regcache, mep_pseudo_to_raw[cookednum], buf);
1170  else if (IS_CR32_REGNUM (cookednum)
1171  || IS_FP_CR32_REGNUM (cookednum))
1172  return mep_pseudo_cr32_read (gdbarch, regcache, cookednum, buf);
1173  else if (IS_CR64_REGNUM (cookednum)
1174  || IS_FP_CR64_REGNUM (cookednum))
1175  return mep_pseudo_cr64_read (gdbarch, regcache, cookednum, buf);
1176  else
1177  gdb_assert_not_reached ("unexpected pseudo register");
1178 }
1179 
1180 
1181 static void
1183  struct regcache *regcache,
1184  int cookednum,
1185  const void *buf)
1186 {
1187  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1188  int size = register_size (gdbarch, cookednum);
1189  struct mep_csr_register *r
1190  = &mep_csr_registers[cookednum - MEP_FIRST_CSR_REGNUM];
1191 
1192  if (r->writeable_bits == 0)
1193  /* A completely read-only register; avoid the read-modify-
1194  write cycle, and juts ignore the entire write. */
1195  ;
1196  else
1197  {
1198  /* A partially writeable register; do a read-modify-write cycle. */
1199  ULONGEST old_bits;
1200  ULONGEST new_bits;
1201  ULONGEST mixed_bits;
1202 
1203  regcache_raw_read_unsigned (regcache, r->raw, &old_bits);
1204  new_bits = extract_unsigned_integer (buf, size, byte_order);
1205  mixed_bits = ((r->writeable_bits & new_bits)
1206  | (~r->writeable_bits & old_bits));
1207  regcache_raw_write_unsigned (regcache, r->raw, mixed_bits);
1208  }
1209 }
1210 
1211 
1212 static void
1214  struct regcache *regcache,
1215  int cookednum,
1216  const void *buf)
1217 {
1218  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1219  /* Expand the 32-bit value into a 64-bit value, and write that to
1220  the pseudoregister. */
1221  int rawnum = mep_pseudo_to_raw[cookednum];
1222  gdb_byte buf64[8];
1223 
1224  gdb_assert (TYPE_LENGTH (register_type (gdbarch, rawnum)) == sizeof (buf64));
1225  gdb_assert (TYPE_LENGTH (register_type (gdbarch, cookednum)) == 4);
1226  /* Slow, but legible. */
1227  store_unsigned_integer (buf64, 8, byte_order,
1228  extract_unsigned_integer (buf, 4, byte_order));
1229  regcache_raw_write (regcache, rawnum, buf64);
1230 }
1231 
1232 
1233 static void
1235  struct regcache *regcache,
1236  int cookednum,
1237  const void *buf)
1238 {
1239  regcache_raw_write (regcache, mep_pseudo_to_raw[cookednum], buf);
1240 }
1241 
1242 
1243 static void
1245  struct regcache *regcache,
1246  int cookednum,
1247  const gdb_byte *buf)
1248 {
1249  if (IS_CSR_REGNUM (cookednum))
1250  mep_pseudo_csr_write (gdbarch, regcache, cookednum, buf);
1251  else if (IS_CR32_REGNUM (cookednum)
1252  || IS_FP_CR32_REGNUM (cookednum))
1253  mep_pseudo_cr32_write (gdbarch, regcache, cookednum, buf);
1254  else if (IS_CR64_REGNUM (cookednum)
1255  || IS_FP_CR64_REGNUM (cookednum))
1256  mep_pseudo_cr64_write (gdbarch, regcache, cookednum, buf);
1257  else if (IS_CCR_REGNUM (cookednum))
1258  regcache_raw_write (regcache, mep_pseudo_to_raw[cookednum], buf);
1259  else
1260  gdb_assert_not_reached ("unexpected pseudo register");
1261 }
1262 
1263 
1264 
1265 /* Disassembly. */
1266 
1267 /* The mep disassembler needs to know about the section in order to
1268  work correctly. */
1269 static int
1270 mep_gdb_print_insn (bfd_vma pc, disassemble_info * info)
1271 {
1272  struct obj_section * s = find_pc_section (pc);
1273 
1274  if (s)
1275  {
1276  /* The libopcodes disassembly code uses the section to find the
1277  BFD, the BFD to find the ELF header, the ELF header to find
1278  the me_module index, and the me_module index to select the
1279  right instructions to print. */
1280  info->section = s->the_bfd_section;
1281  info->arch = bfd_arch_mep;
1282 
1283  return print_insn_mep (pc, info);
1284  }
1285 
1286  return 0;
1287 }
1288 
1289 
1290 /* Prologue analysis. */
1291 
1292 
1293 /* The MeP has two classes of instructions: "core" instructions, which
1294  are pretty normal RISC chip stuff, and "coprocessor" instructions,
1295  which are mostly concerned with moving data in and out of
1296  coprocessor registers, and branching on coprocessor condition
1297  codes. There's space in the instruction set for custom coprocessor
1298  instructions, too.
1299 
1300  Instructions can be 16 or 32 bits long; the top two bits of the
1301  first byte indicate the length. The coprocessor instructions are
1302  mixed in with the core instructions, and there's no easy way to
1303  distinguish them; you have to completely decode them to tell one
1304  from the other.
1305 
1306  The MeP also supports a "VLIW" operation mode, where instructions
1307  always occur in fixed-width bundles. The bundles are either 32
1308  bits or 64 bits long, depending on a fixed configuration flag. You
1309  decode the first part of the bundle as normal; if it's a core
1310  instruction, and there's any space left in the bundle, the
1311  remainder of the bundle is a coprocessor instruction, which will
1312  execute in parallel with the core instruction. If the first part
1313  of the bundle is a coprocessor instruction, it occupies the entire
1314  bundle.
1315 
1316  So, here are all the cases:
1317 
1318  - 32-bit VLIW mode:
1319  Every bundle is four bytes long, and naturally aligned, and can hold
1320  one or two instructions:
1321  - 16-bit core instruction; 16-bit coprocessor instruction
1322  These execute in parallel.
1323  - 32-bit core instruction
1324  - 32-bit coprocessor instruction
1325 
1326  - 64-bit VLIW mode:
1327  Every bundle is eight bytes long, and naturally aligned, and can hold
1328  one or two instructions:
1329  - 16-bit core instruction; 48-bit (!) coprocessor instruction
1330  These execute in parallel.
1331  - 32-bit core instruction; 32-bit coprocessor instruction
1332  These execute in parallel.
1333  - 64-bit coprocessor instruction
1334 
1335  Now, the MeP manual doesn't define any 48- or 64-bit coprocessor
1336  instruction, so I don't really know what's up there; perhaps these
1337  are always the user-defined coprocessor instructions. */
1338 
1339 
1340 /* Return non-zero if PC is in a VLIW code section, zero
1341  otherwise. */
1342 static int
1344 {
1345  struct obj_section *s = find_pc_section (pc);
1346  if (s)
1347  return (s->the_bfd_section->flags & SEC_MEP_VLIW);
1348  return 0;
1349 }
1350 
1351 
1352 /* Set *INSN to the next core instruction at PC, and return the
1353  address of the next instruction.
1354 
1355  The MeP instruction encoding is endian-dependent. 16- and 32-bit
1356  instructions are encoded as one or two two-byte parts, and each
1357  part is byte-swapped independently. Thus:
1358 
1359  void
1360  foo (void)
1361  {
1362  asm ("movu $1, 0x123456");
1363  asm ("sb $1,0x5678($2)");
1364  asm ("clip $1, 19");
1365  }
1366 
1367  compiles to this big-endian code:
1368 
1369  0: d1 56 12 34 movu $1,0x123456
1370  4: c1 28 56 78 sb $1,22136($2)
1371  8: f1 01 10 98 clip $1,0x13
1372  c: 70 02 ret
1373 
1374  and this little-endian code:
1375 
1376  0: 56 d1 34 12 movu $1,0x123456
1377  4: 28 c1 78 56 sb $1,22136($2)
1378  8: 01 f1 98 10 clip $1,0x13
1379  c: 02 70 ret
1380 
1381  Instructions are returned in *INSN in an endian-independent form: a
1382  given instruction always appears in *INSN the same way, regardless
1383  of whether the instruction stream is big-endian or little-endian.
1384 
1385  *INSN's most significant 16 bits are the first (i.e., at lower
1386  addresses) 16 bit part of the instruction. Its least significant
1387  16 bits are the second (i.e., higher-addressed) 16 bit part of the
1388  instruction, or zero for a 16-bit instruction. Both 16-bit parts
1389  are fetched using the current endianness.
1390 
1391  So, the *INSN values for the instruction sequence above would be
1392  the following, in either endianness:
1393 
1394  0xd1561234 movu $1,0x123456
1395  0xc1285678 sb $1,22136($2)
1396  0xf1011098 clip $1,0x13
1397  0x70020000 ret
1398 
1399  (In a sense, it would be more natural to return 16-bit instructions
1400  in the least significant 16 bits of *INSN, but that would be
1401  ambiguous. In order to tell whether you're looking at a 16- or a
1402  32-bit instruction, you have to consult the major opcode field ---
1403  the most significant four bits of the instruction's first 16-bit
1404  part. But if we put 16-bit instructions at the least significant
1405  end of *INSN, then you don't know where to find the major opcode
1406  field until you know if it's a 16- or a 32-bit instruction ---
1407  which is where we started.)
1408 
1409  If PC points to a core / coprocessor bundle in a VLIW section, set
1410  *INSN to the core instruction, and return the address of the next
1411  bundle. This has the effect of skipping the bundled coprocessor
1412  instruction. That's okay, since coprocessor instructions aren't
1413  significant to prologue analysis --- for the time being,
1414  anyway. */
1415 
1416 static CORE_ADDR
1417 mep_get_insn (struct gdbarch *gdbarch, CORE_ADDR pc, unsigned long *insn)
1418 {
1419  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1420  int pc_in_vliw_section;
1421  int vliw_mode;
1422  int insn_len;
1423  gdb_byte buf[2];
1424 
1425  *insn = 0;
1426 
1427  /* Are we in a VLIW section? */
1428  pc_in_vliw_section = mep_pc_in_vliw_section (pc);
1429  if (pc_in_vliw_section)
1430  {
1431  /* Yes, find out which bundle size. */
1432  vliw_mode = current_options () & (MEP_OPT_VL32 | MEP_OPT_VL64);
1433 
1434  /* If PC is in a VLIW section, but the current core doesn't say
1435  that it supports either VLIW mode, then we don't have enough
1436  information to parse the instruction stream it contains.
1437  Since the "undifferentiated" standard core doesn't have
1438  either VLIW mode bit set, this could happen.
1439 
1440  But it shouldn't be an error to (say) set a breakpoint in a
1441  VLIW section, if you know you'll never reach it. (Perhaps
1442  you have a script that sets a bunch of standard breakpoints.)
1443 
1444  So we'll just return zero here, and hope for the best. */
1445  if (! (vliw_mode & (MEP_OPT_VL32 | MEP_OPT_VL64)))
1446  return 0;
1447 
1448  /* If both VL32 and VL64 are set, that's bogus, too. */
1449  if (vliw_mode == (MEP_OPT_VL32 | MEP_OPT_VL64))
1450  return 0;
1451  }
1452  else
1453  vliw_mode = 0;
1454 
1455  read_memory (pc, buf, sizeof (buf));
1456  *insn = extract_unsigned_integer (buf, 2, byte_order) << 16;
1457 
1458  /* The major opcode --- the top four bits of the first 16-bit
1459  part --- indicates whether this instruction is 16 or 32 bits
1460  long. All 32-bit instructions have a major opcode whose top
1461  two bits are 11; all the rest are 16-bit instructions. */
1462  if ((*insn & 0xc0000000) == 0xc0000000)
1463  {
1464  /* Fetch the second 16-bit part of the instruction. */
1465  read_memory (pc + 2, buf, sizeof (buf));
1466  *insn = *insn | extract_unsigned_integer (buf, 2, byte_order);
1467  }
1468 
1469  /* If we're in VLIW code, then the VLIW width determines the address
1470  of the next instruction. */
1471  if (vliw_mode)
1472  {
1473  /* In 32-bit VLIW code, all bundles are 32 bits long. We ignore the
1474  coprocessor half of a core / copro bundle. */
1475  if (vliw_mode == MEP_OPT_VL32)
1476  insn_len = 4;
1477 
1478  /* In 64-bit VLIW code, all bundles are 64 bits long. We ignore the
1479  coprocessor half of a core / copro bundle. */
1480  else if (vliw_mode == MEP_OPT_VL64)
1481  insn_len = 8;
1482 
1483  /* We'd better be in either core, 32-bit VLIW, or 64-bit VLIW mode. */
1484  else
1485  gdb_assert_not_reached ("unexpected vliw mode");
1486  }
1487 
1488  /* Otherwise, the top two bits of the major opcode are (again) what
1489  we need to check. */
1490  else if ((*insn & 0xc0000000) == 0xc0000000)
1491  insn_len = 4;
1492  else
1493  insn_len = 2;
1494 
1495  return pc + insn_len;
1496 }
1497 
1498 
1499 /* Sign-extend the LEN-bit value N. */
1500 #define SEXT(n, len) ((((int) (n)) ^ (1 << ((len) - 1))) - (1 << ((len) - 1)))
1501 
1502 /* Return the LEN-bit field at POS from I. */
1503 #define FIELD(i, pos, len) (((i) >> (pos)) & ((1 << (len)) - 1))
1504 
1505 /* Like FIELD, but sign-extend the field's value. */
1506 #define SFIELD(i, pos, len) (SEXT (FIELD ((i), (pos), (len)), (len)))
1507 
1508 
1509 /* Macros for decoding instructions.
1510 
1511  Remember that 16-bit instructions are placed in bits 16..31 of i,
1512  not at the least significant end; this means that the major opcode
1513  field is always in the same place, regardless of the width of the
1514  instruction. As a reminder of this, we show the lower 16 bits of a
1515  16-bit instruction as xxxx_xxxx_xxxx_xxxx. */
1516 
1517 /* SB Rn,(Rm) 0000_nnnn_mmmm_1000 */
1518 /* SH Rn,(Rm) 0000_nnnn_mmmm_1001 */
1519 /* SW Rn,(Rm) 0000_nnnn_mmmm_1010 */
1520 
1521 /* SW Rn,disp16(Rm) 1100_nnnn_mmmm_1010 dddd_dddd_dddd_dddd */
1522 #define IS_SW(i) (((i) & 0xf00f0000) == 0xc00a0000)
1523 /* SB Rn,disp16(Rm) 1100_nnnn_mmmm_1000 dddd_dddd_dddd_dddd */
1524 #define IS_SB(i) (((i) & 0xf00f0000) == 0xc0080000)
1525 /* SH Rn,disp16(Rm) 1100_nnnn_mmmm_1001 dddd_dddd_dddd_dddd */
1526 #define IS_SH(i) (((i) & 0xf00f0000) == 0xc0090000)
1527 #define SWBH_32_BASE(i) (FIELD (i, 20, 4))
1528 #define SWBH_32_SOURCE(i) (FIELD (i, 24, 4))
1529 #define SWBH_32_OFFSET(i) (SFIELD (i, 0, 16))
1530 
1531 /* SW Rn,disp7.align4(SP) 0100_nnnn_0ddd_dd10 xxxx_xxxx_xxxx_xxxx */
1532 #define IS_SW_IMMD(i) (((i) & 0xf0830000) == 0x40020000)
1533 #define SW_IMMD_SOURCE(i) (FIELD (i, 24, 4))
1534 #define SW_IMMD_OFFSET(i) (FIELD (i, 18, 5) << 2)
1535 
1536 /* SW Rn,(Rm) 0000_nnnn_mmmm_1010 xxxx_xxxx_xxxx_xxxx */
1537 #define IS_SW_REG(i) (((i) & 0xf00f0000) == 0x000a0000)
1538 #define SW_REG_SOURCE(i) (FIELD (i, 24, 4))
1539 #define SW_REG_BASE(i) (FIELD (i, 20, 4))
1540 
1541 /* ADD3 Rl,Rn,Rm 1001_nnnn_mmmm_llll xxxx_xxxx_xxxx_xxxx */
1542 #define IS_ADD3_16_REG(i) (((i) & 0xf0000000) == 0x90000000)
1543 #define ADD3_16_REG_SRC1(i) (FIELD (i, 20, 4)) /* n */
1544 #define ADD3_16_REG_SRC2(i) (FIELD (i, 24, 4)) /* m */
1545 
1546 /* ADD3 Rn,Rm,imm16 1100_nnnn_mmmm_0000 iiii_iiii_iiii_iiii */
1547 #define IS_ADD3_32(i) (((i) & 0xf00f0000) == 0xc0000000)
1548 #define ADD3_32_TARGET(i) (FIELD (i, 24, 4))
1549 #define ADD3_32_SOURCE(i) (FIELD (i, 20, 4))
1550 #define ADD3_32_OFFSET(i) (SFIELD (i, 0, 16))
1551 
1552 /* ADD3 Rn,SP,imm7.align4 0100_nnnn_0iii_ii00 xxxx_xxxx_xxxx_xxxx */
1553 #define IS_ADD3_16(i) (((i) & 0xf0830000) == 0x40000000)
1554 #define ADD3_16_TARGET(i) (FIELD (i, 24, 4))
1555 #define ADD3_16_OFFSET(i) (FIELD (i, 18, 5) << 2)
1556 
1557 /* ADD Rn,imm6 0110_nnnn_iiii_ii00 xxxx_xxxx_xxxx_xxxx */
1558 #define IS_ADD(i) (((i) & 0xf0030000) == 0x60000000)
1559 #define ADD_TARGET(i) (FIELD (i, 24, 4))
1560 #define ADD_OFFSET(i) (SFIELD (i, 18, 6))
1561 
1562 /* LDC Rn,imm5 0111_nnnn_iiii_101I xxxx_xxxx_xxxx_xxxx
1563  imm5 = I||i[7:4] */
1564 #define IS_LDC(i) (((i) & 0xf00e0000) == 0x700a0000)
1565 #define LDC_IMM(i) ((FIELD (i, 16, 1) << 4) | FIELD (i, 20, 4))
1566 #define LDC_TARGET(i) (FIELD (i, 24, 4))
1567 
1568 /* LW Rn,disp16(Rm) 1100_nnnn_mmmm_1110 dddd_dddd_dddd_dddd */
1569 #define IS_LW(i) (((i) & 0xf00f0000) == 0xc00e0000)
1570 #define LW_TARGET(i) (FIELD (i, 24, 4))
1571 #define LW_BASE(i) (FIELD (i, 20, 4))
1572 #define LW_OFFSET(i) (SFIELD (i, 0, 16))
1573 
1574 /* MOV Rn,Rm 0000_nnnn_mmmm_0000 xxxx_xxxx_xxxx_xxxx */
1575 #define IS_MOV(i) (((i) & 0xf00f0000) == 0x00000000)
1576 #define MOV_TARGET(i) (FIELD (i, 24, 4))
1577 #define MOV_SOURCE(i) (FIELD (i, 20, 4))
1578 
1579 /* BRA disp12.align2 1011_dddd_dddd_ddd0 xxxx_xxxx_xxxx_xxxx */
1580 #define IS_BRA(i) (((i) & 0xf0010000) == 0xb0000000)
1581 #define BRA_DISP(i) (SFIELD (i, 17, 11) << 1)
1582 
1583 
1584 /* This structure holds the results of a prologue analysis. */
1586 {
1587  /* The architecture for which we generated this prologue info. */
1588  struct gdbarch *gdbarch;
1589 
1590  /* The offset from the frame base to the stack pointer --- always
1591  zero or negative.
1592 
1593  Calling this a "size" is a bit misleading, but given that the
1594  stack grows downwards, using offsets for everything keeps one
1595  from going completely sign-crazy: you never change anything's
1596  sign for an ADD instruction; always change the second operand's
1597  sign for a SUB instruction; and everything takes care of
1598  itself. */
1600 
1601  /* Non-zero if this function has initialized the frame pointer from
1602  the stack pointer, zero otherwise. */
1604 
1605  /* If has_frame_ptr is non-zero, this is the offset from the frame
1606  base to where the frame pointer points. This is always zero or
1607  negative. */
1609 
1610  /* The address of the first instruction at which the frame has been
1611  set up and the arguments are where the debug info says they are
1612  --- as best as we can tell. */
1614 
1615  /* reg_offset[R] is the offset from the CFA at which register R is
1616  saved, or 1 if register R has not been saved. (Real values are
1617  always zero or negative.) */
1619 };
1620 
1621 /* Return non-zero if VALUE is an incoming argument register. */
1622 
1623 static int
1625 {
1626  return (value.kind == pvk_register
1627  && MEP_R1_REGNUM <= value.reg && value.reg <= MEP_R4_REGNUM
1628  && value.k == 0);
1629 }
1630 
1631 /* Return non-zero if a store of REG's current value VALUE to ADDR is
1632  probably spilling an argument register to its stack slot in STACK.
1633  Such instructions should be included in the prologue, if possible.
1634 
1635  The store is a spill if:
1636  - the value being stored is REG's original value;
1637  - the value has not already been stored somewhere in STACK; and
1638  - ADDR is a stack slot's address (e.g., relative to the original
1639  value of the SP). */
1640 static int
1642  struct pv_area *stack)
1643 {
1644  return (is_arg_reg (value)
1645  && pv_is_register (addr, MEP_SP_REGNUM)
1646  && ! pv_area_find_reg (stack, gdbarch, value.reg, 0));
1647 }
1648 
1649 
1650 /* Function for finding saved registers in a 'struct pv_area'; we pass
1651  this to pv_area_scan.
1652 
1653  If VALUE is a saved register, ADDR says it was saved at a constant
1654  offset from the frame base, and SIZE indicates that the whole
1655  register was saved, record its offset in RESULT_UNTYPED. */
1656 static void
1657 check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size, pv_t value)
1658 {
1659  struct mep_prologue *result = (struct mep_prologue *) result_untyped;
1660 
1661  if (value.kind == pvk_register
1662  && value.k == 0
1663  && pv_is_register (addr, MEP_SP_REGNUM)
1664  && size == register_size (result->gdbarch, value.reg))
1665  result->reg_offset[value.reg] = addr.k;
1666 }
1667 
1668 
1669 /* Analyze a prologue starting at START_PC, going no further than
1670  LIMIT_PC. Fill in RESULT as appropriate. */
1671 static void
1673  CORE_ADDR start_pc, CORE_ADDR limit_pc,
1674  struct mep_prologue *result)
1675 {
1676  CORE_ADDR pc;
1677  unsigned long insn;
1678  int rn;
1679  int found_lp = 0;
1681  struct pv_area *stack;
1682  struct cleanup *back_to;
1683  CORE_ADDR after_last_frame_setup_insn = start_pc;
1684 
1685  memset (result, 0, sizeof (*result));
1686  result->gdbarch = gdbarch;
1687 
1688  for (rn = 0; rn < MEP_NUM_REGS; rn++)
1689  {
1690  reg[rn] = pv_register (rn, 0);
1691  result->reg_offset[rn] = 1;
1692  }
1693 
1694  stack = make_pv_area (MEP_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1695  back_to = make_cleanup_free_pv_area (stack);
1696 
1697  pc = start_pc;
1698  while (pc < limit_pc)
1699  {
1700  CORE_ADDR next_pc;
1701  pv_t pre_insn_fp, pre_insn_sp;
1702 
1703  next_pc = mep_get_insn (gdbarch, pc, &insn);
1704 
1705  /* A zero return from mep_get_insn means that either we weren't
1706  able to read the instruction from memory, or that we don't
1707  have enough information to be able to reliably decode it. So
1708  we'll store here and hope for the best. */
1709  if (! next_pc)
1710  break;
1711 
1712  /* Note the current values of the SP and FP, so we can tell if
1713  this instruction changed them, below. */
1714  pre_insn_fp = reg[MEP_FP_REGNUM];
1715  pre_insn_sp = reg[MEP_SP_REGNUM];
1716 
1717  if (IS_ADD (insn))
1718  {
1719  int rn = ADD_TARGET (insn);
1720  CORE_ADDR imm6 = ADD_OFFSET (insn);
1721 
1722  reg[rn] = pv_add_constant (reg[rn], imm6);
1723  }
1724  else if (IS_ADD3_16 (insn))
1725  {
1726  int rn = ADD3_16_TARGET (insn);
1727  int imm7 = ADD3_16_OFFSET (insn);
1728 
1729  reg[rn] = pv_add_constant (reg[MEP_SP_REGNUM], imm7);
1730  }
1731  else if (IS_ADD3_32 (insn))
1732  {
1733  int rn = ADD3_32_TARGET (insn);
1734  int rm = ADD3_32_SOURCE (insn);
1735  int imm16 = ADD3_32_OFFSET (insn);
1736 
1737  reg[rn] = pv_add_constant (reg[rm], imm16);
1738  }
1739  else if (IS_SW_REG (insn))
1740  {
1741  int rn = SW_REG_SOURCE (insn);
1742  int rm = SW_REG_BASE (insn);
1743 
1744  /* If simulating this store would require us to forget
1745  everything we know about the stack frame in the name of
1746  accuracy, it would be better to just quit now. */
1747  if (pv_area_store_would_trash (stack, reg[rm]))
1748  break;
1749 
1750  if (is_arg_spill (gdbarch, reg[rn], reg[rm], stack))
1751  after_last_frame_setup_insn = next_pc;
1752 
1753  pv_area_store (stack, reg[rm], 4, reg[rn]);
1754  }
1755  else if (IS_SW_IMMD (insn))
1756  {
1757  int rn = SW_IMMD_SOURCE (insn);
1758  int offset = SW_IMMD_OFFSET (insn);
1759  pv_t addr = pv_add_constant (reg[MEP_SP_REGNUM], offset);
1760 
1761  /* If simulating this store would require us to forget
1762  everything we know about the stack frame in the name of
1763  accuracy, it would be better to just quit now. */
1764  if (pv_area_store_would_trash (stack, addr))
1765  break;
1766 
1767  if (is_arg_spill (gdbarch, reg[rn], addr, stack))
1768  after_last_frame_setup_insn = next_pc;
1769 
1770  pv_area_store (stack, addr, 4, reg[rn]);
1771  }
1772  else if (IS_MOV (insn))
1773  {
1774  int rn = MOV_TARGET (insn);
1775  int rm = MOV_SOURCE (insn);
1776 
1777  reg[rn] = reg[rm];
1778 
1779  if (pv_is_register (reg[rm], rm) && is_arg_reg (reg[rm]))
1780  after_last_frame_setup_insn = next_pc;
1781  }
1782  else if (IS_SB (insn) || IS_SH (insn) || IS_SW (insn))
1783  {
1784  int rn = SWBH_32_SOURCE (insn);
1785  int rm = SWBH_32_BASE (insn);
1786  int disp = SWBH_32_OFFSET (insn);
1787  int size = (IS_SB (insn) ? 1
1788  : IS_SH (insn) ? 2
1789  : (gdb_assert (IS_SW (insn)), 4));
1790  pv_t addr = pv_add_constant (reg[rm], disp);
1791 
1792  if (pv_area_store_would_trash (stack, addr))
1793  break;
1794 
1795  if (is_arg_spill (gdbarch, reg[rn], addr, stack))
1796  after_last_frame_setup_insn = next_pc;
1797 
1798  pv_area_store (stack, addr, size, reg[rn]);
1799  }
1800  else if (IS_LDC (insn))
1801  {
1802  int rn = LDC_TARGET (insn);
1803  int cr = LDC_IMM (insn) + MEP_FIRST_CSR_REGNUM;
1804 
1805  reg[rn] = reg[cr];
1806  }
1807  else if (IS_LW (insn))
1808  {
1809  int rn = LW_TARGET (insn);
1810  int rm = LW_BASE (insn);
1811  int offset = LW_OFFSET (insn);
1812  pv_t addr = pv_add_constant (reg[rm], offset);
1813 
1814  reg[rn] = pv_area_fetch (stack, addr, 4);
1815  }
1816  else if (IS_BRA (insn) && BRA_DISP (insn) > 0)
1817  {
1818  /* When a loop appears as the first statement of a function
1819  body, gcc 4.x will use a BRA instruction to branch to the
1820  loop condition checking code. This BRA instruction is
1821  marked as part of the prologue. We therefore set next_pc
1822  to this branch target and also stop the prologue scan.
1823  The instructions at and beyond the branch target should
1824  no longer be associated with the prologue.
1825 
1826  Note that we only consider forward branches here. We
1827  presume that a forward branch is being used to skip over
1828  a loop body.
1829 
1830  A backwards branch is covered by the default case below.
1831  If we were to encounter a backwards branch, that would
1832  most likely mean that we've scanned through a loop body.
1833  We definitely want to stop the prologue scan when this
1834  happens and that is precisely what is done by the default
1835  case below. */
1836  next_pc = pc + BRA_DISP (insn);
1837  after_last_frame_setup_insn = next_pc;
1838  break;
1839  }
1840  else
1841  /* We've hit some instruction we don't know how to simulate.
1842  Strictly speaking, we should set every value we're
1843  tracking to "unknown". But we'll be optimistic, assume
1844  that we have enough information already, and stop
1845  analysis here. */
1846  break;
1847 
1848  /* If this instruction changed the FP or decreased the SP (i.e.,
1849  allocated more stack space), then this may be a good place to
1850  declare the prologue finished. However, there are some
1851  exceptions:
1852 
1853  - If the instruction just changed the FP back to its original
1854  value, then that's probably a restore instruction. The
1855  prologue should definitely end before that.
1856 
1857  - If the instruction increased the value of the SP (that is,
1858  shrunk the frame), then it's probably part of a frame
1859  teardown sequence, and the prologue should end before that. */
1860 
1861  if (! pv_is_identical (reg[MEP_FP_REGNUM], pre_insn_fp))
1862  {
1863  if (! pv_is_register_k (reg[MEP_FP_REGNUM], MEP_FP_REGNUM, 0))
1864  after_last_frame_setup_insn = next_pc;
1865  }
1866  else if (! pv_is_identical (reg[MEP_SP_REGNUM], pre_insn_sp))
1867  {
1868  /* The comparison of constants looks odd, there, because .k
1869  is unsigned. All it really means is that the new value
1870  is lower than it was before the instruction. */
1871  if (pv_is_register (pre_insn_sp, MEP_SP_REGNUM)
1872  && pv_is_register (reg[MEP_SP_REGNUM], MEP_SP_REGNUM)
1873  && ((pre_insn_sp.k - reg[MEP_SP_REGNUM].k)
1874  < (reg[MEP_SP_REGNUM].k - pre_insn_sp.k)))
1875  after_last_frame_setup_insn = next_pc;
1876  }
1877 
1878  pc = next_pc;
1879  }
1880 
1881  /* Is the frame size (offset, really) a known constant? */
1882  if (pv_is_register (reg[MEP_SP_REGNUM], MEP_SP_REGNUM))
1883  result->frame_size = reg[MEP_SP_REGNUM].k;
1884 
1885  /* Was the frame pointer initialized? */
1886  if (pv_is_register (reg[MEP_FP_REGNUM], MEP_SP_REGNUM))
1887  {
1888  result->has_frame_ptr = 1;
1889  result->frame_ptr_offset = reg[MEP_FP_REGNUM].k;
1890  }
1891 
1892  /* Record where all the registers were saved. */
1893  pv_area_scan (stack, check_for_saved, (void *) result);
1894 
1895  result->prologue_end = after_last_frame_setup_insn;
1896 
1897  do_cleanups (back_to);
1898 }
1899 
1900 
1901 static CORE_ADDR
1903 {
1904  const char *name;
1905  CORE_ADDR func_addr, func_end;
1906  struct mep_prologue p;
1907 
1908  /* Try to find the extent of the function that contains PC. */
1909  if (! find_pc_partial_function (pc, &name, &func_addr, &func_end))
1910  return pc;
1911 
1912  mep_analyze_prologue (gdbarch, pc, func_end, &p);
1913  return p.prologue_end;
1914 }
1915 
1916 
1917 
1918 /* Breakpoints. */
1919 
1920 static const unsigned char *
1921 mep_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR * pcptr, int *lenptr)
1922 {
1923  static unsigned char breakpoint[] = { 0x70, 0x32 };
1924  *lenptr = sizeof (breakpoint);
1925  return breakpoint;
1926 }
1927 
1928 
1929 
1930 /* Frames and frame unwinding. */
1931 
1932 
1933 static struct mep_prologue *
1935  void **this_prologue_cache)
1936 {
1937  if (! *this_prologue_cache)
1938  {
1939  CORE_ADDR func_start, stop_addr;
1940 
1941  *this_prologue_cache
1943 
1944  func_start = get_frame_func (this_frame);
1945  stop_addr = get_frame_pc (this_frame);
1946 
1947  /* If we couldn't find any function containing the PC, then
1948  just initialize the prologue cache, but don't do anything. */
1949  if (! func_start)
1950  stop_addr = func_start;
1951 
1952  mep_analyze_prologue (get_frame_arch (this_frame),
1953  func_start, stop_addr, *this_prologue_cache);
1954  }
1955 
1956  return *this_prologue_cache;
1957 }
1958 
1959 
1960 /* Given the next frame and a prologue cache, return this frame's
1961  base. */
1962 static CORE_ADDR
1963 mep_frame_base (struct frame_info *this_frame,
1964  void **this_prologue_cache)
1965 {
1966  struct mep_prologue *p
1967  = mep_analyze_frame_prologue (this_frame, this_prologue_cache);
1968 
1969  /* In functions that use alloca, the distance between the stack
1970  pointer and the frame base varies dynamically, so we can't use
1971  the SP plus static information like prologue analysis to find the
1972  frame base. However, such functions must have a frame pointer,
1973  to be able to restore the SP on exit. So whenever we do have a
1974  frame pointer, use that to find the base. */
1975  if (p->has_frame_ptr)
1976  {
1977  CORE_ADDR fp
1979  return fp - p->frame_ptr_offset;
1980  }
1981  else
1982  {
1983  CORE_ADDR sp
1985  return sp - p->frame_size;
1986  }
1987 }
1988 
1989 
1990 static void
1991 mep_frame_this_id (struct frame_info *this_frame,
1992  void **this_prologue_cache,
1993  struct frame_id *this_id)
1994 {
1995  *this_id = frame_id_build (mep_frame_base (this_frame, this_prologue_cache),
1996  get_frame_func (this_frame));
1997 }
1998 
1999 
2000 static struct value *
2002  void **this_prologue_cache, int regnum)
2003 {
2004  struct mep_prologue *p
2005  = mep_analyze_frame_prologue (this_frame, this_prologue_cache);
2006 
2007  /* There are a number of complications in unwinding registers on the
2008  MeP, having to do with core functions calling VLIW functions and
2009  vice versa.
2010 
2011  The least significant bit of the link register, LP.LTOM, is the
2012  VLIW mode toggle bit: it's set if a core function called a VLIW
2013  function, or vice versa, and clear when the caller and callee
2014  were both in the same mode.
2015 
2016  So, if we're asked to unwind the PC, then we really want to
2017  unwind the LP and clear the least significant bit. (Real return
2018  addresses are always even.) And if we want to unwind the program
2019  status word (PSW), we need to toggle PSW.OM if LP.LTOM is set.
2020 
2021  Tweaking the register values we return in this way means that the
2022  bits in BUFFERP[] are not the same as the bits you'd find at
2023  ADDRP in the inferior, so we make sure lvalp is not_lval when we
2024  do this. */
2025  if (regnum == MEP_PC_REGNUM)
2026  {
2027  struct value *value;
2028  CORE_ADDR lp;
2029  value = mep_frame_prev_register (this_frame, this_prologue_cache,
2030  MEP_LP_REGNUM);
2031  lp = value_as_long (value);
2032  release_value (value);
2033  value_free (value);
2034 
2035  return frame_unwind_got_constant (this_frame, regnum, lp & ~1);
2036  }
2037  else
2038  {
2039  CORE_ADDR frame_base = mep_frame_base (this_frame, this_prologue_cache);
2040  struct value *value;
2041 
2042  /* Our caller's SP is our frame base. */
2043  if (regnum == MEP_SP_REGNUM)
2044  return frame_unwind_got_constant (this_frame, regnum, frame_base);
2045 
2046  /* If prologue analysis says we saved this register somewhere,
2047  return a description of the stack slot holding it. */
2048  if (p->reg_offset[regnum] != 1)
2049  value = frame_unwind_got_memory (this_frame, regnum,
2050  frame_base + p->reg_offset[regnum]);
2051 
2052  /* Otherwise, presume we haven't changed the value of this
2053  register, and get it from the next frame. */
2054  else
2055  value = frame_unwind_got_register (this_frame, regnum, regnum);
2056 
2057  /* If we need to toggle the operating mode, do so. */
2058  if (regnum == MEP_PSW_REGNUM)
2059  {
2060  CORE_ADDR psw, lp;
2061 
2062  psw = value_as_long (value);
2063  release_value (value);
2064  value_free (value);
2065 
2066  /* Get the LP's value, too. */
2067  value = get_frame_register_value (this_frame, MEP_LP_REGNUM);
2068  lp = value_as_long (value);
2069  release_value (value);
2070  value_free (value);
2071 
2072  /* If LP.LTOM is set, then toggle PSW.OM. */
2073  if (lp & 0x1)
2074  psw ^= 0x1000;
2075 
2076  return frame_unwind_got_constant (this_frame, regnum, psw);
2077  }
2078 
2079  return value;
2080  }
2081 }
2082 
2083 
2084 static const struct frame_unwind mep_frame_unwind = {
2085  NORMAL_FRAME,
2089  NULL,
2091 };
2092 
2093 
2094 /* Our general unwinding function can handle unwinding the PC. */
2095 static CORE_ADDR
2096 mep_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2097 {
2098  return frame_unwind_register_unsigned (next_frame, MEP_PC_REGNUM);
2099 }
2100 
2101 
2102 /* Our general unwinding function can handle unwinding the SP. */
2103 static CORE_ADDR
2104 mep_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2105 {
2106  return frame_unwind_register_unsigned (next_frame, MEP_SP_REGNUM);
2107 }
2108 
2109 
2110 
2111 /* Return values. */
2112 
2113 
2114 static int
2116 {
2117  return (TYPE_LENGTH (type) > MEP_GPR_SIZE);
2118 }
2119 
2120 
2121 static void
2123  struct type *type,
2124  struct regcache *regcache,
2125  gdb_byte *valbuf)
2126 {
2127  int byte_order = gdbarch_byte_order (arch);
2128 
2129  /* Values that don't occupy a full register appear at the less
2130  significant end of the value. This is the offset to where the
2131  value starts. */
2132  int offset;
2133 
2134  /* Return values > MEP_GPR_SIZE bytes are returned in memory,
2135  pointed to by R0. */
2136  gdb_assert (TYPE_LENGTH (type) <= MEP_GPR_SIZE);
2137 
2138  if (byte_order == BFD_ENDIAN_BIG)
2139  offset = MEP_GPR_SIZE - TYPE_LENGTH (type);
2140  else
2141  offset = 0;
2142 
2143  /* Return values that do fit in a single register are returned in R0. */
2145  offset, TYPE_LENGTH (type),
2146  valbuf);
2147 }
2148 
2149 
2150 static void
2152  struct type *type,
2153  struct regcache *regcache,
2154  const gdb_byte *valbuf)
2155 {
2156  int byte_order = gdbarch_byte_order (arch);
2157 
2158  /* Values that fit in a single register go in R0. */
2159  if (TYPE_LENGTH (type) <= MEP_GPR_SIZE)
2160  {
2161  /* Values that don't occupy a full register appear at the least
2162  significant end of the value. This is the offset to where the
2163  value starts. */
2164  int offset;
2165 
2166  if (byte_order == BFD_ENDIAN_BIG)
2167  offset = MEP_GPR_SIZE - TYPE_LENGTH (type);
2168  else
2169  offset = 0;
2170 
2172  offset, TYPE_LENGTH (type),
2173  valbuf);
2174  }
2175 
2176  /* Return values larger than a single register are returned in
2177  memory, pointed to by R0. Unfortunately, we can't count on R0
2178  pointing to the return buffer, so we raise an error here. */
2179  else
2180  error (_("\
2181 GDB cannot set return values larger than four bytes; the Media Processor's\n\
2182 calling conventions do not provide enough information to do this.\n\
2183 Try using the 'return' command with no argument."));
2184 }
2185 
2186 static enum return_value_convention
2187 mep_return_value (struct gdbarch *gdbarch, struct value *function,
2188  struct type *type, struct regcache *regcache,
2189  gdb_byte *readbuf, const gdb_byte *writebuf)
2190 {
2191  if (mep_use_struct_convention (type))
2192  {
2193  if (readbuf)
2194  {
2195  ULONGEST addr;
2196  /* Although the address of the struct buffer gets passed in R1, it's
2197  returned in R0. Fetch R0's value and then read the memory
2198  at that address. */
2199  regcache_raw_read_unsigned (regcache, MEP_R0_REGNUM, &addr);
2200  read_memory (addr, readbuf, TYPE_LENGTH (type));
2201  }
2202  if (writebuf)
2203  {
2204  /* Return values larger than a single register are returned in
2205  memory, pointed to by R0. Unfortunately, we can't count on R0
2206  pointing to the return buffer, so we raise an error here. */
2207  error (_("\
2208 GDB cannot set return values larger than four bytes; the Media Processor's\n\
2209 calling conventions do not provide enough information to do this.\n\
2210 Try using the 'return' command with no argument."));
2211  }
2213  }
2214 
2215  if (readbuf)
2216  mep_extract_return_value (gdbarch, type, regcache, readbuf);
2217  if (writebuf)
2218  mep_store_return_value (gdbarch, type, regcache, writebuf);
2219 
2221 }
2222 
2223 
2224 /* Inferior calls. */
2225 
2226 
2227 static CORE_ADDR
2229 {
2230  /* Require word alignment. */
2231  return sp & -4;
2232 }
2233 
2234 
2235 /* From "lang_spec2.txt":
2236 
2237  4.2 Calling conventions
2238 
2239  4.2.1 Core register conventions
2240 
2241  - Parameters should be evaluated from left to right, and they
2242  should be held in $1,$2,$3,$4 in order. The fifth parameter or
2243  after should be held in the stack. If the size is larger than 4
2244  bytes in the first four parameters, the pointer should be held in
2245  the registers instead. If the size is larger than 4 bytes in the
2246  fifth parameter or after, the pointer should be held in the stack.
2247 
2248  - Return value of a function should be held in register $0. If the
2249  size of return value is larger than 4 bytes, $1 should hold the
2250  pointer pointing memory that would hold the return value. In this
2251  case, the first parameter should be held in $2, the second one in
2252  $3, and the third one in $4, and the forth parameter or after
2253  should be held in the stack.
2254 
2255  [This doesn't say so, but arguments shorter than four bytes are
2256  passed in the least significant end of a four-byte word when
2257  they're passed on the stack.] */
2258 
2259 
2260 /* Traverse the list of ARGC arguments ARGV; for every ARGV[i] too
2261  large to fit in a register, save it on the stack, and place its
2262  address in COPY[i]. SP is the initial stack pointer; return the
2263  new stack pointer. */
2264 static CORE_ADDR
2265 push_large_arguments (CORE_ADDR sp, int argc, struct value **argv,
2266  CORE_ADDR copy[])
2267 {
2268  int i;
2269 
2270  for (i = 0; i < argc; i++)
2271  {
2272  unsigned arg_len = TYPE_LENGTH (value_type (argv[i]));
2273 
2274  if (arg_len > MEP_GPR_SIZE)
2275  {
2276  /* Reserve space for the copy, and then round the SP down, to
2277  make sure it's all aligned properly. */
2278  sp = (sp - arg_len) & -4;
2279  write_memory (sp, value_contents (argv[i]), arg_len);
2280  copy[i] = sp;
2281  }
2282  }
2283 
2284  return sp;
2285 }
2286 
2287 
2288 static CORE_ADDR
2289 mep_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2290  struct regcache *regcache, CORE_ADDR bp_addr,
2291  int argc, struct value **argv, CORE_ADDR sp,
2292  int struct_return,
2293  CORE_ADDR struct_addr)
2294 {
2295  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2296  CORE_ADDR *copy = (CORE_ADDR *) alloca (argc * sizeof (copy[0]));
2297  CORE_ADDR func_addr = find_function_addr (function, NULL);
2298  int i;
2299 
2300  /* The number of the next register available to hold an argument. */
2301  int arg_reg;
2302 
2303  /* The address of the next stack slot available to hold an argument. */
2304  CORE_ADDR arg_stack;
2305 
2306  /* The address of the end of the stack area for arguments. This is
2307  just for error checking. */
2308  CORE_ADDR arg_stack_end;
2309 
2310  sp = push_large_arguments (sp, argc, argv, copy);
2311 
2312  /* Reserve space for the stack arguments, if any. */
2313  arg_stack_end = sp;
2314  if (argc + (struct_addr ? 1 : 0) > 4)
2315  sp -= ((argc + (struct_addr ? 1 : 0)) - 4) * MEP_GPR_SIZE;
2316 
2317  arg_reg = MEP_R1_REGNUM;
2318  arg_stack = sp;
2319 
2320  /* If we're returning a structure by value, push the pointer to the
2321  buffer as the first argument. */
2322  if (struct_return)
2323  {
2324  regcache_cooked_write_unsigned (regcache, arg_reg, struct_addr);
2325  arg_reg++;
2326  }
2327 
2328  for (i = 0; i < argc; i++)
2329  {
2330  ULONGEST value;
2331 
2332  /* Arguments that fit in a GPR get expanded to fill the GPR. */
2333  if (TYPE_LENGTH (value_type (argv[i])) <= MEP_GPR_SIZE)
2334  value = extract_unsigned_integer (value_contents (argv[i]),
2335  TYPE_LENGTH (value_type (argv[i])),
2336  byte_order);
2337 
2338  /* Arguments too large to fit in a GPR get copied to the stack,
2339  and we pass a pointer to the copy. */
2340  else
2341  value = copy[i];
2342 
2343  /* We use $1 -- $4 for passing arguments, then use the stack. */
2344  if (arg_reg <= MEP_R4_REGNUM)
2345  {
2346  regcache_cooked_write_unsigned (regcache, arg_reg, value);
2347  arg_reg++;
2348  }
2349  else
2350  {
2351  gdb_byte buf[MEP_GPR_SIZE];
2352  store_unsigned_integer (buf, MEP_GPR_SIZE, byte_order, value);
2353  write_memory (arg_stack, buf, MEP_GPR_SIZE);
2354  arg_stack += MEP_GPR_SIZE;
2355  }
2356  }
2357 
2358  gdb_assert (arg_stack <= arg_stack_end);
2359 
2360  /* Set the return address. */
2361  regcache_cooked_write_unsigned (regcache, MEP_LP_REGNUM, bp_addr);
2362 
2363  /* Update the stack pointer. */
2365 
2366  return sp;
2367 }
2368 
2369 
2370 static struct frame_id
2371 mep_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2372 {
2374  return frame_id_build (sp, get_frame_pc (this_frame));
2375 }
2376 
2377 
2378 
2379 /* Initialization. */
2380 
2381 
2382 static struct gdbarch *
2383 mep_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2384 {
2385  struct gdbarch *gdbarch;
2386  struct gdbarch_tdep *tdep;
2387 
2388  /* Which me_module are we building a gdbarch object for? */
2389  CONFIG_ATTR me_module;
2390 
2391  /* If we have a BFD in hand, figure out which me_module it was built
2392  for. Otherwise, use the no-particular-me_module code. */
2393  if (info.abfd)
2394  {
2395  /* The way to get the me_module code depends on the object file
2396  format. At the moment, we only know how to handle ELF. */
2397  if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2398  me_module = elf_elfheader (info.abfd)->e_flags & EF_MEP_INDEX_MASK;
2399  else
2400  me_module = CONFIG_NONE;
2401  }
2402  else
2403  me_module = CONFIG_NONE;
2404 
2405  /* If we're setting the architecture from a file, check the
2406  endianness of the file against that of the me_module. */
2407  if (info.abfd)
2408  {
2409  /* The negations on either side make the comparison treat all
2410  non-zero (true) values as equal. */
2411  if (! bfd_big_endian (info.abfd) != ! me_module_big_endian (me_module))
2412  {
2413  const char *module_name = me_module_name (me_module);
2414  const char *module_endianness
2415  = me_module_big_endian (me_module) ? "big" : "little";
2416  const char *file_name = bfd_get_filename (info.abfd);
2417  const char *file_endianness
2418  = bfd_big_endian (info.abfd) ? "big" : "little";
2419 
2420  fputc_unfiltered ('\n', gdb_stderr);
2421  if (module_name)
2422  warning (_("the MeP module '%s' is %s-endian, but the executable\n"
2423  "%s is %s-endian."),
2424  module_name, module_endianness,
2425  file_name, file_endianness);
2426  else
2427  warning (_("the selected MeP module is %s-endian, but the "
2428  "executable\n"
2429  "%s is %s-endian."),
2430  module_endianness, file_name, file_endianness);
2431  }
2432  }
2433 
2434  /* Find a candidate among the list of architectures we've created
2435  already. info->bfd_arch_info needs to match, but we also want
2436  the right me_module: the ELF header's e_flags field needs to
2437  match as well. */
2438  for (arches = gdbarch_list_lookup_by_info (arches, &info);
2439  arches != NULL;
2440  arches = gdbarch_list_lookup_by_info (arches->next, &info))
2441  if (gdbarch_tdep (arches->gdbarch)->me_module == me_module)
2442  return arches->gdbarch;
2443 
2444  tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
2445  gdbarch = gdbarch_alloc (&info, tdep);
2446 
2447  /* Get a CGEN CPU descriptor for this architecture. */
2448  {
2449  const char *mach_name = info.bfd_arch_info->printable_name;
2450  enum cgen_endian endian = (info.byte_order == BFD_ENDIAN_BIG
2451  ? CGEN_ENDIAN_BIG
2452  : CGEN_ENDIAN_LITTLE);
2453 
2454  tdep->cpu_desc = mep_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
2455  CGEN_CPU_OPEN_ENDIAN, endian,
2456  CGEN_CPU_OPEN_END);
2457  }
2458 
2459  tdep->me_module = me_module;
2460 
2461  /* Register set. */
2462  set_gdbarch_read_pc (gdbarch, mep_read_pc);
2473 
2475  reggroup_add (gdbarch, all_reggroup);
2476  reggroup_add (gdbarch, general_reggroup);
2477  reggroup_add (gdbarch, save_reggroup);
2478  reggroup_add (gdbarch, restore_reggroup);
2479  reggroup_add (gdbarch, mep_csr_reggroup);
2480  reggroup_add (gdbarch, mep_cr_reggroup);
2481  reggroup_add (gdbarch, mep_ccr_reggroup);
2482 
2483  /* Disassembly. */
2485 
2486  /* Breakpoints. */
2488  set_gdbarch_decr_pc_after_break (gdbarch, 0);
2490 
2491  /* Frames and frame unwinding. */
2492  frame_unwind_append_unwinder (gdbarch, &mep_frame_unwind);
2496  set_gdbarch_frame_args_skip (gdbarch, 0);
2497 
2498  /* Return values. */
2500 
2501  /* Inferior function calls. */
2505 
2506  return gdbarch;
2507 }
2508 
2509 /* Provide a prototype to silence -Wmissing-prototypes. */
2511 
2512 void
2514 {
2515  mep_csr_reggroup = reggroup_new ("csr", USER_REGGROUP);
2516  mep_cr_reggroup = reggroup_new ("cr", USER_REGGROUP);
2517  mep_ccr_reggroup = reggroup_new ("ccr", USER_REGGROUP);
2518 
2519  register_gdbarch_init (bfd_arch_mep, mep_gdbarch_init);
2520 
2522 }
void reggroup_add(struct gdbarch *gdbarch, struct reggroup *group)
Definition: reggroups.c:103
struct gdbarch * target_gdbarch(void)
Definition: gdbarch.c:5143
void set_gdbarch_num_regs(struct gdbarch *gdbarch, int num_regs)
Definition: gdbarch.c:1909
void set_gdbarch_frame_align(struct gdbarch *gdbarch, gdbarch_frame_align_ftype frame_align)
Definition: gdbarch.c:2935
initialize_file_ftype _initialize_mep_tdep
ULONGEST extract_unsigned_integer(const gdb_byte *, int, enum bfd_endian)
Definition: findvar.c:84
#define target_has_registers
Definition: target.h:1710
static struct frame_id mep_dummy_id(struct gdbarch *gdbarch, struct frame_info *this_frame)
Definition: mep-tdep.c:2371
static struct gdbarch * mep_gdbarch_init(struct gdbarch_info info, struct gdbarch_list *arches)
Definition: mep-tdep.c:2383
static CORE_ADDR mep_skip_prologue(struct gdbarch *gdbarch, CORE_ADDR pc)
Definition: mep-tdep.c:1902
struct frame_id frame_id_build(CORE_ADDR stack_addr, CORE_ADDR code_addr)
Definition: frame.c:554
CONFIG_ATTR me_module
Definition: mep-tdep.c:144
#define IS_ADD3_32(i)
Definition: mep-tdep.c:1547
#define PC
#define ADD3_16_TARGET(i)
Definition: mep-tdep.c:1554
#define IS_BRA(i)
Definition: mep-tdep.c:1580
CORE_ADDR get_frame_pc(struct frame_info *frame)
Definition: frame.c:2217
#define IS_SW(i)
Definition: mep-tdep.c:1522
bfd_vma CORE_ADDR
Definition: common-types.h:41
#define ADD3_32_TARGET(i)
Definition: mep-tdep.c:1548
static CORE_ADDR push_large_arguments(CORE_ADDR sp, int argc, struct value **argv, CORE_ADDR copy[])
Definition: mep-tdep.c:2265
#define LDC_TARGET(i)
Definition: mep-tdep.c:1566
struct reggroup * reggroup_new(const char *name, enum reggroup_type type)
Definition: reggroups.c:39
pv_t pv_add_constant(pv_t v, CORE_ADDR k)
static void mep_pseudo_cr64_write(struct gdbarch *gdbarch, struct regcache *regcache, int cookednum, const void *buf)
Definition: mep-tdep.c:1234
static const char * mep_register_name(struct gdbarch *gdbarch, int regnr)
Definition: mep-tdep.c:927
LONGEST value_as_long(struct value *val)
Definition: value.c:2654
struct value * frame_unwind_got_memory(struct frame_info *frame, int regnum, CORE_ADDR addr)
Definition: frame-unwind.c:228
static int mep_pseudo_cr_is_float(int pseudo)
Definition: mep-tdep.c:811
static CORE_ADDR mep_read_pc(struct regcache *regcache)
Definition: mep-tdep.c:1118
static const CGEN_HW_ENTRY * find_hw_entry_by_prefix_and_isa(CGEN_CPU_DESC desc, const char *prefix, CGEN_BITSET *copro_isa_mask, CGEN_BITSET *generic_isa_mask)
Definition: mep-tdep.c:157
struct bfd_section * the_bfd_section
Definition: objfiles.h:121
static int is_arg_reg(pv_t value)
Definition: mep-tdep.c:1624
void warning(const char *fmt,...)
Definition: errors.c:26
#define IS_CR64_REGNUM(n)
Definition: mep-tdep.c:625
static int me_module_cop_data_bus_width(CONFIG_ATTR me_module)
Definition: mep-tdep.c:401
int reg_offset[MEP_NUM_REGS]
Definition: mep-tdep.c:1618
static int mep_gdb_print_insn(bfd_vma pc, disassemble_info *info)
Definition: mep-tdep.c:1270
void set_gdbarch_stab_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_stab_reg_to_regnum_ftype stab_reg_to_regnum)
Definition: gdbarch.c:2059
#define SWBH_32_OFFSET(i)
Definition: mep-tdep.c:1529
static CORE_ADDR mep_get_insn(struct gdbarch *gdbarch, CORE_ADDR pc, unsigned long *insn)
Definition: mep-tdep.c:1417
static unsigned int me_module_opt(CONFIG_ATTR me_module)
Definition: mep-tdep.c:392
struct cleanup * make_cleanup_free_pv_area(struct pv_area *area)
ULONGEST frame_unwind_register_unsigned(struct frame_info *frame, int regnum)
Definition: frame.c:1182
const struct builtin_type * builtin_type(struct gdbarch *gdbarch)
Definition: gdbtypes.c:4766
static CONFIG_ATTR current_me_module(void)
Definition: mep-tdep.c:844
int pv_is_register(pv_t a, int r)
static void mep_extract_return_value(struct gdbarch *arch, struct type *type, struct regcache *regcache, gdb_byte *valbuf)
Definition: mep-tdep.c:2122
return_value_convention
Definition: defs.h:206
#define CSR(name)
Definition: mep-tdep.c:664
static int reg_offset[]
Definition: i386gnu-nat.c:42
#define IS_SH(i)
Definition: mep-tdep.c:1526
void set_gdbarch_register_reggroup_p(struct gdbarch *gdbarch, gdbarch_register_reggroup_p_ftype register_reggroup_p)
Definition: gdbarch.c:3350
#define MOV_SOURCE(i)
Definition: mep-tdep.c:1577
void value_free(struct value *val)
Definition: value.c:1518
int pv_area_find_reg(struct pv_area *area, struct gdbarch *gdbarch, int reg, CORE_ADDR *offset_p)
enum prologue_value_kind kind
void regcache_cooked_write_part(struct regcache *regcache, int regnum, int offset, int len, const gdb_byte *buf)
Definition: regcache.c:1028
struct gdbarch_list * gdbarch_list_lookup_by_info(struct gdbarch_list *arches, const struct gdbarch_info *info)
Definition: gdbarch.c:4985
#define IS_MOV(i)
Definition: mep-tdep.c:1575
struct gdbarch_list * next
Definition: gdbarch.h:1543
struct reggroup *const restore_reggroup
Definition: reggroups.c:298
#define SWBH_32_BASE(i)
Definition: mep-tdep.c:1527
struct reggroup *const all_reggroup
Definition: reggroups.c:296
#define IS_RAW_CR_REGNUM(n)
Definition: mep-tdep.c:619
#define _(String)
Definition: gdb_locale.h:40
static void mep_pseudo_cr32_write(struct gdbarch *gdbarch, struct regcache *regcache, int cookednum, const void *buf)
Definition: mep-tdep.c:1213
const struct bfd_arch_info * bfd_arch_info
Definition: gdbarch.h:1549
#define ADD3_32_SOURCE(i)
Definition: mep-tdep.c:1549
static struct type * mep_register_type(struct gdbarch *gdbarch, int reg_nr)
Definition: mep-tdep.c:1076
void set_gdbarch_dwarf2_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_dwarf2_reg_to_regnum_ftype dwarf2_reg_to_regnum)
Definition: gdbarch.c:2110
#define bits(obj, st, fn)
struct gdbarch_tdep * gdbarch_tdep(struct gdbarch *gdbarch)
Definition: gdbarch.c:1402
#define SW_IMMD_SOURCE(i)
Definition: mep-tdep.c:1533
static struct reggroup * mep_csr_reggroup
Definition: mep-tdep.c:1019
void frame_unwind_append_unwinder(struct gdbarch *gdbarch, const struct frame_unwind *unwinder)
Definition: frame-unwind.c:78
struct regcache * get_current_regcache(void)
Definition: regcache.c:541
#define FRAME_OBSTACK_ZALLOC(TYPE)
Definition: frame.h:660
void store_unsigned_integer(gdb_byte *, int, enum bfd_endian, ULONGEST)
Definition: findvar.c:212
static CGEN_KEYWORD * register_set_keyword_table(const CGEN_HW_ENTRY *hw)
Definition: mep-tdep.c:291
int frame_size
Definition: mep-tdep.c:1599
struct value * frame_unwind_got_constant(struct frame_info *frame, int regnum, ULONGEST val)
Definition: frame-unwind.c:241
#define SW_REG_SOURCE(i)
Definition: mep-tdep.c:1538
int pv_is_identical(pv_t a, pv_t b)
static int mep_pc_in_vliw_section(CORE_ADDR pc)
Definition: mep-tdep.c:1343
static int mep_pseudo_cr_index(int pseudo)
Definition: mep-tdep.c:821
const char *const name
Definition: aarch64-tdep.c:68
CORE_ADDR prologue_end
Definition: mep-tdep.c:1613
struct value * get_frame_register_value(struct frame_info *frame, int regnum)
Definition: frame.c:1158
void set_gdbarch_pseudo_register_write(struct gdbarch *gdbarch, gdbarch_pseudo_register_write_ftype pseudo_register_write)
Definition: gdbarch.c:1891
static CORE_ADDR mep_push_dummy_call(struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int argc, struct value **argv, CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr)
Definition: mep-tdep.c:2289
static CORE_ADDR mep_unwind_sp(struct gdbarch *gdbarch, struct frame_info *next_frame)
Definition: mep-tdep.c:2104
void set_gdbarch_register_type(struct gdbarch *gdbarch, gdbarch_register_type_ftype register_type)
Definition: gdbarch.c:2151
const gdb_byte * value_contents(struct value *value)
Definition: value.c:1329
struct reggroup *const general_reggroup
Definition: reggroups.c:292
static void mep_frame_this_id(struct frame_info *this_frame, void **this_prologue_cache, struct frame_id *this_id)
Definition: mep-tdep.c:1991
int fputc_unfiltered(int c, struct ui_file *stream)
Definition: utils.c:2169
void initialize_file_ftype(void)
Definition: defs.h:281
int has_frame_ptr
Definition: mep-tdep.c:1603
static CGEN_KEYWORD * current_ccr_names(void)
Definition: mep-tdep.c:917
register_status
Definition: regcache.h:50
enum register_status regcache_cooked_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition: regcache.c:837
#define BRA_DISP(i)
Definition: mep-tdep.c:1581
static struct reggroup * mep_cr_reggroup
Definition: mep-tdep.c:1020
pv_t pv_area_fetch(struct pv_area *area, pv_t addr, CORE_ADDR size)
void set_gdbarch_sp_regnum(struct gdbarch *gdbarch, int sp_regnum)
Definition: gdbarch.c:1991
static char * register_name_from_keyword(CGEN_KEYWORD *keyword_table, int regnum)
Definition: mep-tdep.c:309
bfd * abfd
Definition: gdbarch.h:1557
void set_gdbarch_decr_pc_after_break(struct gdbarch *gdbarch, CORE_ADDR decr_pc_after_break)
Definition: gdbarch.c:2764
struct type * register_type(struct gdbarch *gdbarch, int regnum)
Definition: regcache.c:157
void set_gdbarch_dummy_id(struct gdbarch *gdbarch, gdbarch_dummy_id_ftype dummy_id)
Definition: gdbarch.c:2175
mach_port_t mach_port_t name mach_port_t mach_port_t name error_t int status
Definition: gnu-nat.c:1816
struct_return
Definition: arm-tdep.h:148
#define IS_SB(i)
Definition: mep-tdep.c:1524
#define gdb_assert_not_reached(message)
Definition: gdb_assert.h:56
static int current_cop_data_bus_width(void)
Definition: mep-tdep.c:884
enum bfd_endian gdbarch_byte_order(struct gdbarch *gdbarch)
Definition: gdbarch.c:1420
int pv_is_register_k(pv_t a, int r, CORE_ADDR k)
#define ADD_OFFSET(i)
Definition: mep-tdep.c:1560
Definition: gdbtypes.h:749
static const unsigned char * mep_breakpoint_from_pc(struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
Definition: mep-tdep.c:1921
int find_pc_partial_function(CORE_ADDR pc, const char **name, CORE_ADDR *address, CORE_ADDR *endaddr)
Definition: blockframe.c:321
static int current_cr_is_float(void)
Definition: mep-tdep.c:905
#define IS_LDC(i)
Definition: mep-tdep.c:1564
#define LW_BASE(i)
Definition: mep-tdep.c:1571
void set_gdbarch_unwind_pc(struct gdbarch *gdbarch, gdbarch_unwind_pc_ftype unwind_pc)
Definition: gdbarch.c:2863
#define ADD3_32_OFFSET(i)
Definition: mep-tdep.c:1550
void set_gdbarch_breakpoint_from_pc(struct gdbarch *gdbarch, gdbarch_breakpoint_from_pc_ftype breakpoint_from_pc)
Definition: gdbarch.c:2672
#define IS_CR32_REGNUM(n)
Definition: mep-tdep.c:623
struct type * builtin_uint32
Definition: gdbtypes.h:1519
int default_frame_sniffer(const struct frame_unwind *self, struct frame_info *this_frame, void **this_prologue_cache)
Definition: frame-unwind.c:170
void pv_area_store(struct pv_area *area, pv_t addr, CORE_ADDR size, pv_t value)
#define gdb_assert(expr)
Definition: gdb_assert.h:33
int pv_area_store_would_trash(struct pv_area *area, pv_t addr)
#define MOV_TARGET(i)
Definition: mep-tdep.c:1576
static int is_arg_spill(struct gdbarch *gdbarch, pv_t value, pv_t addr, struct pv_area *stack)
Definition: mep-tdep.c:1641
static enum register_status mep_pseudo_cr64_read(struct gdbarch *gdbarch, struct regcache *regcache, int cookednum, void *buf)
Definition: mep-tdep.c:1152
static struct mep_prologue * mep_analyze_frame_prologue(struct frame_info *this_frame, void **this_prologue_cache)
Definition: mep-tdep.c:1934
enum register_status regcache_raw_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition: regcache.c:690
void set_gdbarch_read_pc(struct gdbarch *gdbarch, gdbarch_read_pc_ftype read_pc)
Definition: gdbarch.c:1778
int frame_ptr_offset
Definition: mep-tdep.c:1608
#define IS_ADD(i)
Definition: mep-tdep.c:1558
int gdbarch_addr_bit(struct gdbarch *gdbarch)
Definition: gdbarch.c:1707
void set_gdbarch_unwind_sp(struct gdbarch *gdbarch, gdbarch_unwind_sp_ftype unwind_sp)
Definition: gdbarch.c:2887
struct gdbarch * gdbarch
Definition: gdbarch.h:1542
int regnum
Definition: aarch64-tdep.c:69
static const char * me_module_name(CONFIG_ATTR me_module)
Definition: mep-tdep.c:421
static int mep_debug_reg_to_regnum(struct gdbarch *gdbarch, int debug_reg)
Definition: mep-tdep.c:784
void read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition: corefile.c:244
struct obj_section * find_pc_section(CORE_ADDR pc)
Definition: objfiles.c:1337
#define IS_SW_IMMD(i)
Definition: mep-tdep.c:1532
ULONGEST get_frame_register_unsigned(struct frame_info *frame, int regnum)
Definition: frame.c:1194
void * xmalloc(YYSIZE_T)
void pv_area_scan(struct pv_area *area, void(*func)(void *closure, pv_t addr, CORE_ADDR size, pv_t value), void *closure)
void set_gdbarch_frame_args_skip(struct gdbarch *gdbarch, CORE_ADDR frame_args_skip)
Definition: gdbarch.c:2839
Definition: regdef.h:22
Definition: value.c:172
#define IS_CSR_REGNUM(n)
Definition: mep-tdep.c:622
#define IS_CCR_REGNUM(n)
Definition: mep-tdep.c:629
#define ADD_TARGET(i)
Definition: mep-tdep.c:1559
struct pv_area * make_pv_area(int base_reg, int addr_bit)
#define IS_FP_CR32_REGNUM(n)
Definition: mep-tdep.c:624
int core_addr_lessthan(CORE_ADDR lhs, CORE_ADDR rhs)
Definition: arch-utils.c:138
bfd_byte gdb_byte
Definition: common-types.h:38
static void check_for_saved(void *result_untyped, pv_t addr, CORE_ADDR size, pv_t value)
Definition: mep-tdep.c:1657
void set_gdbarch_pseudo_register_read(struct gdbarch *gdbarch, gdbarch_pseudo_register_read_ftype pseudo_register_read)
Definition: gdbarch.c:1843
struct type * builtin_double
Definition: gdbtypes.h:1491
static CORE_ADDR mep_unwind_pc(struct gdbarch *gdbarch, struct frame_info *next_frame)
Definition: mep-tdep.c:2096
static const CGEN_HW_ENTRY * find_hw_entry_by_type(CGEN_CPU_DESC desc, CGEN_HW_TYPE type)
Definition: mep-tdep.c:187
#define IS_CR_REGNUM(n)
Definition: mep-tdep.c:627
enum register_status regcache_raw_read(struct regcache *regcache, int regnum, gdb_byte *buf)
Definition: regcache.c:637
void regcache_cooked_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
Definition: regcache.c:871
struct value * frame_unwind_got_register(struct frame_info *frame, int regnum, int new_regnum)
Definition: frame-unwind.c:218
static enum return_value_convention mep_return_value(struct gdbarch *gdbarch, struct value *function, struct type *type, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf)
Definition: mep-tdep.c:2187
struct ui_file * gdb_stderr
Definition: main.c:72
CORE_ADDR find_function_addr(struct value *function, struct type **retval_type)
Definition: infcall.c:247
int offset
Definition: agent.c:65
#define MEP_GPR_SIZE
Definition: mep-tdep.c:637
static void mep_pseudo_register_write(struct gdbarch *gdbarch, struct regcache *regcache, int cookednum, const gdb_byte *buf)
Definition: mep-tdep.c:1244
void regcache_raw_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
Definition: regcache.c:723
static CORE_ADDR mep_frame_align(struct gdbarch *gdbarch, CORE_ADDR sp)
Definition: mep-tdep.c:2228
void set_gdbarch_num_pseudo_regs(struct gdbarch *gdbarch, int num_pseudo_regs)
Definition: gdbarch.c:1926
static CORE_ADDR mep_frame_base(struct frame_info *this_frame, void **this_prologue_cache)
Definition: mep-tdep.c:1963
static const CGEN_HW_ENTRY * me_module_register_set(CONFIG_ATTR me_module, const char *prefix, CGEN_HW_TYPE generic_type)
Definition: mep-tdep.c:209
static unsigned int opt_from_option_mask(unsigned int option_mask)
Definition: mep-tdep.c:356
struct gdbarch * gdbarch
Definition: mep-tdep.c:1588
#define SW_REG_BASE(i)
Definition: mep-tdep.c:1539
static int me_module_big_endian(CONFIG_ATTR me_module)
Definition: mep-tdep.c:413
#define SW_IMMD_OFFSET(i)
Definition: mep-tdep.c:1534
static unsigned int current_options(void)
Definition: mep-tdep.c:867
static enum register_status mep_pseudo_register_read(struct gdbarch *gdbarch, struct regcache *regcache, int cookednum, gdb_byte *buf)
Definition: mep-tdep.c:1162
static int mep_pseudo_cr_size(int pseudo)
Definition: mep-tdep.c:794
unsigned long long ULONGEST
Definition: common-types.h:53
enum unwind_stop_reason default_frame_unwind_stop_reason(struct frame_info *this_frame, void **this_cache)
Definition: frame-unwind.c:180
#define LW_TARGET(i)
Definition: mep-tdep.c:1570
static void mep_analyze_prologue(struct gdbarch *gdbarch, CORE_ADDR start_pc, CORE_ADDR limit_pc, struct mep_prologue *result)
Definition: mep-tdep.c:1672
void release_value(struct value *val)
Definition: value.c:1603
int register_size(struct gdbarch *gdbarch, int regnum)
Definition: regcache.c:169
struct type * value_type(const struct value *value)
Definition: value.c:1021
enum register_status regcache_cooked_read_part(struct regcache *regcache, int regnum, int offset, int len, gdb_byte *buf)
Definition: regcache.c:1017
void set_gdbarch_return_value(struct gdbarch *gdbarch, gdbarch_return_value_ftype return_value)
Definition: gdbarch.c:2556
#define IS_FP_CR64_REGNUM(n)
Definition: mep-tdep.c:626
static int mep_register_reggroup_p(struct gdbarch *gdbarch, int regnum, struct reggroup *group)
Definition: mep-tdep.c:1025
#define IS_GPR_REGNUM(n)
Definition: mep-tdep.c:617
#define LDC_IMM(i)
Definition: mep-tdep.c:1565
struct reggroup *const save_reggroup
Definition: reggroups.c:297
#define TYPE_LENGTH(thistype)
Definition: gdbtypes.h:1237
CGEN_CPU_DESC cpu_desc
Definition: mep-tdep.c:128
void set_gdbarch_push_dummy_call(struct gdbarch *gdbarch, gdbarch_push_dummy_call_ftype push_dummy_call)
Definition: gdbarch.c:2216
struct type * builtin_uint64
Definition: gdbtypes.h:1521
static void mep_init_pseudoregister_maps(void)
Definition: mep-tdep.c:712
void register_gdbarch_init(enum bfd_architecture bfd_architecture, gdbarch_init_ftype *init)
Definition: gdbarch.c:4975
#define IS_ADD3_16(i)
Definition: mep-tdep.c:1553
static int mep_use_struct_convention(struct type *type)
Definition: mep-tdep.c:2115
void write_memory(CORE_ADDR memaddr, const bfd_byte *myaddr, ssize_t len)
Definition: corefile.c:389
void set_gdbarch_skip_prologue(struct gdbarch *gdbarch, gdbarch_skip_prologue_ftype skip_prologue)
Definition: gdbarch.c:2590
#define NUM_REGS_IN_SET(set)
Definition: mep-tdep.c:634
static void mep_pseudo_csr_write(struct gdbarch *gdbarch, struct regcache *regcache, int cookednum, const void *buf)
Definition: mep-tdep.c:1182
#define IS_LW(i)
Definition: mep-tdep.c:1569
enum bfd_endian byte_order
Definition: gdbarch.h:1552
void set_gdbarch_pc_regnum(struct gdbarch *gdbarch, int pc_regnum)
Definition: gdbarch.c:2008
LONGEST writeable_bits
Definition: mep-tdep.c:657
void set_gdbarch_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype register_name)
Definition: gdbarch.c:2127
CORE_ADDR get_frame_func(struct frame_info *this_frame)
Definition: frame.c:920
static CGEN_KEYWORD * current_cr_names(void)
Definition: mep-tdep.c:893
void error(const char *fmt,...)
Definition: errors.c:38
#define LW_OFFSET(i)
Definition: mep-tdep.c:1572
pv_t pv_register(int reg, CORE_ADDR k)
size_t size
Definition: go32-nat.c:242
static struct reggroup * mep_ccr_reggroup
Definition: mep-tdep.c:1021
struct gdbarch * gdbarch_alloc(const struct gdbarch_info *info, struct gdbarch_tdep *tdep)
Definition: gdbarch.c:339
void set_gdbarch_inner_than(struct gdbarch *gdbarch, gdbarch_inner_than_ftype inner_than)
Definition: gdbarch.c:2655
struct gdbarch * get_frame_arch(struct frame_info *this_frame)
Definition: frame.c:2535
#define SWBH_32_SOURCE(i)
Definition: mep-tdep.c:1528
long long LONGEST
Definition: common-types.h:52
#define ADD3_16_OFFSET(i)
Definition: mep-tdep.c:1555
static struct value * mep_frame_prev_register(struct frame_info *this_frame, void **this_prologue_cache, int regnum)
Definition: mep-tdep.c:2001
void do_cleanups(struct cleanup *old_chain)
Definition: cleanups.c:175
static enum register_status mep_pseudo_cr32_read(struct gdbarch *gdbarch, struct regcache *regcache, int cookednum, void *buf)
Definition: mep-tdep.c:1126
void set_gdbarch_print_insn(struct gdbarch *gdbarch, gdbarch_print_insn_ftype print_insn)
Definition: gdbarch.c:3067
struct type * builtin_float
Definition: gdbtypes.h:1490
static void mep_store_return_value(struct gdbarch *arch, struct type *type, struct regcache *regcache, const gdb_byte *valbuf)
Definition: mep-tdep.c:2151
void regcache_raw_write(struct regcache *regcache, int regnum, const gdb_byte *buf)
Definition: regcache.c:885
#define IS_SW_REG(i)
Definition: mep-tdep.c:1537