GDBserver
linux-aarch64-low.c
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1 /* GNU/Linux/AArch64 specific low level interface, for the remote server for
2  GDB.
3 
4  Copyright (C) 2009-2015 Free Software Foundation, Inc.
5  Contributed by ARM Ltd.
6 
7  This file is part of GDB.
8 
9  This program is free software; you can redistribute it and/or modify
10  it under the terms of the GNU General Public License as published by
11  the Free Software Foundation; either version 3 of the License, or
12  (at your option) any later version.
13 
14  This program is distributed in the hope that it will be useful,
15  but WITHOUT ANY WARRANTY; without even the implied warranty of
16  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17  GNU General Public License for more details.
18 
19  You should have received a copy of the GNU General Public License
20  along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 
22 #include "server.h"
23 #include "linux-low.h"
24 #include "elf/common.h"
25 
26 #include <signal.h>
27 #include <sys/user.h>
28 #include <sys/ptrace.h>
29 #include <asm/ptrace.h>
30 #include <sys/uio.h>
31 
32 #include "gdb_proc_service.h"
33 
34 /* Defined in auto-generated files. */
35 void init_registers_aarch64 (void);
36 extern const struct target_desc *tdesc_aarch64;
37 
38 #ifdef HAVE_SYS_REG_H
39 #include <sys/reg.h>
40 #endif
41 
42 #define AARCH64_X_REGS_NUM 31
43 #define AARCH64_V_REGS_NUM 32
44 #define AARCH64_X0_REGNO 0
45 #define AARCH64_SP_REGNO 31
46 #define AARCH64_PC_REGNO 32
47 #define AARCH64_CPSR_REGNO 33
48 #define AARCH64_V0_REGNO 34
49 #define AARCH64_FPSR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM)
50 #define AARCH64_FPCR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 1)
51 
52 #define AARCH64_NUM_REGS (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 2)
53 
54 static int
56 {
57  /* These offsets correspond to GET/SETREGSET */
58  /* x0... */
59  0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8,
60  8*8, 9*8, 10*8, 11*8, 12*8, 13*8, 14*8, 15*8,
61  16*8, 17*8, 18*8, 19*8, 20*8, 21*8, 22*8, 23*8,
62  24*8, 25*8, 26*8, 27*8, 28*8,
63  29*8,
64  30*8, /* x30 lr */
65  31*8, /* x31 sp */
66  32*8, /* pc */
67  33*8, /* cpsr 4 bytes!*/
68 
69  /* FP register offsets correspond to GET/SETFPREGSET */
70  0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16,
71  8*16, 9*16, 10*16, 11*16, 12*16, 13*16, 14*16, 15*16,
72  16*16, 17*16, 18*16, 19*16, 20*16, 21*16, 22*16, 23*16,
73  24*16, 25*16, 26*16, 27*16, 28*16, 29*16, 30*16, 31*16
74 };
75 
76 /* Here starts the macro definitions, data structures, and code for
77  the hardware breakpoint and hardware watchpoint support. The
78  following is the abbreviations that are used frequently in the code
79  and comment:
80 
81  hw - hardware
82  bp - breakpoint
83  wp - watchpoint */
84 
85 /* Maximum number of hardware breakpoint and watchpoint registers.
86  Neither of these values may exceed the width of dr_changed_t
87  measured in bits. */
88 
89 #define AARCH64_HBP_MAX_NUM 16
90 #define AARCH64_HWP_MAX_NUM 16
91 
92 /* Alignment requirement in bytes of hardware breakpoint and
93  watchpoint address. This is the requirement for the addresses that
94  can be written to the hardware breakpoint/watchpoint value
95  registers. The kernel currently does not do any alignment on
96  addresses when receiving a writing request (via ptrace call) to
97  these debug registers, and it will reject any address that is
98  unaligned.
99  Some limited support has been provided in this gdbserver port for
100  unaligned watchpoints, so that from a gdb user point of view, an
101  unaligned watchpoint can still be set. This is achieved by
102  minimally enlarging the watched area to meet the alignment
103  requirement, and if necessary, splitting the watchpoint over
104  several hardware watchpoint registers. */
105 
106 #define AARCH64_HBP_ALIGNMENT 4
107 #define AARCH64_HWP_ALIGNMENT 8
108 
109 /* The maximum length of a memory region that can be watched by one
110  hardware watchpoint register. */
111 
112 #define AARCH64_HWP_MAX_LEN_PER_REG 8
113 
114 /* Each bit of a variable of this type is used to indicate whether a
115  hardware breakpoint or watchpoint setting has been changed since
116  the last updating. Bit N corresponds to the Nth hardware
117  breakpoint or watchpoint setting which is managed in
118  aarch64_debug_reg_state. Where N is valid between 0 and the total
119  number of the hardware breakpoint or watchpoint debug registers
120  minus 1. When the bit N is 1, it indicates the corresponding
121  breakpoint or watchpoint setting is changed, and thus the
122  corresponding hardware debug register needs to be updated via the
123  ptrace interface.
124 
125  In the per-thread arch-specific data area, we define two such
126  variables for per-thread hardware breakpoint and watchpoint
127  settings respectively.
128 
129  This type is part of the mechanism which helps reduce the number of
130  ptrace calls to the kernel, i.e. avoid asking the kernel to write
131  to the debug registers with unchanged values. */
132 
133 typedef unsigned long long dr_changed_t;
134 
135 /* Set each of the lower M bits of X to 1; assert X is wide enough. */
136 
137 #define DR_MARK_ALL_CHANGED(x, m) \
138  do \
139  { \
140  gdb_assert (sizeof ((x)) * 8 >= (m)); \
141  (x) = (((dr_changed_t)1 << (m)) - 1); \
142  } while (0)
143 
144 #define DR_MARK_N_CHANGED(x, n) \
145  do \
146  { \
147  (x) |= ((dr_changed_t)1 << (n)); \
148  } while (0)
149 
150 #define DR_CLEAR_CHANGED(x) \
151  do \
152  { \
153  (x) = 0; \
154  } while (0)
155 
156 #define DR_HAS_CHANGED(x) ((x) != 0)
157 #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
158 
159 /* Structure for managing the hardware breakpoint/watchpoint resources.
160  DR_ADDR_* stores the address, DR_CTRL_* stores the control register
161  content, and DR_REF_COUNT_* counts the numbers of references to the
162  corresponding bp/wp, by which way the limited hardware resources
163  are not wasted on duplicated bp/wp settings (though so far gdb has
164  done a good job by not sending duplicated bp/wp requests). */
165 
167 {
168  /* hardware breakpoint */
172 
173  /* hardware watchpoint */
177 };
178 
179 /* Per-process arch-specific data we want to keep. */
180 
182 {
183  /* Hardware breakpoint/watchpoint data.
184  The reason for them to be per-process rather than per-thread is
185  due to the lack of information in the gdbserver environment;
186  gdbserver is not told that whether a requested hardware
187  breakpoint/watchpoint is thread specific or not, so it has to set
188  each hw bp/wp for every thread in the current process. The
189  higher level bp/wp management in gdb will resume a thread if a hw
190  bp/wp trap is not expected for it. Since the hw bp/wp setting is
191  same for each thread, it is reasonable for the data to live here.
192  */
194 };
195 
196 /* Per-thread arch-specific data we want to keep. */
197 
199 {
200  /* When bit N is 1, it indicates the Nth hardware breakpoint or
201  watchpoint register pair needs to be updated when the thread is
202  resumed; see aarch64_linux_prepare_to_resume. */
203  dr_changed_t dr_changed_bp;
204  dr_changed_t dr_changed_wp;
205 };
206 
207 /* Number of hardware breakpoints/watchpoints the target supports.
208  They are initialized with values obtained via the ptrace calls
209  with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */
210 
213 
214 static int
216 {
217  return regno >= AARCH64_NUM_REGS;
218 }
219 
220 static int
222 {
223  return regno >= AARCH64_NUM_REGS;
224 }
225 
226 static void
228 {
229  struct user_pt_regs *regset = buf;
230  int i;
231 
232  for (i = 0; i < AARCH64_X_REGS_NUM; i++)
233  collect_register (regcache, AARCH64_X0_REGNO + i, &regset->regs[i]);
234  collect_register (regcache, AARCH64_SP_REGNO, &regset->sp);
235  collect_register (regcache, AARCH64_PC_REGNO, &regset->pc);
236  collect_register (regcache, AARCH64_CPSR_REGNO, &regset->pstate);
237 }
238 
239 static void
240 aarch64_store_gregset (struct regcache *regcache, const void *buf)
241 {
242  const struct user_pt_regs *regset = buf;
243  int i;
244 
245  for (i = 0; i < AARCH64_X_REGS_NUM; i++)
246  supply_register (regcache, AARCH64_X0_REGNO + i, &regset->regs[i]);
247  supply_register (regcache, AARCH64_SP_REGNO, &regset->sp);
248  supply_register (regcache, AARCH64_PC_REGNO, &regset->pc);
249  supply_register (regcache, AARCH64_CPSR_REGNO, &regset->pstate);
250 }
251 
252 static void
254 {
255  struct user_fpsimd_state *regset = buf;
256  int i;
257 
258  for (i = 0; i < AARCH64_V_REGS_NUM; i++)
259  collect_register (regcache, AARCH64_V0_REGNO + i, &regset->vregs[i]);
260  collect_register (regcache, AARCH64_FPSR_REGNO, &regset->fpsr);
261  collect_register (regcache, AARCH64_FPCR_REGNO, &regset->fpcr);
262 }
263 
264 static void
265 aarch64_store_fpregset (struct regcache *regcache, const void *buf)
266 {
267  const struct user_fpsimd_state *regset = buf;
268  int i;
269 
270  for (i = 0; i < AARCH64_V_REGS_NUM; i++)
271  supply_register (regcache, AARCH64_V0_REGNO + i, &regset->vregs[i]);
272  supply_register (regcache, AARCH64_FPSR_REGNO, &regset->fpsr);
273  supply_register (regcache, AARCH64_FPCR_REGNO, &regset->fpcr);
274 }
275 
276 /* Enable miscellaneous debugging output. The name is historical - it
277  was originally used to debug LinuxThreads support. */
278 extern int debug_threads;
279 
280 static CORE_ADDR
282 {
283  unsigned long pc;
284 
285  collect_register_by_name (regcache, "pc", &pc);
286  if (debug_threads)
287  debug_printf ("stop pc is %08lx\n", pc);
288  return pc;
289 }
290 
291 static void
293 {
294  unsigned long newpc = pc;
295  supply_register_by_name (regcache, "pc", &newpc);
296 }
297 
298 #define aarch64_breakpoint_len 4
299 
300 /* AArch64 BRK software debug mode instruction.
301  This instruction needs to match gdb/aarch64-tdep.c
302  (aarch64_default_breakpoint). */
303 static const gdb_byte aarch64_breakpoint[] = {0x00, 0x00, 0x20, 0xd4};
304 
305 static int
307 {
309 
310  (*the_target->read_memory) (where, (unsigned char *) &insn,
312  if (memcmp (insn, aarch64_breakpoint, aarch64_breakpoint_len) == 0)
313  return 1;
314 
315  return 0;
316 }
317 
318 /* Print the values of the cached breakpoint/watchpoint registers.
319  This is enabled via the "set debug-hw-points" monitor command. */
320 
321 static void
323  const char *func, CORE_ADDR addr,
324  int len, enum target_hw_bp_type type)
325 {
326  int i;
327 
328  fprintf (stderr, "%s", func);
329  if (addr || len)
330  fprintf (stderr, " (addr=0x%08lx, len=%d, type=%s)",
331  (unsigned long) addr, len,
332  type == hw_write ? "hw-write-watchpoint"
333  : (type == hw_read ? "hw-read-watchpoint"
334  : (type == hw_access ? "hw-access-watchpoint"
335  : (type == hw_execute ? "hw-breakpoint"
336  : "??unknown??"))));
337  fprintf (stderr, ":\n");
338 
339  fprintf (stderr, "\tBREAKPOINTs:\n");
340  for (i = 0; i < aarch64_num_bp_regs; i++)
341  fprintf (stderr, "\tBP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n",
342  i, paddress (state->dr_addr_bp[i]),
343  state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]);
344 
345  fprintf (stderr, "\tWATCHPOINTs:\n");
346  for (i = 0; i < aarch64_num_wp_regs; i++)
347  fprintf (stderr, "\tWP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n",
348  i, paddress (state->dr_addr_wp[i]),
349  state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]);
350 }
351 
352 static void
354 {
355  int i;
356 
357  for (i = 0; i < AARCH64_HBP_MAX_NUM; ++i)
358  {
359  state->dr_addr_bp[i] = 0;
360  state->dr_ctrl_bp[i] = 0;
361  state->dr_ref_count_bp[i] = 0;
362  }
363 
364  for (i = 0; i < AARCH64_HWP_MAX_NUM; ++i)
365  {
366  state->dr_addr_wp[i] = 0;
367  state->dr_ctrl_wp[i] = 0;
368  state->dr_ref_count_wp[i] = 0;
369  }
370 }
371 
372 /* ptrace expects control registers to be formatted as follows:
373 
374  31 13 5 3 1 0
375  +--------------------------------+----------+------+------+----+
376  | RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN |
377  +--------------------------------+----------+------+------+----+
378 
379  The TYPE field is ignored for breakpoints. */
380 
381 #define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1)
382 #define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff)
383 
384 /* Utility function that returns the length in bytes of a watchpoint
385  according to the content of a hardware debug control register CTRL.
386  Note that the kernel currently only supports the following Byte
387  Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
388  that for a hardware watchpoint, its valid length can only be 1
389  byte, 2 bytes, 4 bytes or 8 bytes. */
390 
391 static inline unsigned int
392 aarch64_watchpoint_length (unsigned int ctrl)
393 {
394  switch (DR_CONTROL_LENGTH (ctrl))
395  {
396  case 0x01:
397  return 1;
398  case 0x03:
399  return 2;
400  case 0x0f:
401  return 4;
402  case 0xff:
403  return 8;
404  default:
405  return 0;
406  }
407 }
408 
409 /* Given the hardware breakpoint or watchpoint type TYPE and its
410  length LEN, return the expected encoding for a hardware
411  breakpoint/watchpoint control register. */
412 
413 static unsigned int
415 {
416  unsigned int ctrl, ttype;
417 
418  /* type */
419  switch (type)
420  {
421  case hw_write:
422  ttype = 2;
423  break;
424  case hw_read:
425  ttype = 1;
426  break;
427  case hw_access:
428  ttype = 3;
429  break;
430  case hw_execute:
431  ttype = 0;
432  break;
433  default:
434  perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
435  }
436 
437  /* type */
438  ctrl = ttype << 3;
439  /* length bitmask */
440  ctrl |= ((1 << len) - 1) << 5;
441  /* enabled at el0 */
442  ctrl |= (2 << 1) | 1;
443 
444  return ctrl;
445 }
446 
447 /* Addresses to be written to the hardware breakpoint and watchpoint
448  value registers need to be aligned; the alignment is 4-byte and
449  8-type respectively. Linux kernel rejects any non-aligned address
450  it receives from the related ptrace call. Furthermore, the kernel
451  currently only supports the following Byte Address Select (BAS)
452  values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
453  watchpoint to be accepted by the kernel (via ptrace call), its
454  valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
455  Despite these limitations, the unaligned watchpoint is supported in
456  this gdbserver port.
457 
458  Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */
459 
460 static int
461 aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len)
462 {
463  unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT
465 
466  if (addr & (alignment - 1))
467  return 0;
468 
469  if (len != 8 && len != 4 && len != 2 && len != 1)
470  return 0;
471 
472  return 1;
473 }
474 
475 /* Given the (potentially unaligned) watchpoint address in ADDR and
476  length in LEN, return the aligned address and aligned length in
477  *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned
478  aligned address and length will be valid to be written to the
479  hardware watchpoint value and control registers. See the comment
480  above aarch64_point_is_aligned for the information about the
481  alignment requirement. The given watchpoint may get truncated if
482  more than one hardware register is needed to cover the watched
483  region. *NEXT_ADDR_P and *NEXT_LEN_P, if non-NULL, will return the
484  address and length of the remaining part of the watchpoint (which
485  can be processed by calling this routine again to generate another
486  aligned address and length pair.
487 
488  Essentially, unaligned watchpoint is achieved by minimally
489  enlarging the watched area to meet the alignment requirement, and
490  if necessary, splitting the watchpoint over several hardware
491  watchpoint registers. The trade-off is that there will be
492  false-positive hits for the read-type or the access-type hardware
493  watchpoints; for the write type, which is more commonly used, there
494  will be no such issues, as the higher-level breakpoint management
495  in gdb always examines the exact watched region for any content
496  change, and transparently resumes a thread from a watchpoint trap
497  if there is no change to the watched region.
498 
499  Another limitation is that because the watched region is enlarged,
500  the watchpoint fault address returned by
501  aarch64_stopped_data_address may be outside of the original watched
502  region, especially when the triggering instruction is accessing a
503  larger region. When the fault address is not within any known
504  range, watchpoints_triggered in gdb will get confused, as the
505  higher-level watchpoint management is only aware of original
506  watched regions, and will think that some unknown watchpoint has
507  been triggered. In such a case, gdb may stop without displaying
508  any detailed information.
509 
510  Once the kernel provides the full support for Byte Address Select
511  (BAS) in the hardware watchpoint control register, these
512  limitations can be largely relaxed with some further work. */
513 
514 static void
515 aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p,
516  int *aligned_len_p, CORE_ADDR *next_addr_p,
517  int *next_len_p)
518 {
519  int aligned_len;
520  unsigned int offset;
521  CORE_ADDR aligned_addr;
522  const unsigned int alignment = AARCH64_HWP_ALIGNMENT;
523  const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG;
524 
525  /* As assumed by the algorithm. */
526  gdb_assert (alignment == max_wp_len);
527 
528  if (len <= 0)
529  return;
530 
531  /* Address to be put into the hardware watchpoint value register
532  must be aligned. */
533  offset = addr & (alignment - 1);
534  aligned_addr = addr - offset;
535 
536  gdb_assert (offset >= 0 && offset < alignment);
537  gdb_assert (aligned_addr >= 0 && aligned_addr <= addr);
538  gdb_assert ((offset + len) > 0);
539 
540  if (offset + len >= max_wp_len)
541  {
542  /* Need more than one watchpoint registers; truncate it at the
543  alignment boundary. */
544  aligned_len = max_wp_len;
545  len -= (max_wp_len - offset);
546  addr += (max_wp_len - offset);
547  gdb_assert ((addr & (alignment - 1)) == 0);
548  }
549  else
550  {
551  /* Find the smallest valid length that is large enough to
552  accommodate this watchpoint. */
553  static const unsigned char
554  aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] =
555  { 1, 2, 4, 4, 8, 8, 8, 8 };
556 
557  aligned_len = aligned_len_array[offset + len - 1];
558  addr += len;
559  len = 0;
560  }
561 
562  if (aligned_addr_p != NULL)
563  *aligned_addr_p = aligned_addr;
564  if (aligned_len_p != NULL)
565  *aligned_len_p = aligned_len;
566  if (next_addr_p != NULL)
567  *next_addr_p = addr;
568  if (next_len_p != NULL)
569  *next_len_p = len;
570 }
571 
572 /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
573  registers with data from *STATE. */
574 
575 static void
577  int tid, int watchpoint)
578 {
579  int i, count;
580  struct iovec iov;
581  struct user_hwdebug_state regs;
582  const CORE_ADDR *addr;
583  const unsigned int *ctrl;
584 
585  memset (&regs, 0, sizeof (regs));
586  iov.iov_base = &regs;
587  count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs;
588  addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp;
589  ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp;
590  if (count == 0)
591  return;
592  iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs[count - 1])
593  + sizeof (regs.dbg_regs [count - 1]));
594 
595  for (i = 0; i < count; i++)
596  {
597  regs.dbg_regs[i].addr = addr[i];
598  regs.dbg_regs[i].ctrl = ctrl[i];
599  }
600 
601  if (ptrace (PTRACE_SETREGSET, tid,
602  watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK,
603  (void *) &iov))
604  error (_("Unexpected error setting hardware debug registers"));
605 }
606 
608 {
609  int pid;
611  unsigned int idx;
612 };
613 
614 /* Callback function which records the information about the change of
615  one hardware breakpoint/watchpoint setting for the thread ENTRY.
616  The information is passed in via PTR.
617  N.B. The actual updating of hardware debug registers is not
618  carried out until the moment the thread is resumed. */
619 
620 static int
622 {
623  struct thread_info *thread = (struct thread_info *) entry;
624  struct lwp_info *lwp = get_thread_lwp (thread);
625  struct aarch64_dr_update_callback_param *param_p
626  = (struct aarch64_dr_update_callback_param *) ptr;
627  int pid = param_p->pid;
628  int idx = param_p->idx;
629  int is_watchpoint = param_p->is_watchpoint;
630  struct arch_lwp_info *info = lwp->arch_private;
631  dr_changed_t *dr_changed_ptr;
632  dr_changed_t dr_changed;
633 
634  if (show_debug_regs)
635  {
636  fprintf (stderr, "debug_reg_change_callback: \n\tOn entry:\n");
637  fprintf (stderr, "\tpid%d, tid: %ld, dr_changed_bp=0x%llx, "
638  "dr_changed_wp=0x%llx\n",
639  pid, lwpid_of (thread), info->dr_changed_bp,
640  info->dr_changed_wp);
641  }
642 
643  dr_changed_ptr = is_watchpoint ? &info->dr_changed_wp
644  : &info->dr_changed_bp;
645  dr_changed = *dr_changed_ptr;
646 
647  /* Only update the threads of this process. */
648  if (pid_of (thread) == pid)
649  {
650  gdb_assert (idx >= 0
651  && (idx <= (is_watchpoint ? aarch64_num_wp_regs
652  : aarch64_num_bp_regs)));
653 
654  /* The following assertion is not right, as there can be changes
655  that have not been made to the hardware debug registers
656  before new changes overwrite the old ones. This can happen,
657  for instance, when the breakpoint/watchpoint hit one of the
658  threads and the user enters continue; then what happens is:
659  1) all breakpoints/watchpoints are removed for all threads;
660  2) a single step is carried out for the thread that was hit;
661  3) all of the points are inserted again for all threads;
662  4) all threads are resumed.
663  The 2nd step will only affect the one thread in which the
664  bp/wp was hit, which means only that one thread is resumed;
665  remember that the actual updating only happen in
666  aarch64_linux_prepare_to_resume, so other threads remain
667  stopped during the removal and insertion of bp/wp. Therefore
668  for those threads, the change of insertion of the bp/wp
669  overwrites that of the earlier removals. (The situation may
670  be different when bp/wp is steppable, or in the non-stop
671  mode.) */
672  /* gdb_assert (DR_N_HAS_CHANGED (dr_changed, idx) == 0); */
673 
674  /* The actual update is done later just before resuming the lwp,
675  we just mark that one register pair needs updating. */
676  DR_MARK_N_CHANGED (dr_changed, idx);
677  *dr_changed_ptr = dr_changed;
678 
679  /* If the lwp isn't stopped, force it to momentarily pause, so
680  we can update its debug registers. */
681  if (!lwp->stopped)
682  linux_stop_lwp (lwp);
683  }
684 
685  if (show_debug_regs)
686  {
687  fprintf (stderr, "\tOn exit:\n\tpid%d, tid: %ld, dr_changed_bp=0x%llx, "
688  "dr_changed_wp=0x%llx\n",
689  pid, lwpid_of (thread), info->dr_changed_bp,
690  info->dr_changed_wp);
691  }
692 
693  return 0;
694 }
695 
696 /* Notify each thread that their IDXth breakpoint/watchpoint register
697  pair needs to be updated. The message will be recorded in each
698  thread's arch-specific data area, the actual updating will be done
699  when the thread is resumed. */
700 
701 void
703  int is_watchpoint, unsigned int idx)
704 {
706 
707  /* Only update the threads of this process. */
708  param.pid = pid_of (current_thread);
709 
711  param.idx = idx;
712 
714 }
715 
716 
717 /* Return the pointer to the debug register state structure in the
718  current process' arch-specific data area. */
719 
720 static struct aarch64_debug_reg_state *
722 {
723  struct process_info *proc;
724 
725  proc = current_process ();
726  return &proc->priv->arch_private->debug_reg_state;
727 }
728 
729 /* Record the insertion of one breakpoint/watchpoint, as represented
730  by ADDR and CTRL, in the process' arch-specific data area *STATE. */
731 
732 static int
734  enum target_hw_bp_type type,
735  CORE_ADDR addr, int len)
736 {
737  int i, idx, num_regs, is_watchpoint;
738  unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
739  CORE_ADDR *dr_addr_p;
740 
741  /* Set up state pointers. */
742  is_watchpoint = (type != hw_execute);
743  gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
744  if (is_watchpoint)
745  {
746  num_regs = aarch64_num_wp_regs;
747  dr_addr_p = state->dr_addr_wp;
748  dr_ctrl_p = state->dr_ctrl_wp;
749  dr_ref_count = state->dr_ref_count_wp;
750  }
751  else
752  {
753  num_regs = aarch64_num_bp_regs;
754  dr_addr_p = state->dr_addr_bp;
755  dr_ctrl_p = state->dr_ctrl_bp;
756  dr_ref_count = state->dr_ref_count_bp;
757  }
758 
759  ctrl = aarch64_point_encode_ctrl_reg (type, len);
760 
761  /* Find an existing or free register in our cache. */
762  idx = -1;
763  for (i = 0; i < num_regs; ++i)
764  {
765  if ((dr_ctrl_p[i] & 1) == 0)
766  {
767  gdb_assert (dr_ref_count[i] == 0);
768  idx = i;
769  /* no break; continue hunting for an exising one. */
770  }
771  else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
772  {
773  gdb_assert (dr_ref_count[i] != 0);
774  idx = i;
775  break;
776  }
777  }
778 
779  /* No space. */
780  if (idx == -1)
781  return -1;
782 
783  /* Update our cache. */
784  if ((dr_ctrl_p[idx] & 1) == 0)
785  {
786  /* new entry */
787  dr_addr_p[idx] = addr;
788  dr_ctrl_p[idx] = ctrl;
789  dr_ref_count[idx] = 1;
790  /* Notify the change. */
791  aarch64_notify_debug_reg_change (state, is_watchpoint, idx);
792  }
793  else
794  {
795  /* existing entry */
796  dr_ref_count[idx]++;
797  }
798 
799  return 0;
800 }
801 
802 /* Record the removal of one breakpoint/watchpoint, as represented by
803  ADDR and CTRL, in the process' arch-specific data area *STATE. */
804 
805 static int
807  enum target_hw_bp_type type,
808  CORE_ADDR addr, int len)
809 {
810  int i, num_regs, is_watchpoint;
811  unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
812  CORE_ADDR *dr_addr_p;
813 
814  /* Set up state pointers. */
815  is_watchpoint = (type != hw_execute);
816  gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
817  if (is_watchpoint)
818  {
819  num_regs = aarch64_num_wp_regs;
820  dr_addr_p = state->dr_addr_wp;
821  dr_ctrl_p = state->dr_ctrl_wp;
822  dr_ref_count = state->dr_ref_count_wp;
823  }
824  else
825  {
826  num_regs = aarch64_num_bp_regs;
827  dr_addr_p = state->dr_addr_bp;
828  dr_ctrl_p = state->dr_ctrl_bp;
829  dr_ref_count = state->dr_ref_count_bp;
830  }
831 
832  ctrl = aarch64_point_encode_ctrl_reg (type, len);
833 
834  /* Find the entry that matches the ADDR and CTRL. */
835  for (i = 0; i < num_regs; ++i)
836  if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
837  {
838  gdb_assert (dr_ref_count[i] != 0);
839  break;
840  }
841 
842  /* Not found. */
843  if (i == num_regs)
844  return -1;
845 
846  /* Clear our cache. */
847  if (--dr_ref_count[i] == 0)
848  {
849  /* Clear the enable bit. */
850  ctrl &= ~1;
851  dr_addr_p[i] = 0;
852  dr_ctrl_p[i] = ctrl;
853  /* Notify the change. */
854  aarch64_notify_debug_reg_change (state, is_watchpoint, i);
855  }
856 
857  return 0;
858 }
859 
860 static int
862  int len, int is_insert)
863 {
864  struct aarch64_debug_reg_state *state;
865 
866  /* The hardware breakpoint on AArch64 should always be 4-byte
867  aligned. */
868  if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len))
869  return -1;
870 
871  state = aarch64_get_debug_reg_state ();
872 
873  if (is_insert)
874  return aarch64_dr_state_insert_one_point (state, type, addr, len);
875  else
876  return aarch64_dr_state_remove_one_point (state, type, addr, len);
877 }
878 
879 /* This is essentially the same as aarch64_handle_breakpoint, apart
880  from that it is an aligned watchpoint to be handled. */
881 
882 static int
884  CORE_ADDR addr, int len, int is_insert)
885 {
886  struct aarch64_debug_reg_state *state;
887 
888  state = aarch64_get_debug_reg_state ();
889 
890  if (is_insert)
891  return aarch64_dr_state_insert_one_point (state, type, addr, len);
892  else
893  return aarch64_dr_state_remove_one_point (state, type, addr, len);
894 }
895 
896 /* Insert/remove unaligned watchpoint by calling
897  aarch64_align_watchpoint repeatedly until the whole watched region,
898  as represented by ADDR and LEN, has been properly aligned and ready
899  to be written to one or more hardware watchpoint registers.
900  IS_INSERT indicates whether this is an insertion or a deletion.
901  Return 0 if succeed. */
902 
903 static int
905  CORE_ADDR addr, int len, int is_insert)
906 {
907  struct aarch64_debug_reg_state *state
909 
910  while (len > 0)
911  {
912  CORE_ADDR aligned_addr;
913  int aligned_len, ret;
914 
915  aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len,
916  &addr, &len);
917 
918  if (is_insert)
919  ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr,
920  aligned_len);
921  else
922  ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr,
923  aligned_len);
924 
925  if (show_debug_regs)
926  fprintf (stderr,
927  "handle_unaligned_watchpoint: is_insert: %d\n"
928  " aligned_addr: 0x%s, aligned_len: %d\n"
929  " next_addr: 0x%s, next_len: %d\n",
930  is_insert, paddress (aligned_addr), aligned_len,
931  paddress (addr), len);
932 
933  if (ret != 0)
934  return ret;
935  }
936 
937  return 0;
938 }
939 
940 static int
942  int len, int is_insert)
943 {
944  if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len))
945  return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert);
946  else
947  return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert);
948 }
949 
950 static int
952 {
953  switch (z_type)
954  {
955  case Z_PACKET_SW_BP:
956  case Z_PACKET_HW_BP:
957  case Z_PACKET_WRITE_WP:
958  case Z_PACKET_READ_WP:
959  case Z_PACKET_ACCESS_WP:
960  return 1;
961  default:
962  return 0;
963  }
964 }
965 
966 /* Insert a hardware breakpoint/watchpoint.
967  It actually only records the info of the to-be-inserted bp/wp;
968  the actual insertion will happen when threads are resumed.
969 
970  Return 0 if succeed;
971  Return 1 if TYPE is unsupported type;
972  Return -1 if an error occurs. */
973 
974 static int
976  int len, struct raw_breakpoint *bp)
977 {
978  int ret;
979  enum target_hw_bp_type targ_type;
980 
981  if (show_debug_regs)
982  fprintf (stderr, "insert_point on entry (addr=0x%08lx, len=%d)\n",
983  (unsigned long) addr, len);
984 
985  /* Determine the type from the raw breakpoint type. */
986  targ_type = raw_bkpt_type_to_target_hw_bp_type (type);
987 
988  if (targ_type != hw_execute)
989  ret =
990  aarch64_handle_watchpoint (targ_type, addr, len, 1 /* is_insert */);
991  else
992  ret =
993  aarch64_handle_breakpoint (targ_type, addr, len, 1 /* is_insert */);
994 
995  if (show_debug_regs)
997  "insert_point", addr, len, targ_type);
998 
999  return ret;
1000 }
1001 
1002 /* Remove a hardware breakpoint/watchpoint.
1003  It actually only records the info of the to-be-removed bp/wp,
1004  the actual removal will be done when threads are resumed.
1005 
1006  Return 0 if succeed;
1007  Return 1 if TYPE is an unsupported type;
1008  Return -1 if an error occurs. */
1009 
1010 static int
1012  int len, struct raw_breakpoint *bp)
1013 {
1014  int ret;
1015  enum target_hw_bp_type targ_type;
1016 
1017  if (show_debug_regs)
1018  fprintf (stderr, "remove_point on entry (addr=0x%08lx, len=%d)\n",
1019  (unsigned long) addr, len);
1020 
1021  /* Determine the type from the raw breakpoint type. */
1022  targ_type = raw_bkpt_type_to_target_hw_bp_type (type);
1023 
1024  /* Set up state pointers. */
1025  if (targ_type != hw_execute)
1026  ret =
1027  aarch64_handle_watchpoint (targ_type, addr, len, 0 /* is_insert */);
1028  else
1029  ret =
1030  aarch64_handle_breakpoint (targ_type, addr, len, 0 /* is_insert */);
1031 
1032  if (show_debug_regs)
1034  "remove_point", addr, len, targ_type);
1035 
1036  return ret;
1037 }
1038 
1039 /* Returns the address associated with the watchpoint that hit, if
1040  any; returns 0 otherwise. */
1041 
1042 static CORE_ADDR
1044 {
1045  siginfo_t siginfo;
1046  int pid, i;
1047  struct aarch64_debug_reg_state *state;
1048 
1049  pid = lwpid_of (current_thread);
1050 
1051  /* Get the siginfo. */
1052  if (ptrace (PTRACE_GETSIGINFO, pid, NULL, &siginfo) != 0)
1053  return (CORE_ADDR) 0;
1054 
1055  /* Need to be a hardware breakpoint/watchpoint trap. */
1056  if (siginfo.si_signo != SIGTRAP
1057  || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
1058  return (CORE_ADDR) 0;
1059 
1060  /* Check if the address matches any watched address. */
1061  state = aarch64_get_debug_reg_state ();
1062  for (i = aarch64_num_wp_regs - 1; i >= 0; --i)
1063  {
1064  const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]);
1065  const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr;
1066  const CORE_ADDR addr_watch = state->dr_addr_wp[i];
1067  if (state->dr_ref_count_wp[i]
1068  && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i])
1069  && addr_trap >= addr_watch
1070  && addr_trap < addr_watch + len)
1071  return addr_trap;
1072  }
1073 
1074  return (CORE_ADDR) 0;
1075 }
1076 
1077 /* Returns 1 if target was stopped due to a watchpoint hit, 0
1078  otherwise. */
1079 
1080 static int
1082 {
1083  if (aarch64_stopped_data_address () != 0)
1084  return 1;
1085  else
1086  return 0;
1087 }
1088 
1089 /* Fetch the thread-local storage pointer for libthread_db. */
1090 
1091 ps_err_e
1093  lwpid_t lwpid, int idx, void **base)
1094 {
1095  struct iovec iovec;
1096  uint64_t reg;
1097 
1098  iovec.iov_base = &reg;
1099  iovec.iov_len = sizeof (reg);
1100 
1101  if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0)
1102  return PS_ERR;
1103 
1104  /* IDX is the bias from the thread pointer to the beginning of the
1105  thread descriptor. It has to be subtracted due to implementation
1106  quirks in libthread_db. */
1107  *base = (void *) (reg - idx);
1108 
1109  return PS_OK;
1110 }
1111 
1112 /* Called when a new process is created. */
1113 
1114 static struct arch_process_info *
1116 {
1117  struct arch_process_info *info = xcalloc (1, sizeof (*info));
1118 
1120 
1121  return info;
1122 }
1123 
1124 /* Called when a new thread is detected. */
1125 
1126 static void
1128 {
1129  struct arch_lwp_info *info = xcalloc (1, sizeof (*info));
1130 
1131  /* Mark that all the hardware breakpoint/watchpoint register pairs
1132  for this thread need to be initialized (with data from
1133  aarch_process_info.debug_reg_state). */
1134  DR_MARK_ALL_CHANGED (info->dr_changed_bp, aarch64_num_bp_regs);
1135  DR_MARK_ALL_CHANGED (info->dr_changed_wp, aarch64_num_wp_regs);
1136 
1137  lwp->arch_private = info;
1138 }
1139 
1140 static void
1142  struct process_info *child)
1143 {
1144  /* These are allocated by linux_add_process. */
1145  gdb_assert (parent->priv != NULL
1146  && parent->priv->arch_private != NULL);
1147  gdb_assert (child->priv != NULL
1148  && child->priv->arch_private != NULL);
1149 
1150  /* Linux kernel before 2.6.33 commit
1151  72f674d203cd230426437cdcf7dd6f681dad8b0d
1152  will inherit hardware debug registers from parent
1153  on fork/vfork/clone. Newer Linux kernels create such tasks with
1154  zeroed debug registers.
1155 
1156  GDB core assumes the child inherits the watchpoints/hw
1157  breakpoints of the parent, and will remove them all from the
1158  forked off process. Copy the debug registers mirrors into the
1159  new process so that all breakpoints and watchpoints can be
1160  removed together. The debug registers mirror will become zeroed
1161  in the end before detaching the forked off process, thus making
1162  this compatible with older Linux kernels too. */
1163 
1164  *child->priv->arch_private = *parent->priv->arch_private;
1165 }
1166 
1167 /* Called when resuming a thread.
1168  If the debug regs have changed, update the thread's copies. */
1169 
1170 static void
1172 {
1173  struct thread_info *thread = get_lwp_thread (lwp);
1174  ptid_t ptid = ptid_of (thread);
1175  struct arch_lwp_info *info = lwp->arch_private;
1176 
1177  if (DR_HAS_CHANGED (info->dr_changed_bp)
1178  || DR_HAS_CHANGED (info->dr_changed_wp))
1179  {
1180  int tid = ptid_get_lwp (ptid);
1181  struct process_info *proc = find_process_pid (ptid_get_pid (ptid));
1182  struct aarch64_debug_reg_state *state
1183  = &proc->priv->arch_private->debug_reg_state;
1184 
1185  if (show_debug_regs)
1186  fprintf (stderr, "prepare_to_resume thread %ld\n", lwpid_of (thread));
1187 
1188  /* Watchpoints. */
1189  if (DR_HAS_CHANGED (info->dr_changed_wp))
1190  {
1191  aarch64_linux_set_debug_regs (state, tid, 1);
1193  }
1194 
1195  /* Breakpoints. */
1196  if (DR_HAS_CHANGED (info->dr_changed_bp))
1197  {
1198  aarch64_linux_set_debug_regs (state, tid, 0);
1200  }
1201  }
1202 }
1203 
1204 /* ptrace hardware breakpoint resource info is formatted as follows:
1205 
1206  31 24 16 8 0
1207  +---------------+--------------+---------------+---------------+
1208  | RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS |
1209  +---------------+--------------+---------------+---------------+ */
1210 
1211 #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
1212 #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
1213 #define AARCH64_DEBUG_ARCH_V8 0x6
1214 
1215 static void
1217 {
1218  int pid;
1219  struct iovec iov;
1220  struct user_hwdebug_state dreg_state;
1221 
1223 
1224  pid = lwpid_of (current_thread);
1225  iov.iov_base = &dreg_state;
1226  iov.iov_len = sizeof (dreg_state);
1227 
1228  /* Get hardware watchpoint register info. */
1229  if (ptrace (PTRACE_GETREGSET, pid, NT_ARM_HW_WATCH, &iov) == 0
1230  && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
1231  {
1232  aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
1233  if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM)
1234  {
1235  warning ("Unexpected number of hardware watchpoint registers reported"
1236  " by ptrace, got %d, expected %d.",
1237  aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM);
1238  aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM;
1239  }
1240  }
1241  else
1242  {
1243  warning ("Unable to determine the number of hardware watchpoints"
1244  " available.");
1245  aarch64_num_wp_regs = 0;
1246  }
1247 
1248  /* Get hardware breakpoint register info. */
1249  if (ptrace (PTRACE_GETREGSET, pid, NT_ARM_HW_BREAK, &iov) == 0
1250  && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
1251  {
1252  aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
1253  if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM)
1254  {
1255  warning ("Unexpected number of hardware breakpoint registers reported"
1256  " by ptrace, got %d, expected %d.",
1257  aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM);
1258  aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM;
1259  }
1260  }
1261  else
1262  {
1263  warning ("Unable to determine the number of hardware breakpoints"
1264  " available.");
1265  aarch64_num_bp_regs = 0;
1266  }
1267 }
1268 
1269 static struct regset_info aarch64_regsets[] =
1270 {
1271  { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS,
1272  sizeof (struct user_pt_regs), GENERAL_REGS,
1273  aarch64_fill_gregset, aarch64_store_gregset },
1274  { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET,
1275  sizeof (struct user_fpsimd_state), FP_REGS,
1276  aarch64_fill_fpregset, aarch64_store_fpregset
1277  },
1278  { 0, 0, 0, -1, -1, NULL, NULL }
1279 };
1280 
1281 static struct regsets_info aarch64_regsets_info =
1282  {
1283  aarch64_regsets, /* regsets */
1284  0, /* num_regsets */
1285  NULL, /* disabled_regsets */
1286  };
1287 
1288 static struct usrregs_info aarch64_usrregs_info =
1289  {
1292  };
1293 
1294 static struct regs_info regs_info =
1295  {
1296  NULL, /* regset_bitmap */
1299  };
1300 
1301 static const struct regs_info *
1303 {
1304  return &regs_info;
1305 }
1306 
1307 struct linux_target_ops the_low_target =
1308 {
1313  NULL,
1316  (const unsigned char *) &aarch64_breakpoint,
1318  NULL,
1319  0,
1326  NULL,
1327  NULL,
1328  NULL,
1333 };
1334 
1335 void
1337 {
1339 
1340  initialize_regsets_info (&aarch64_regsets_info);
1341 }
unsigned int lwpid_t
struct arch_lwp_info * arch_private
Definition: linux-low.h:352
enum target_hw_bp_type raw_bkpt_type_to_target_hw_bp_type(enum raw_bkpt_type raw_type)
Definition: mem-break.c:195
#define DR_MARK_ALL_CHANGED(x, m)
void initialize_low_arch(void)
struct thread_info * current_thread
Definition: inferiors.c:28
void collect_register(struct regcache *regcache, int n, void *buf)
Definition: regcache.c:414
static int debug_reg_change_callback(struct inferior_list_entry *entry, void *ptr)
static void aarch64_linux_new_thread(struct lwp_info *lwp)
static void aarch64_store_gregset(struct regcache *regcache, const void *buf)
#define ptid_of(inf)
Definition: inferiors.h:75
static void aarch64_fill_gregset(struct regcache *regcache, void *buf)
bfd_vma CORE_ADDR
Definition: common-types.h:41
void supply_register_by_name(struct regcache *regcache, const char *name, const void *buf)
Definition: regcache.c:405
#define AARCH64_DEBUG_ARCH_V8
static void aarch64_linux_set_debug_regs(const struct aarch64_debug_reg_state *state, int tid, int watchpoint)
static int aarch64_cannot_fetch_register(int regno)
static CORE_ADDR aarch64_stopped_data_address(void)
struct aarch64_debug_reg_state debug_reg_state
void warning(const char *fmt,...)
Definition: errors.c:26
unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM]
static struct aarch64_debug_reg_state * aarch64_get_debug_reg_state()
#define Z_PACKET_HW_BP
Definition: mem-break.h:33
static int aarch64_handle_unaligned_watchpoint(enum target_hw_bp_type type, CORE_ADDR addr, int len, int is_insert)
struct process_info * find_process_pid(int pid)
Definition: inferiors.c:302
static struct regs_info regs_info
char * paddress(CORE_ADDR addr)
Definition: utils.c:124
ps_err_e
static int aarch64_supports_z_point_type(char z_type)
#define AARCH64_FPCR_REGNO
#define AARCH64_CPSR_REGNO
static struct regset_info aarch64_regsets[]
static void aarch64_arch_setup(void)
#define _(String)
Definition: gdb_locale.h:40
#define AARCH64_X_REGS_NUM
static int aarch64_regmap[]
static struct arch_process_info * aarch64_linux_new_process(void)
#define get_thread_lwp(thr)
Definition: linux-low.h:235
static int aarch64_breakpoint_at(CORE_ADDR where)
struct target_ops * the_target
Definition: target.c:24
const struct target_desc * tdesc
Definition: inferiors.h:69
static int aarch64_handle_watchpoint(enum target_hw_bp_type type, CORE_ADDR addr, int len, int is_insert)
Definition: ptid.h:35
void init_registers_aarch64(void)
struct arch_process_info * arch_private
Definition: linux-low.h:110
static CORE_ADDR aarch64_get_pc(struct regcache *regcache)
static const gdb_byte aarch64_breakpoint[]
#define Z_PACKET_SW_BP
Definition: mem-break.h:32
static int aarch64_cannot_store_register(int regno)
void collect_register_by_name(struct regcache *regcache, const char *name, void *buf)
Definition: regcache.c:430
ps_err_e ps_get_thread_area(const struct ps_prochandle *ph, lwpid_t lwpid, int idx, void **base)
raw_bkpt_type
Definition: mem-break.h:40
#define Z_PACKET_READ_WP
Definition: mem-break.h:35
#define AARCH64_HWP_ALIGNMENT
static unsigned int aarch64_watchpoint_length(unsigned int ctrl)
#define aarch64_breakpoint_len
const struct target_desc * tdesc_aarch64
int offset
Definition: tracepoint.c:179
#define DR_HAS_CHANGED(x)
int show_debug_regs
Definition: common-debug.c:25
#define AARCH64_HBP_ALIGNMENT
#define AARCH64_HWP_MAX_LEN_PER_REG
#define AARCH64_DEBUG_NUM_SLOTS(x)
static int aarch64_dr_state_remove_one_point(struct aarch64_debug_reg_state *state, enum target_hw_bp_type type, CORE_ADDR addr, int len)
static void aarch64_linux_new_fork(struct process_info *parent, struct process_info *child)
#define AARCH64_HBP_MAX_NUM
#define get_lwp_thread(lwp)
Definition: linux-low.h:236
static struct regsets_info aarch64_regsets_info
static int aarch64_num_bp_regs
static void aarch64_fill_fpregset(struct regcache *regcache, void *buf)
#define AARCH64_NUM_REGS
static unsigned int aarch64_point_encode_ctrl_reg(enum target_hw_bp_type type, int len)
#define gdb_assert(expr)
Definition: gdb_assert.h:33
int stopped
Definition: linux-low.h:267
#define PTRACE_SETREGSET
Definition: linux-ptrace.h:51
#define DR_CLEAR_CHANGED(x)
struct process_info * current_process(void)
Definition: inferiors.c:356
CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM]
static int aarch64_point_is_aligned(int is_watchpoint, CORE_ADDR addr, int len)
struct process_info_private * priv
Definition: inferiors.h:72
struct inferior_list all_threads
Definition: inferiors.c:26
static void aarch64_set_pc(struct regcache *regcache, CORE_ADDR pc)
#define PTRACE_GETREGSET
Definition: linux-ptrace.h:47
int ptid_get_pid(ptid_t ptid)
Definition: ptid.c:52
static void aarch64_show_debug_reg_state(struct aarch64_debug_reg_state *state, const char *func, CORE_ADDR addr, int len, enum target_hw_bp_type type)
#define PTRACE_GETSIGINFO
Definition: linux-ptrace.h:42
static int aarch64_remove_point(enum raw_bkpt_type type, CORE_ADDR addr, int len, struct raw_breakpoint *bp)
bfd_byte gdb_byte
Definition: common-types.h:38
unsigned long long dr_changed_t
#define AARCH64_FPSR_REGNO
#define lwpid_of(inf)
Definition: inferiors.h:77
#define DR_CONTROL_ENABLED(ctrl)
#define AARCH64_PC_REGNO
static int aarch64_stopped_by_watchpoint(void)
static const struct regs_info * aarch64_regs_info(void)
#define AARCH64_SP_REGNO
#define AARCH64_HWP_MAX_NUM
int debug_threads
Definition: debug.c:24
static void aarch64_store_fpregset(struct regcache *regcache, const void *buf)
static int aarch64_handle_breakpoint(enum target_hw_bp_type type, CORE_ADDR addr, int len, int is_insert)
int(* read_memory)(CORE_ADDR memaddr, unsigned char *myaddr, int len)
Definition: target.h:160
#define DR_CONTROL_LENGTH(ctrl)
#define pid_of(inf)
Definition: inferiors.h:76
dr_changed_t dr_changed_wp
#define AARCH64_X0_REGNO
#define AARCH64_V0_REGNO
#define AARCH64_DEBUG_ARCH(x)
#define Z_PACKET_ACCESS_WP
Definition: mem-break.h:36
void perror_with_name(const char *string)
Definition: utils.c:57
target_hw_bp_type
Definition: break-common.h:22
static int aarch64_num_wp_regs
unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM]
unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM]
#define DR_MARK_N_CHANGED(x, n)
long ptid_get_lwp(ptid_t ptid)
Definition: ptid.c:60
Definition: inferiors.h:29
static struct usrregs_info aarch64_usrregs_info
static int aarch64_handle_aligned_watchpoint(enum target_hw_bp_type type, CORE_ADDR addr, int len, int is_insert)
static void aarch64_linux_prepare_to_resume(struct lwp_info *lwp)
static void aarch64_init_debug_reg_state(struct aarch64_debug_reg_state *state)
void debug_printf(const char *fmt,...)
Definition: common-debug.c:30
static int aarch64_dr_state_insert_one_point(struct aarch64_debug_reg_state *state, enum target_hw_bp_type type, CORE_ADDR addr, int len)
void linux_stop_lwp(struct lwp_info *lwp)
Definition: linux-low.c:3467
dr_changed_t dr_changed_bp
void supply_register(struct regcache *regcache, int n, const void *buf)
Definition: regcache.c:330
PTR xcalloc(size_t number, size_t size)
Definition: common-utils.c:71
static void aarch64_align_watchpoint(CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p, int *aligned_len_p, CORE_ADDR *next_addr_p, int *next_len_p)
void error(const char *fmt,...)
Definition: errors.c:38
unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM]
#define AARCH64_V_REGS_NUM
#define Z_PACKET_WRITE_WP
Definition: mem-break.h:34
struct inferior_list_entry * find_inferior(struct inferior_list *list, int(*func)(struct inferior_list_entry *, void *), void *arg)
Definition: inferiors.c:188
void aarch64_notify_debug_reg_change(const struct aarch64_debug_reg_state *state, int is_watchpoint, unsigned int idx)
static int aarch64_insert_point(enum raw_bkpt_type type, CORE_ADDR addr, int len, struct raw_breakpoint *bp)
CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM]