49 #include "gdb/sim-arm.h"
52 #include "coff/internal.h"
77 #define MSYMBOL_SET_SPECIAL(msym) \
78 MSYMBOL_TARGET_FLAG_1 (msym) = 1
80 #define MSYMBOL_IS_SPECIAL(msym) \
81 MSYMBOL_TARGET_FLAG_1 (msym)
206 {
"r0",
"r1",
"r2",
"r3",
207 "r4",
"r5",
"r6",
"r7",
208 "r8",
"r9",
"r10",
"r11",
209 "r12",
"sp",
"lr",
"pc",
210 "f0",
"f1",
"f2",
"f3",
211 "f4",
"f5",
"f6",
"f7",
268 #define DISPLACED_STEPPING_ARCH_VERSION 5
272 #define IS_THUMB_ADDR(addr) ((addr) & 1)
273 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
274 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
305 return (cpsr & t_bit) != 0;
358 return map_sym->
type;
367 return map_sym->
type;
394 "displaced: check mode of %.8lx instead of %.8lx\n",
396 (
unsigned long) memaddr);
453 && (val & 0xfffffff0) == 0xfffffff0)
459 return (val & 0x03fffffc);
473 if (msym.minsym != NULL
481 if (strstr (name,
"_from_thumb") != NULL)
517 #define submask(x) ((1L << ((x) + 1)) - 1)
518 #define bit(obj,st) (((obj) >> (st)) & 1)
519 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
520 #define sbits(obj,st,fn) \
521 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
522 #define BranchDest(addr,instr) \
523 ((CORE_ADDR) (((unsigned long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
528 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
529 ((bits ((insn1), 0, 3) << 12) \
530 | (bits ((insn1), 10, 10) << 11) \
531 | (bits ((insn2), 12, 14) << 8) \
532 | bits ((insn2), 0, 7))
536 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
537 ((bits ((insn), 16, 19) << 12) \
538 | bits ((insn), 0, 11))
545 unsigned int count = imm >> 7;
553 return (imm & 0xff) | ((imm & 0xff) << 16);
555 return ((imm & 0xff) << 8) | ((imm & 0xff) << 24);
557 return (imm & 0xff) | ((imm & 0xff) << 8)
558 | ((imm & 0xff) << 16) | ((imm & 0xff) << 24);
561 return (0x80 | (imm & 0x7f)) << (32 - count);
570 if ((inst & 0xff00) == 0xbd00)
573 if ((inst & 0xf000) == 0xd000)
576 if ((inst & 0xf800) == 0xe000)
579 if ((inst & 0xff00) == 0x4700)
582 if ((inst & 0xff87) == 0x4687)
585 if ((inst & 0xf500) == 0xb100)
597 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
601 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
606 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
611 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
620 if ((inst1 & 0xfe50) == 0xe810)
624 if (
bit (inst1, 7) && !
bit (inst1, 8))
630 else if (!
bit (inst1, 7) &&
bit (inst1, 8))
636 else if (
bit (inst1, 7) &&
bit (inst1, 8))
641 else if (!
bit (inst1, 7) && !
bit (inst1, 8))
650 if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
656 if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
659 if (
bits (inst1, 0, 3) == 15)
665 if ((inst2 & 0x0fc0) == 0x0000)
671 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
677 if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
692 return (insn == 0x46bd
693 || (insn & 0xff80) == 0xb000
694 || (insn & 0xfe00) == 0xbc00);
717 for (i = 0; i < 16; i++)
722 while (start < limit)
728 if ((insn & 0xfe00) == 0xb400)
738 mask = (insn & 0xff) | ((insn & 0x100) << 6);
742 if (mask & (1 << regno))
749 else if ((insn & 0xff80) == 0xb080)
751 offset = (insn & 0x7f) << 2;
760 else if ((insn & 0xf800) == 0xa800)
763 else if ((insn & 0xfe00) == 0x1c00
767 else if ((insn & 0xf800) == 0x3000
771 else if ((insn & 0xfe00) == 0x1800
775 regs[
bits (insn, 6, 8)]);
776 else if ((insn & 0xff00) == 0x4400
779 int rd = (
bit (insn, 7) << 3) +
bits (insn, 0, 2);
780 int rm =
bits (insn, 3, 6);
781 regs[rd] =
pv_add (regs[rd], regs[rm]);
783 else if ((insn & 0xff00) == 0x4600)
785 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
786 int src_reg = (insn & 0x78) >> 3;
787 regs[dst_reg] = regs[src_reg];
789 else if ((insn & 0xf800) == 0x9000)
794 int regno = (insn >> 8) & 0x7;
797 offset = (insn & 0xff) << 2;
805 else if ((insn & 0xf800) == 0x6000)
807 int rd =
bits (insn, 0, 2);
808 int rn =
bits (insn, 3, 5);
811 offset =
bits (insn, 6, 10) << 2;
819 else if (((insn & 0xf800) == 0x7000
820 || (insn & 0xf800) == 0x8000)
824 else if ((insn & 0xf800) == 0xc800
829 else if ((insn & 0xf800) == 0x9800
830 || ((insn & 0xf800) == 0x6800
834 else if ((insn & 0xffc0) == 0x0000
835 || (insn & 0xffc0) == 0x1c00)
839 else if ((insn & 0xf800) == 0x2000)
843 else if ((insn & 0xf800) == 0x4800)
846 unsigned int constant;
849 loc = start + 4 +
bits (insn, 0, 7) * 4;
855 unsigned short inst2;
858 byte_order_for_code);
860 if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800)
866 int j1, j2, imm1, imm2;
868 imm1 =
sbits (insn, 0, 10);
869 imm2 =
bits (inst2, 0, 10);
870 j1 =
bit (inst2, 13);
871 j2 =
bit (inst2, 11);
873 offset = ((imm1 << 12) + (imm2 << 1));
874 offset ^= ((!j2) << 22) | ((!j1) << 23);
876 nextpc = start + 4 +
offset;
878 if (
bit (inst2, 12) == 0)
879 nextpc = nextpc & 0xfffffffc;
882 bit (inst2, 12) != 0))
886 else if ((insn & 0xffd0) == 0xe900
890 pv_t addr = regs[
bits (insn, 0, 3)];
898 if (inst2 & (1 << regno))
905 regs[
bits (insn, 0, 3)] = addr;
908 else if ((insn & 0xff50) == 0xe940
912 int regno1 =
bits (inst2, 12, 15);
913 int regno2 =
bits (inst2, 8, 11);
914 pv_t addr = regs[
bits (insn, 0, 3)];
916 offset = inst2 & 0xff;
930 regs[
bits (insn, 0, 3)] = addr;
933 else if ((insn & 0xfff0) == 0xf8c0
934 && (inst2 & 0x0c00) == 0x0c00
937 int regno =
bits (inst2, 12, 15);
938 pv_t addr = regs[
bits (insn, 0, 3)];
940 offset = inst2 & 0xff;
952 regs[
bits (insn, 0, 3)] = addr;
955 else if ((insn & 0xfff0) == 0xf8c0
958 int regno =
bits (inst2, 12, 15);
961 offset = inst2 & 0xfff;
970 else if ((insn & 0xffd0) == 0xf880
975 else if ((insn & 0xffd0) == 0xf800
976 && (inst2 & 0x0d00) == 0x0c00
981 else if ((insn & 0xffd0) == 0xe890
983 && (inst2 & 0x8000) == 0x0000
989 else if ((insn & 0xffb0) == 0xe950
995 else if ((insn & 0xfff0) == 0xf850
996 && (inst2 & 0x0d00) == 0x0c00
1001 else if ((insn & 0xfff0) == 0xf8d0
1006 else if ((insn & 0xfbf0) == 0xf100
1007 && (inst2 & 0x8000) == 0x0000)
1009 unsigned int imm = ((
bits (insn, 10, 10) << 11)
1010 | (
bits (inst2, 12, 14) << 8)
1011 |
bits (inst2, 0, 7));
1013 regs[
bits (inst2, 8, 11)]
1018 else if ((insn & 0xfbf0) == 0xf200
1019 && (inst2 & 0x8000) == 0x0000)
1021 unsigned int imm = ((
bits (insn, 10, 10) << 11)
1022 | (
bits (inst2, 12, 14) << 8)
1023 |
bits (inst2, 0, 7));
1025 regs[
bits (inst2, 8, 11)]
1029 else if ((insn & 0xfbf0) == 0xf1a0
1030 && (inst2 & 0x8000) == 0x0000)
1032 unsigned int imm = ((
bits (insn, 10, 10) << 11)
1033 | (
bits (inst2, 12, 14) << 8)
1034 |
bits (inst2, 0, 7));
1036 regs[
bits (inst2, 8, 11)]
1041 else if ((insn & 0xfbf0) == 0xf2a0
1042 && (inst2 & 0x8000) == 0x0000)
1044 unsigned int imm = ((
bits (insn, 10, 10) << 11)
1045 | (
bits (inst2, 12, 14) << 8)
1046 |
bits (inst2, 0, 7));
1048 regs[
bits (inst2, 8, 11)]
1052 else if ((insn & 0xfbff) == 0xf04f)
1054 unsigned int imm = ((
bits (insn, 10, 10) << 11)
1055 | (
bits (inst2, 12, 14) << 8)
1056 |
bits (inst2, 0, 7));
1058 regs[
bits (inst2, 8, 11)]
1062 else if ((insn & 0xfbf0) == 0xf240)
1070 else if (insn == 0xea5f
1071 && (inst2 & 0xf0f0) == 0)
1073 int dst_reg = (inst2 & 0x0f00) >> 8;
1074 int src_reg = inst2 & 0xf;
1075 regs[dst_reg] = regs[src_reg];
1078 else if ((insn & 0xff7f) == 0xf85f)
1081 unsigned int constant;
1084 offset =
bits (inst2, 0, 11);
1086 loc = start + 4 +
offset;
1088 loc = start + 4 -
offset;
1094 else if ((insn & 0xff7f) == 0xe95f)
1097 unsigned int constant;
1100 offset =
bits (inst2, 0, 7) << 2;
1102 loc = start + 4 +
offset;
1104 loc = start + 4 -
offset;
1122 unrecognized_pc = start;
1136 unrecognized_pc = start;
1146 if (unrecognized_pc == 0)
1147 unrecognized_pc = start;
1152 return unrecognized_pc;
1174 for (i = 0; i < 16; i++)
1179 return unrecognized_pc;
1191 unsigned int *destreg,
int *
offset)
1195 unsigned int low, high, address;
1200 unsigned short insn1
1203 if ((insn1 & 0xf800) == 0x4800)
1205 *destreg =
bits (insn1, 8, 10);
1207 address = (pc & 0xfffffffc) + 4 + (
bits (insn1, 0, 7) << 2);
1209 byte_order_for_code);
1211 else if ((insn1 & 0xfbf0) == 0xf240)
1213 unsigned short insn2
1224 if ((insn1 & 0xfbc0) == 0xf2c0)
1227 *destreg =
bits (insn2, 8, 11);
1229 address = (high << 16 | low);
1238 if ((insn & 0x0e5f0000) == 0x041f0000)
1240 address =
bits (insn, 0, 11) + pc + 8;
1242 byte_order_for_code);
1244 *destreg =
bits (insn, 12, 15);
1247 else if ((insn & 0x0ff00000) == 0x03000000)
1254 if ((insn & 0x0ff00000) == 0x03400000)
1257 *destreg =
bits (insn, 12, 15);
1259 address = (high << 16 | low);
1301 unsigned int basereg;
1316 if (stack_chk_guard.
minsym == NULL
1322 unsigned int destreg;
1327 if ((insn & 0xf800) != 0x6800)
1329 if (
bits (insn, 3, 5) != basereg)
1331 destreg =
bits (insn, 0, 2);
1334 byte_order_for_code);
1336 if ((insn & 0xf800) != 0x6000)
1338 if (destreg !=
bits (insn, 0, 2))
1343 unsigned int destreg;
1348 if ((insn & 0x0e500000) != 0x04100000)
1350 if (
bits (insn, 16, 19) != basereg)
1352 destreg =
bits (insn, 12, 15);
1355 4, byte_order_for_code);
1356 if ((insn & 0x0e500000) != 0x04000000)
1358 if (
bits (insn, 12, 15) != destreg)
1364 return pc + offset + 4;
1366 return pc + offset + 8;
1400 if (post_prologue_pc)
1411 if (post_prologue_pc
1416 return post_prologue_pc;
1418 if (post_prologue_pc != 0)
1433 post_prologue_pc, NULL);
1436 post_prologue_pc, NULL);
1438 if (analyzed_limit != post_prologue_pc)
1441 return post_prologue_pc;
1498 if (prologue_end > prologue_start + 64)
1500 prologue_end = prologue_start + 64;
1508 prologue_end =
min (prologue_end, prev_pc);
1520 switch (
bits (this_instr, 24, 27))
1530 if (
bits (this_instr, 12, 15) == 15)
1531 error (
_(
"Invalid update to pc in instruction"));
1537 switch (
bits (this_instr, 25, 27))
1540 if (
bits (this_instr, 23, 24) == 2 &&
bit (this_instr, 20) == 0)
1543 if (
bit (this_instr, 4) == 1 &&
bit (this_instr, 7) == 1)
1551 if (
bits (this_instr, 4, 27) == 0x12fff1
1552 ||
bits (this_instr, 4, 27) == 0x12fff2
1553 ||
bits (this_instr, 4, 27) == 0x12fff3)
1563 if (
bits (this_instr, 12, 15) == 15)
1571 if (
bits (this_instr, 25, 27) == 3 &&
bit (this_instr, 4) == 1)
1575 if (
bit (this_instr, 20) == 0)
1586 if (
bit (this_instr, 20) == 1 &&
bit (this_instr, 15) == 1)
1613 if ((insn & 0x0df0f000) == 0x0080d000
1615 || (insn & 0x0df0f000) == 0x0040d000
1617 || (insn & 0x0ffffff0) == 0x01a0d000
1619 || (insn & 0x0fff0000) == 0x08bd0000
1621 || (insn & 0x0fff0000) == 0x049d0000)
1668 for (current_pc = prologue_start;
1669 current_pc < prologue_end;
1675 if (insn == 0xe1a0c00d)
1680 else if ((insn & 0xfff00000) == 0xe2800000
1683 unsigned imm = insn & 0xff;
1684 unsigned rot = (insn & 0xf00) >> 7;
1685 int rd =
bits (insn, 12, 15);
1686 imm = (imm >> rot) | (imm << (32 - rot));
1690 else if ((insn & 0xfff00000) == 0xe2400000
1693 unsigned imm = insn & 0xff;
1694 unsigned rot = (insn & 0xf00) >> 7;
1695 int rd =
bits (insn, 12, 15);
1696 imm = (imm >> rot) | (imm << (32 - rot));
1700 else if ((insn & 0xffff0fff) == 0xe52d0004)
1707 regs[
bits (insn, 12, 15)]);
1710 else if ((insn & 0xffff0000) == 0xe92d0000)
1715 int mask = insn & 0xffff;
1722 if (mask & (1 << regno))
1729 else if ((insn & 0xffff0000) == 0xe54b0000
1730 || (insn & 0xffff00f0) == 0xe14b00b0
1731 || (insn & 0xffffc000) == 0xe50b0000)
1736 else if ((insn & 0xffff0000) == 0xe5cd0000
1737 || (insn & 0xffff00f0) == 0xe1cd00b0
1738 || (insn & 0xffffc000) == 0xe58d0000)
1743 else if ((insn & 0xfff00000) == 0xe8800000
1750 else if ((insn & 0xfffff000) == 0xe24cb000)
1752 unsigned imm = insn & 0xff;
1753 unsigned rot = (insn & 0xf00) >> 7;
1754 imm = (imm >> rot) | (imm << (32 - rot));
1757 else if ((insn & 0xfffff000) == 0xe24dd000)
1759 unsigned imm = insn & 0xff;
1760 unsigned rot = (insn & 0xf00) >> 7;
1761 imm = (imm >> rot) | (imm << (32 - rot));
1764 else if ((insn & 0xffff7fff) == 0xed6d0103
1773 pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
1775 else if ((insn & 0xffbf0fff) == 0xec2d0200
1779 int n_saved_fp_regs;
1780 unsigned int fp_start_reg, fp_bound_reg;
1785 if ((insn & 0x800) == 0x800)
1787 if ((insn & 0x40000) == 0x40000)
1788 n_saved_fp_regs = 3;
1790 n_saved_fp_regs = 1;
1794 if ((insn & 0x40000) == 0x40000)
1795 n_saved_fp_regs = 2;
1797 n_saved_fp_regs = 4;
1801 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
1802 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
1806 regs[fp_start_reg++]);
1809 else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL)
1821 else if ((insn & 0xf0000000) != 0xe0000000)
1831 else if ((insn & 0xfe500000) == 0xe8100000
1836 else if ((insn & 0xfc500000) == 0xe4100000
1840 else if ((insn & 0xffff0ff0) == 0xe1a00000)
1852 unrecognized_pc = current_pc;
1860 if (unrecognized_pc == 0)
1861 unrecognized_pc = current_pc;
1865 int framereg, framesize;
1892 paddress (gdbarch, unrecognized_pc));
1895 return unrecognized_pc;
1905 CORE_ADDR prologue_start, prologue_end, current_pc;
1961 if (prologue_end > prologue_start + 64)
1963 prologue_end = prologue_start + 64;
1982 (gdbarch, return_value) - 8;
1983 prologue_end = prologue_start + 64;
1987 if (prev_pc < prologue_end)
1988 prologue_end = prev_pc;
2006 if (unwound_fp == 0)
2029 if (*this_cache == NULL)
2031 cache = *this_cache;
2036 return UNWIND_OUTERMOST;
2040 return UNWIND_OUTERMOST;
2042 return UNWIND_NO_REASON;
2057 if (*this_cache == NULL)
2059 cache = *this_cache;
2073 static struct value *
2081 if (*this_cache == NULL)
2083 cache = *this_cache;
2166 for (i = 0; i < objfile->
obfd->section_count; i++)
2183 if (bfd_get_section_flags (objfile->
obfd,
2186 bfd_vma start,
size;
2190 if (start <= vma && vma < start + size)
2216 asection *exidx, *extab;
2217 bfd_vma exidx_vma = 0, extab_vma = 0;
2218 bfd_size_type exidx_size = 0, extab_size = 0;
2219 gdb_byte *exidx_data = NULL, *extab_data = NULL;
2228 exidx = bfd_get_section_by_name (objfile->
obfd,
".ARM.exidx");
2231 exidx_vma = bfd_section_vma (objfile->
obfd, exidx);
2232 exidx_size = bfd_get_section_size (exidx);
2233 exidx_data =
xmalloc (exidx_size);
2236 if (!bfd_get_section_contents (objfile->
obfd, exidx,
2237 exidx_data, 0, exidx_size))
2244 extab = bfd_get_section_by_name (objfile->
obfd,
".ARM.extab");
2247 extab_vma = bfd_section_vma (objfile->
obfd, extab);
2248 extab_size = bfd_get_section_size (extab);
2249 extab_data =
xmalloc (extab_size);
2252 if (!bfd_get_section_contents (objfile->
obfd, extab,
2253 extab_data, 0, extab_size))
2264 objfile->
obfd->section_count,
2268 for (i = 0; i < exidx_size / 8; i++)
2271 bfd_vma idx = bfd_h_get_32 (objfile->
obfd, exidx_data + i * 8);
2272 bfd_vma val = bfd_h_get_32 (objfile->
obfd, exidx_data + i * 8 + 4);
2274 int n_bytes = 0, n_words = 0;
2279 idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2280 idx += exidx_vma + i * 8;
2293 else if ((val & 0xff000000) == 0x80000000)
2300 else if (!(val & 0x80000000))
2303 addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2304 addr += exidx_vma + i * 8 + 4;
2306 if (addr >= extab_vma && addr + 4 <= extab_vma + extab_size)
2308 word = bfd_h_get_32 (objfile->
obfd,
2309 extab_data + addr - extab_vma);
2312 if ((
word & 0xff000000) == 0x80000000)
2317 else if ((
word & 0xff000000) == 0x81000000
2318 || (
word & 0xff000000) == 0x82000000)
2322 n_words = ((
word >> 16) & 0xff);
2324 else if (!(
word & 0x80000000))
2328 int gnu_personality = 0;
2331 pers = ((
word & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2339 static const char *personality[] =
2341 "__gcc_personality_v0",
2342 "__gxx_personality_v0",
2343 "__gcj_personality_v0",
2344 "__gnu_objc_personality_v0",
2351 for (k = 0; personality[k]; k++)
2353 (pc, personality[k], objfile))
2355 gnu_personality = 1;
2364 && addr + 4 <= extab_vma + extab_size)
2366 word = bfd_h_get_32 (objfile->
obfd,
2367 extab_data + addr - extab_vma);
2370 n_words = ((
word >> 24) & 0xff);
2378 if (addr < extab_vma || addr + 4 * n_words > extab_vma + extab_size)
2379 n_words = n_bytes = 0;
2384 if (n_bytes || n_words)
2387 n_bytes + n_words * 4 + 1);
2394 word = bfd_h_get_32 (objfile->
obfd,
2395 extab_data + addr - extab_vma);
2410 new_exidx_entry.
addr = idx;
2411 new_exidx_entry.
entry = entry;
2459 return map_sym->
entry;
2468 return map_sym->
entry;
2521 if ((insn & 0xc0) == 0)
2523 int offset = insn & 0x3f;
2524 vsp += (offset << 2) + 4;
2526 else if ((insn & 0xc0) == 0x40)
2528 int offset = insn & 0x3f;
2529 vsp -= (offset << 2) + 4;
2531 else if ((insn & 0xf0) == 0x80)
2533 int mask = ((insn & 0xf) << 8) | *entry++;
2543 for (i = 0; i < 12; i++)
2544 if (mask & (1 << i))
2554 else if ((insn & 0xf0) == 0x90)
2556 int reg = insn & 0xf;
2566 else if ((insn & 0xf0) == 0xa0)
2568 int count = insn & 0x7;
2569 int pop_lr = (insn & 0x8) != 0;
2573 for (i = 0; i <= count; i++)
2586 else if (insn == 0xb0)
2597 else if (insn == 0xb1)
2599 int mask = *entry++;
2603 if (mask == 0 || mask >= 16)
2607 for (i = 0; i < 4; i++)
2608 if (mask & (1 << i))
2614 else if (insn == 0xb2)
2621 offset |= (*entry & 0x7f) << shift;
2624 while (*entry++ & 0x80);
2626 vsp += 0x204 + (offset << 2);
2628 else if (insn == 0xb3)
2630 int start = *entry >> 4;
2631 int count = (*entry++) & 0xf;
2635 if (start + count >= 16)
2639 for (i = 0; i <= count; i++)
2648 else if ((insn & 0xf8) == 0xb8)
2650 int count = insn & 0x7;
2654 for (i = 0; i <= count; i++)
2663 else if (insn == 0xc6)
2665 int start = *entry >> 4;
2666 int count = (*entry++) & 0xf;
2670 if (start + count >= 16)
2674 for (i = 0; i <= count; i++)
2680 else if (insn == 0xc7)
2682 int mask = *entry++;
2686 if (mask == 0 || mask >= 16)
2690 for (i = 0; i < 4; i++)
2691 if (mask & (1 << i))
2697 else if ((insn & 0xf8) == 0xc0)
2699 int count = insn & 0x7;
2703 for (i = 0; i <= count; i++)
2709 else if (insn == 0xc8)
2711 int start = *entry >> 4;
2712 int count = (*entry++) & 0xf;
2716 if (start + count >= 16)
2721 for (i = 0; i <= count; i++)
2727 else if (insn == 0xc9)
2729 int start = *entry >> 4;
2730 int count = (*entry++) & 0xf;
2734 for (i = 0; i <= count; i++)
2740 else if ((insn & 0xf8) == 0xd0)
2742 int count = insn & 0x7;
2746 for (i = 0; i <= count; i++)
2784 void **this_prologue_cache)
2788 CORE_ADDR addr_in_block, exidx_region, func_start;
2827 byte_order_for_code, &insn)
2828 && (insn & 0xff00) == 0xdf00 )
2836 byte_order_for_code, &insn)
2837 && (insn & 0x0f000000) == 0x0f000000 )
2857 if (func_start > exidx_region)
2867 *this_prologue_cache = cache;
2923 if ((insn & 0xff80) == 0x4700)
2960 if (*this_cache == NULL)
2962 cache = *this_cache;
2970 void **this_prologue_cache)
3036 cache->
prev_sp = unwound_sp + 32;
3038 && (xpsr & (1 << 9)) != 0)
3054 if (*this_cache == NULL)
3056 cache = *this_cache;
3066 static struct value *
3074 if (*this_cache == NULL)
3076 cache = *this_cache;
3093 void **this_prologue_cache)
3103 if (this_pc == 0xfffffff1 || this_pc == 0xfffffff9
3104 || this_pc == 0xfffffffd)
3127 if (*this_cache == NULL)
3129 cache = *this_cache;
3138 arm_normal_frame_base
3173 static struct value *
3204 _(
"Unexpected register %d"), regnum);
3232 unsigned int insn, insn2;
3233 int found_return = 0, found_stack_adjust = 0;
3259 while (scan_pc < func_end && !found_return)
3267 if ((insn & 0xff80) == 0x4700)
3269 else if (insn == 0x46f7)
3273 if ((insn & 0xff00) == 0xbd00)
3289 else if (insn == 0xf85d
3290 && (insn2 & 0x0fff) == 0x0b04)
3292 if ((insn2 & 0xf000) == 0xf000)
3295 else if ((insn & 0xffbf) == 0xecbd
3296 && (insn2 & 0x0e00) == 0x0a00)
3314 if (pc - 4 < func_start)
3323 found_stack_adjust = 1;
3324 else if (insn == 0xe8bd)
3325 found_stack_adjust = 1;
3326 else if (insn == 0xf85d
3327 && (insn2 & 0x0fff) == 0x0b04)
3328 found_stack_adjust = 1;
3329 else if ((insn & 0xffbf) == 0xecbd
3330 && (insn2 & 0x0e00) == 0x0a00)
3331 found_stack_adjust = 1;
3333 return found_stack_adjust;
3362 if ((insn & 0x0ffffff0) == 0x012fff10)
3365 else if ((insn & 0x0ffffff0) == 0x01a0f000)
3368 else if ((insn & 0x0fff0000) == 0x08bd0000
3369 && (insn & 0x0000c000) != 0)
3380 if (pc < func_start + 4)
3409 memcpy (si->
data, contents, len);
3611 else if (count == 0)
3628 if (sub_count == -1)
3637 else if (count == 0)
3654 if (sub_count == -1)
3656 count = (count > sub_count ? count : sub_count);
3663 else if (count == 0)
3690 if (c <= 0 || c > 4)
3733 unsigned vfp_regs_free = (1 << 16) - 1;
3768 for (argnum = 0; argnum < nargs; argnum++)
3771 struct type *arg_type;
3772 struct type *target_type;
3774 const bfd_byte *val;
3778 int may_use_core_reg = 1;
3817 may_use_core_reg = 0;
3820 shift = unit_length / 4;
3821 mask = (1 << (shift * vfp_base_count)) - 1;
3822 for (regno = 0; regno < 16; regno += shift)
3823 if (((vfp_regs_free >> regno) & mask) == mask)
3832 vfp_regs_free &= ~(mask << regno);
3833 reg_scaled = regno / shift;
3835 for (i = 0; i < vfp_base_count; i++)
3839 if (reg_char ==
'q')
3841 val + i * unit_length);
3844 xsnprintf (name_buf,
sizeof (name_buf),
"%c%d",
3845 reg_char, reg_scaled + i);
3849 val + i * unit_length);
3863 if (nstack & (align - 1))
3870 if (may_use_core_reg
3880 && target_type != NULL
3886 bfd_byte *copy = alloca (len);
3906 if (byte_order == BFD_ENDIAN_BIG)
3963 if (flags & (1 << 0))
3965 if (flags & (1 << 1))
3967 if (flags & (1 << 2))
3969 if (flags & (1 << 3))
3971 if (flags & (1 << 4))
3985 type = (status >> 24) & 127;
3986 if (status & (1 << 31))
3999 static struct type *
4012 static struct type *
4019 struct type *t, *elem;
4051 static struct type *
4058 struct type *t, *elem;
4086 static struct type *
4092 && regnum >= num_regs && regnum < num_regs + 32)
4096 && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16)
4140 if (reg >= 0 && reg <= 15)
4147 if (reg >= 16 && reg <= 23)
4151 if (reg >= 96 && reg <= 103)
4155 if (reg >= 104 && reg <= 111)
4158 if (reg >= 112 && reg <= 127)
4161 if (reg >= 192 && reg <= 199)
4172 if (reg >= 64 && reg <= 95)
4176 xsnprintf (name_buf,
sizeof (name_buf),
"s%d", reg - 64);
4183 if (reg >= 256 && reg <= 287)
4187 xsnprintf (name_buf,
sizeof (name_buf),
"d%d", reg - 256);
4212 return SIM_ARM_R0_REGNUM + reg;
4216 return SIM_ARM_FP0_REGNUM + reg;
4220 return SIM_ARM_FPS_REGNUM + reg;
4233 void *dbl,
int endianess)
4237 if (endianess == BFD_ENDIAN_BIG)
4252 if (endianess == BFD_ENDIAN_BIG)
4268 return ((status_reg &
FLAG_Z) != 0);
4270 return ((status_reg & FLAG_Z) == 0);
4272 return ((status_reg &
FLAG_C) != 0);
4274 return ((status_reg & FLAG_C) == 0);
4276 return ((status_reg &
FLAG_N) != 0);
4278 return ((status_reg & FLAG_N) == 0);
4280 return ((status_reg &
FLAG_V) != 0);
4282 return ((status_reg & FLAG_V) == 0);
4284 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
4286 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
4288 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
4290 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
4292 return (((status_reg & FLAG_Z) == 0)
4293 && (((status_reg & FLAG_N) == 0)
4294 == ((status_reg & FLAG_V) == 0)));
4296 return (((status_reg & FLAG_Z) != 0)
4297 || (((status_reg & FLAG_N) == 0)
4298 != ((status_reg & FLAG_V) == 0)));
4303 static unsigned long
4305 unsigned long pc_val,
unsigned long status_reg)
4307 unsigned long res, shift;
4308 int rm =
bits (inst, 0, 3);
4313 int rs =
bits (inst, 8, 11);
4314 shift = (rs == 15 ? pc_val + 8
4318 shift =
bits (inst, 7, 11);
4321 ? (pc_val + (
bit (inst, 4) ? 12 : 8))
4327 res = shift >= 32 ? 0 : res << shift;
4331 res = shift >= 32 ? 0 : res >> shift;
4337 res = ((res & 0x80000000
L)
4338 ? ~((~res) >> shift) : res >> shift);
4344 res = (res >> 1) | (carry ? 0x80000000L : 0);
4346 res = (res >> shift) | (res << (32 - shift));
4350 return res & 0xffffffff;
4359 for (nbits = 0; val != 0; nbits++)
4370 if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
4381 itstate = (itstate & 0xe0) | ((itstate << 1) & 0x1f);
4384 if ((itstate & 0x0f) == 0)
4403 unsigned long pc_val = ((
unsigned long) pc) + 4;
4404 unsigned short inst1;
4423 itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3);
4435 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
4440 itstate = inst1 & 0x00ff;
4446 byte_order_for_code);
4453 else if (itstate != 0)
4465 byte_order_for_code);
4472 else if ((itstate & 0x0f) == 0x08)
4497 cond_negated = (itstate >> 4) & 1;
4507 byte_order_for_code);
4511 while (itstate != 0 && ((itstate >> 4) & 1) == cond_negated);
4517 else if (itstate & 0x0f)
4520 int cond = itstate >> 4;
4530 if ((inst1 & 0xff00) == 0xbd00)
4540 else if ((inst1 & 0xf000) == 0xd000)
4542 unsigned long cond =
bits (inst1, 8, 11);
4553 nextpc = pc_val + (
sbits (inst1, 0, 7) << 1);
4555 else if ((inst1 & 0xf800) == 0xe000)
4557 nextpc = pc_val + (
sbits (inst1, 0, 10) << 1);
4561 unsigned short inst2;
4568 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
4572 if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
4575 int j1, j2, imm1, imm2;
4577 imm1 =
sbits (inst1, 0, 10);
4578 imm2 =
bits (inst2, 0, 10);
4579 j1 =
bit (inst2, 13);
4580 j2 =
bit (inst2, 11);
4582 offset = ((imm1 << 12) + (imm2 << 1));
4583 offset ^= ((!j2) << 22) | ((!j1) << 23);
4585 nextpc = pc_val +
offset;
4587 if (
bit (inst2, 12) == 0)
4588 nextpc = nextpc & 0xfffffffc;
4590 else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
4594 nextpc -= inst2 & 0x00ff;
4596 else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
4601 int sign, j1, j2, imm1, imm2;
4603 sign =
sbits (inst1, 10, 10);
4604 imm1 =
bits (inst1, 0, 5);
4605 imm2 =
bits (inst2, 0, 10);
4606 j1 =
bit (inst2, 13);
4607 j2 =
bit (inst2, 11);
4609 offset = (sign << 20) + (j2 << 19) + (j1 << 18);
4610 offset += (imm1 << 12) + (imm2 << 1);
4612 nextpc = pc_val +
offset;
4616 else if ((inst1 & 0xfe50) == 0xe810)
4619 int rn,
offset, load_pc = 1;
4621 rn =
bits (inst1, 0, 3);
4622 if (
bit (inst1, 7) && !
bit (inst1, 8))
4625 if (!
bit (inst2, 15))
4629 else if (!
bit (inst1, 7) &&
bit (inst1, 8))
4632 if (!
bit (inst2, 15))
4636 else if (
bit (inst1, 7) &&
bit (inst1, 8))
4641 else if (!
bit (inst1, 7) && !
bit (inst1, 8))
4655 else if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
4661 else if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
4665 int rn, load_pc = 1;
4667 rn =
bits (inst1, 0, 3);
4673 base +=
bits (inst2, 0, 11);
4675 base -=
bits (inst2, 0, 11);
4677 else if (
bit (inst1, 7))
4678 base +=
bits (inst2, 0, 11);
4679 else if (
bit (inst2, 11))
4681 if (
bit (inst2, 10))
4684 base +=
bits (inst2, 0, 7);
4686 base -=
bits (inst2, 0, 7);
4689 else if ((inst2 & 0x0fc0) == 0x0000)
4691 int shift =
bits (inst2, 4, 5), rm =
bits (inst2, 0, 3);
4701 else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
4706 tbl_reg =
bits (inst1, 0, 3);
4707 if (tbl_reg == 0x0f)
4714 nextpc = pc_val + length;
4716 else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
4721 tbl_reg =
bits (inst1, 0, 3);
4722 if (tbl_reg == 0x0f)
4729 nextpc = pc_val + length;
4732 else if ((inst1 & 0xff00) == 0x4700)
4734 if (
bits (inst1, 3, 6) == 0x0f)
4739 else if ((inst1 & 0xff87) == 0x4687)
4741 if (
bits (inst1, 3, 6) == 0x0f)
4748 else if ((inst1 & 0xf500) == 0xb100)
4751 int imm = (
bit (inst1, 9) << 6) + (
bits (inst1, 3, 7) << 1);
4754 if (
bit (inst1, 11) && reg != 0)
4755 nextpc = pc_val + imm;
4756 else if (!
bit (inst1, 11) && reg == 0)
4757 nextpc = pc_val + imm;
4776 unsigned long pc_val;
4777 unsigned long this_instr;
4781 pc_val = (
unsigned long) pc;
4788 switch (
bits (this_instr, 24, 27))
4795 nextpc |=
bit (this_instr, 24) << 1;
4803 if (
bits (this_instr, 12, 15) == 15)
4804 error (
_(
"Invalid update to pc in instruction"));
4809 switch (
bits (this_instr, 24, 27))
4816 unsigned long operand1, operand2, result = 0;
4820 if (
bits (this_instr, 12, 15) != 15)
4823 if (
bits (this_instr, 22, 25) == 0
4824 &&
bits (this_instr, 4, 7) == 9)
4825 error (
_(
"Invalid update to pc in instruction"));
4828 if (
bits (this_instr, 4, 27) == 0x12fff1
4829 ||
bits (this_instr, 4, 27) == 0x12fff3)
4831 rn =
bits (this_instr, 0, 3);
4840 c = (status &
FLAG_C) ? 1 : 0;
4841 rn =
bits (this_instr, 16, 19);
4846 if (
bit (this_instr, 25))
4848 unsigned long immval =
bits (this_instr, 0, 7);
4849 unsigned long rotate = 2 *
bits (this_instr, 8, 11);
4850 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
4857 switch (
bits (this_instr, 21, 24))
4860 result = operand1 & operand2;
4864 result = operand1 ^ operand2;
4868 result = operand1 - operand2;
4872 result = operand2 - operand1;
4876 result = operand1 + operand2;
4880 result = operand1 + operand2 + c;
4884 result = operand1 - operand2 + c;
4888 result = operand2 - operand1 + c;
4895 result = (
unsigned long) nextpc;
4899 result = operand1 | operand2;
4908 result = operand1 & ~operand2;
4930 if (
bits (this_instr, 25, 27) == 0x3 &&
bit (this_instr, 4) == 1)
4937 if (
bit (this_instr, 20))
4940 if (
bits (this_instr, 12, 15) == 15)
4946 if (
bit (this_instr, 22))
4947 error (
_(
"Invalid update to pc in instruction"));
4950 rn =
bits (this_instr, 16, 19);
4955 if (
bit (this_instr, 24))
4958 int c = (status &
FLAG_C) ? 1 : 0;
4960 (
bit (this_instr, 25)
4962 :
bits (this_instr, 0, 11));
4964 if (
bit (this_instr, 23))
4978 if (
bit (this_instr, 20))
4981 if (
bit (this_instr, 15))
4985 unsigned long rn_val
4987 bits (this_instr, 16, 19));
4989 if (
bit (this_instr, 23))
4992 unsigned long reglist =
bits (this_instr, 0, 14);
4994 if (
bit (this_instr, 24))
4997 else if (
bit (this_instr, 24))
5090 unsigned short insn1, insn2;
5093 int last_breakpoint = 0;
5094 const int atomic_sequence_length = 16;
5099 itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3);
5111 if (!((insn1 & 0xfff0) == 0xe850
5112 || ((insn1 & 0xfff0) == 0xe8d0 && (insn2 & 0x00c0) == 0x0040)))
5117 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
5127 if ((insn1 & 0xf000) == 0xd000 &&
bits (insn1, 8, 11) != 0x0f)
5129 if (last_breakpoint > 0)
5133 breaks[1] = loc + 2 + (
sbits (insn1, 0, 7) << 1);
5152 if ((insn1 & 0xf800) == 0xf000
5153 && (insn2 & 0xd000) == 0x8000
5154 && (insn1 & 0x0380) != 0x0380)
5156 int sign, j1, j2, imm1, imm2;
5159 sign =
sbits (insn1, 10, 10);
5160 imm1 =
bits (insn1, 0, 5);
5161 imm2 =
bits (insn2, 0, 10);
5162 j1 =
bit (insn2, 13);
5163 j2 =
bit (insn2, 11);
5165 offset = (sign << 20) + (j2 << 19) + (j1 << 18);
5166 offset += (imm1 << 12) + (imm2 << 1);
5168 if (last_breakpoint > 0)
5172 breaks[1] = loc +
offset;
5184 if ((insn1 & 0xfff0) == 0xe840
5185 || ((insn1 & 0xfff0) == 0xe8c0 && (insn2 & 0x00c0) == 0x0040))
5191 if (insn_count == atomic_sequence_length)
5200 && (breaks[1] == breaks[0]
5201 || (breaks[1] >= pc && breaks[1] < loc)))
5202 last_breakpoint = 0;
5205 for (index = 0; index <= last_breakpoint; index++)
5224 int last_breakpoint = 0;
5225 const int atomic_sequence_length = 16;
5232 if ((insn & 0xff9000f0) != 0xe1900090)
5237 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
5245 if (
bits (insn, 24, 27) == 0xa)
5247 if (last_breakpoint > 0)
5262 if ((insn & 0xff9000f0) == 0xe1800090)
5267 if (insn_count == atomic_sequence_length)
5276 && (breaks[1] == breaks[0]
5277 || (breaks[1] >= pc && breaks[1] < loc)))
5278 last_breakpoint = 0;
5281 for (index = 0; index <= last_breakpoint; index++)
5323 int old_len,
int new_len)
5326 int bytes_to_read = new_len - old_len;
5329 memcpy (new_buf + bytes_to_read, buf, old_len);
5343 #define MAX_IT_BLOCK_PREFIX 14
5347 #define IT_SCAN_THRESHOLD 32
5360 int i, any, last_it, last_it_count;
5382 && func_start > boundary)
5383 boundary = func_start;
5398 for (i = 0; i < buf_len; i += 2)
5401 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5433 for (i = 0; i < buf_len -
sizeof (buf) && ! definite; i += 2)
5454 buf_len = bpaddr - boundary;
5463 buf_len = bpaddr - boundary;
5474 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5479 else if (inst1 & 0x0002)
5481 else if (inst1 & 0x0004)
5495 if (last_it_count < 1)
5501 return bpaddr - buf_len + last_it;
5527 #define ARM_NOP 0xe1a00000
5528 #define THUMB_NOP 0x4600
5556 (
unsigned long) from);
5564 regno, (
unsigned long) ret);
5577 return (ps & t_bit) == 0;
5611 else if ((val & 2) == 0)
5620 warning (
_(
"Single-stepping BX to non-word-aligned ARM instruction."));
5662 (
unsigned long) val);
5682 warning (
_(
"Instruction wrote to PC in an unexpected way when "
5683 "single-stepping"));
5688 _(
"Invalid argument to displaced_write_reg"));
5697 regno, (
unsigned long) val);
5711 uint32_t lowbit = 1;
5713 while (bitmask != 0)
5717 for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1)
5723 mask = lowbit * 0xf;
5725 if ((insn & mask) == mask)
5743 "opcode/class '%s' unmodified\n", (
unsigned long) insn,
5753 uint16_t insn2,
const char *iname,
5758 "opcode/class '%s' unmodified\n", insn1, insn2,
5777 "opcode/class '%s' unmodified\n", insn,
5819 unsigned int rn =
bits (insn, 16, 19);
5826 (
unsigned long) insn);
5828 dsc->
modinsn[0] = insn & 0xfff0ffff;
5839 unsigned int rn =
bits (insn1, 0, 3);
5840 unsigned int u_bit =
bit (insn1, 7);
5841 int imm12 =
bits (insn2, 0, 11);
5851 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
5852 (
unsigned int) dsc->
insn_addr, u_bit ?
'+' :
'-',
5875 dsc->
modinsn[0] = insn1 & 0xfff0;
5914 unsigned int rn =
bits (insn, 16, 19);
5915 unsigned int rm =
bits (insn, 0, 3);
5923 (
unsigned long) insn);
5925 dsc->
modinsn[0] = (insn & 0xfff0fff0) | 0x1;
5942 if (dsc->
u.
ldst.writeback)
5949 int writeback,
unsigned int rn)
5964 rn_val = rn_val & 0xfffffffc;
5967 dsc->
u.
ldst.writeback = writeback;
5968 dsc->
u.
ldst.rn = rn;
5978 unsigned int rn =
bits (insn, 16, 19);
5985 "load/store insn %.8lx\n", (
unsigned long) insn);
5987 dsc->
modinsn[0] = insn & 0xfff0ffff;
5996 uint16_t insn2,
struct regcache *regs,
5999 unsigned int rn =
bits (insn1, 0, 3);
6003 "copro load/store", dsc);
6007 "load/store insn %.4x%.4x\n", insn1, insn2);
6009 dsc->
modinsn[0] = insn1 & 0xfff0;
6043 next_insn_addr |= 0x1;
6057 unsigned int cond,
int exchange,
int link,
long offset)
6069 dsc->
u.
branch.exchange = exchange;
6072 if (link && exchange)
6087 unsigned int cond =
bits (insn, 28, 31);
6088 int exchange = (cond == 0xf);
6089 int link = exchange ||
bit (insn, 24);
6094 "%.8lx\n", (exchange) ?
"blx" : (link) ?
"bl" :
"b",
6095 (
unsigned long) insn);
6099 offset = (
bits (insn, 0, 23) << 2) | (
bit (insn, 24) << 1) | 1;
6101 offset =
bits (insn, 0, 23) << 2;
6103 if (
bit (offset, 25))
6104 offset = offset | ~0x3ffffff;
6114 uint16_t insn2,
struct regcache *regs,
6117 int link =
bit (insn2, 14);
6118 int exchange = link && !
bit (insn2, 12);
6121 int j1 =
bit (insn2, 13);
6122 int j2 =
bit (insn2, 11);
6123 int s =
sbits (insn1, 10, 10);
6124 int i1 = !(j1 ^
bit (insn1, 10));
6125 int i2 = !(j2 ^
bit (insn1, 10));
6127 if (!link && !exchange)
6129 offset = (
bits (insn2, 0, 10) << 1);
6130 if (
bit (insn2, 12))
6132 offset |= (
bits (insn1, 0, 9) << 12)
6140 offset |= (
bits (insn1, 0, 5) << 12)
6144 cond =
bits (insn1, 6, 9);
6149 offset = (
bits (insn1, 0, 9) << 12);
6150 offset |= ((i2 << 22) | (i1 << 23) | (s << 24));
6151 offset |= exchange ?
6152 (
bits (insn2, 1, 10) << 2) : (
bits (insn2, 0, 10) << 1);
6157 "%.4x %.4x with offset %.8lx\n",
6158 link ? (exchange) ?
"blx" :
"bl" :
"b",
6159 insn1, insn2, offset);
6172 unsigned int cond = 0;
6174 unsigned short bit_12_15 =
bits (insn, 12, 15);
6177 if (bit_12_15 == 0xd)
6180 offset =
sbits ((insn << 1), 0, 8);
6181 cond =
bits (insn, 8, 11);
6183 else if (bit_12_15 == 0xe)
6185 offset =
sbits ((insn << 1), 0, 11);
6191 "displaced: copying b immediate insn %.4x "
6192 "with offset %d\n", insn, offset);
6211 unsigned int cond,
unsigned int rm)
6235 unsigned int cond =
bits (insn, 28, 31);
6238 int link =
bit (insn, 5);
6239 unsigned int rm =
bits (insn, 0, 3);
6243 (
unsigned long) insn);
6256 int link =
bit (insn, 7);
6257 unsigned int rm =
bits (insn, 3, 6);
6261 (
unsigned short) insn);
6287 unsigned int rn =
bits (insn, 16, 19);
6288 unsigned int rd =
bits (insn, 12, 15);
6289 unsigned int op =
bits (insn, 21, 24);
6290 int is_mov = (op == 0xd);
6298 "%.8lx\n", is_mov ?
"move" :
"ALU",
6299 (
unsigned long) insn);
6322 dsc->
modinsn[0] = insn & 0xfff00fff;
6324 dsc->
modinsn[0] = (insn & 0xfff00fff) | 0x10000;
6333 uint16_t insn2,
struct regcache *regs,
6336 unsigned int op =
bits (insn1, 5, 8);
6337 unsigned int rn, rm, rd;
6340 rn =
bits (insn1, 0, 3);
6341 rm =
bits (insn2, 0, 3);
6342 rd =
bits (insn2, 8, 11);
6352 "ALU", insn1, insn2);
6375 dsc->
modinsn[1] = ((insn2 & 0xf0f0) | 0x1);
6394 for (i = 0; i < 3; i++)
6403 unsigned int rd,
unsigned int rn,
unsigned int rm)
6437 unsigned int op =
bits (insn, 21, 24);
6438 int is_mov = (op == 0xd);
6445 is_mov ?
"move" :
"ALU", (
unsigned long) insn);
6448 dsc->
modinsn[0] = (insn & 0xfff00ff0) | 0x2;
6450 dsc->
modinsn[0] = (insn & 0xfff00ff0) | 0x10002;
6464 rm =
bits (insn, 3, 6);
6465 rd = (
bit (insn, 7) << 3) |
bits (insn, 0, 2);
6472 (
unsigned short) insn);
6474 dsc->
modinsn[0] = ((insn & 0xff00) | 0x10);
6491 for (i = 0; i < 4; i++)
6500 unsigned int rd,
unsigned int rn,
unsigned int rm,
6504 ULONGEST rd_val, rn_val, rm_val, rs_val;
6520 for (i = 0; i < 4; i++)
6540 unsigned int op =
bits (insn, 21, 24);
6541 int is_mov = (op == 0xd);
6542 unsigned int rd, rn, rm, rs;
6549 "%.8lx\n", is_mov ?
"move" :
"ALU",
6550 (
unsigned long) insn);
6552 rn =
bits (insn, 16, 19);
6553 rm =
bits (insn, 0, 3);
6554 rs =
bits (insn, 8, 11);
6555 rd =
bits (insn, 12, 15);
6558 dsc->
modinsn[0] = (insn & 0xfff000f0) | 0x302;
6560 dsc->
modinsn[0] = (insn & 0xfff000f0) | 0x10302;
6573 ULONGEST rt_val, rt_val2 = 0, rn_val;
6576 if (dsc->
u.
ldst.xfersize == 8)
6581 if (dsc->
u.
ldst.xfersize > 4)
6584 if (!dsc->
u.
ldst.immed)
6588 if (dsc->
u.
ldst.writeback)
6592 if (dsc->
u.
ldst.xfersize == 8)
6605 if (dsc->
u.
ldst.xfersize > 4)
6608 if (!dsc->
u.
ldst.immed)
6610 if (!dsc->
u.
ldst.restore_r4)
6614 if (dsc->
u.
ldst.writeback)
6625 unsigned int op1 =
bits (insn, 20, 24);
6626 unsigned int op2 =
bits (insn, 5, 6);
6627 unsigned int rt =
bits (insn, 12, 15);
6628 unsigned int rn =
bits (insn, 16, 19);
6629 unsigned int rm =
bits (insn, 0, 3);
6630 char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
6631 char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
6632 int immed = (op1 & 0x4) != 0;
6634 ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0;
6641 "insn %.8lx\n", unpriveleged ?
"unpriveleged " :
"",
6642 (
unsigned long) insn);
6644 opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4;
6648 _(
"copy_extra_ld_st: instruction decode error"));
6657 if (bytesize[opcode] == 8)
6664 if (bytesize[opcode] == 8)
6671 dsc->
u.
ldst.xfersize = bytesize[opcode];
6672 dsc->
u.
ldst.rn = rn;
6673 dsc->
u.
ldst.immed = immed;
6674 dsc->
u.
ldst.writeback =
bit (insn, 24) == 0 ||
bit (insn, 21) != 0;
6675 dsc->
u.
ldst.restore_r4 = 0;
6681 dsc->
modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6686 dsc->
modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6698 int immed,
int writeback,
int size,
int usermode,
6699 int rt,
int rm,
int rn)
6701 ULONGEST rt_val, rn_val, rm_val = 0;
6721 dsc->
u.
ldst.rn = rn;
6722 dsc->
u.
ldst.immed = immed;
6723 dsc->
u.
ldst.writeback = writeback;
6752 uint16_t insn2,
struct regcache *regs,
6755 unsigned int u_bit =
bit (insn1, 7);
6756 unsigned int rt =
bits (insn2, 12, 15);
6757 int imm12 =
bits (insn2, 0, 11);
6762 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
6763 (
unsigned int) dsc->
insn_addr, rt, u_bit ?
'+' :
'-',
6784 pc_val = pc_val & 0xfffffffc;
6792 dsc->
u.
ldst.immed = 0;
6793 dsc->
u.
ldst.writeback = 0;
6794 dsc->
u.
ldst.restore_r4 = 0;
6808 uint16_t insn2,
struct regcache *regs,
6810 int writeback,
int immed)
6812 unsigned int rt =
bits (insn2, 12, 15);
6813 unsigned int rn =
bits (insn1, 0, 3);
6814 unsigned int rm =
bits (insn2, 0, 3);
6824 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
6825 rt, rn, insn1, insn2);
6830 dsc->
u.
ldst.restore_r4 = 0;
6837 dsc->
modinsn[0] = (insn1 & 0xfff0) | 0x2;
6838 dsc->
modinsn[1] = insn2 & 0x0fff;
6845 dsc->
modinsn[0] = (insn1 & 0xfff0) | 0x2;
6846 dsc->
modinsn[1] = (insn2 & 0x0ff0) | 0x3;
6859 int load,
int size,
int usermode)
6861 int immed = !
bit (insn, 25);
6862 int writeback = (
bit (insn, 24) == 0 ||
bit (insn, 21) != 0);
6863 unsigned int rt =
bits (insn, 12, 15);
6864 unsigned int rn =
bits (insn, 16, 19);
6865 unsigned int rm =
bits (insn, 0, 3);
6872 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
6873 load ? (size == 1 ?
"ldrb" :
"ldr")
6874 : (size == 1 ?
"strb" :
"str"), usermode ?
"t" :
"",
6876 (
unsigned long) insn);
6879 usermode, rt, rm, rn);
6883 dsc->
u.
ldst.restore_r4 = 0;
6889 dsc->
modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6894 dsc->
modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6899 dsc->
u.
ldst.restore_r4 = 1;
6908 dsc->
modinsn[5] = (insn & 0xfff00fff) | 0x20000;
6910 dsc->
modinsn[5] = (insn & 0xfff00ff0) | 0x20003;
6944 int inc = dsc->
u.
block.increment;
6945 int bump_before = dsc->
u.
block.before ? (inc ? 4 : -4) : 0;
6946 int bump_after = dsc->
u.
block.before ? 0 : (inc ? 4 : -4);
6947 uint32_t regmask = dsc->
u.
block.regmask;
6948 int regno = inc ? 0 : 15;
6950 int exception_return = dsc->
u.
block.load && dsc->
u.
block.user
6951 && (regmask & 0x8000) != 0;
6961 if (exception_return)
6962 error (
_(
"Cannot single-step exception return"));
6969 "%s %s %s\n", dsc->
u.
block.load ?
"ldm" :
"stm",
6970 dsc->
u.
block.increment ?
"inc" :
"dec",
6971 dsc->
u.
block.before ?
"before" :
"after");
6978 while (regno <=
ARM_PC_REGNUM && (regmask & (1 << regno)) == 0)
6981 while (regno >= 0 && (regmask & (1 << regno)) == 0)
6984 xfer_addr += bump_before;
6989 xfer_addr += bump_after;
6991 regmask &= ~(1 << regno);
6994 if (dsc->
u.
block.writeback)
7014 if (!store_executed)
7017 if (dsc->
u.
block.increment)
7019 pc_stored_at = dsc->
u.
block.xfer_addr + 4 * transferred_regs;
7026 pc_stored_at = dsc->
u.
block.xfer_addr;
7034 offset = pc_val - stm_insn_addr;
7038 "STM instruction\n", offset);
7059 unsigned int regs_loaded =
bitcount (mask);
7060 unsigned int num_to_shuffle = regs_loaded, clobbered;
7069 clobbered = (1 << num_to_shuffle) - 1;
7071 while (num_to_shuffle > 0)
7073 if ((mask & (1 << write_reg)) != 0)
7075 unsigned int read_reg = num_to_shuffle - 1;
7077 if (read_reg != write_reg)
7083 "loaded register r%d to r%d\n"), read_reg,
7088 "r%d already in the right place\n"),
7091 clobbered &= ~(1 << write_reg);
7100 for (write_reg = 0; clobbered != 0; write_reg++)
7102 if ((clobbered & (1 << write_reg)) != 0)
7108 "clobbered register r%d\n"), write_reg);
7109 clobbered &= ~(1 << write_reg);
7114 if (dsc->
u.
block.writeback)
7118 if (dsc->
u.
block.increment)
7119 new_rn_val += regs_loaded * 4;
7121 new_rn_val -= regs_loaded * 4;
7136 int load =
bit (insn, 20);
7137 int user =
bit (insn, 22);
7138 int increment =
bit (insn, 23);
7139 int before =
bit (insn, 24);
7140 int writeback =
bit (insn, 21);
7141 int rn =
bits (insn, 16, 19);
7150 warning (
_(
"displaced: Unpredictable LDM or STM with "
7151 "base register r15"));
7157 "%.8lx\n", (
unsigned long) insn);
7162 dsc->
u.
block.load = load;
7163 dsc->
u.
block.user = user;
7164 dsc->
u.
block.increment = increment;
7165 dsc->
u.
block.before = before;
7166 dsc->
u.
block.writeback = writeback;
7169 dsc->
u.
block.regmask = insn & 0xffff;
7173 if ((insn & 0xffff) == 0xffff)
7190 unsigned int regmask = insn & 0xffff;
7191 unsigned int num_in_list =
bitcount (regmask), new_regmask,
bit = 1;
7192 unsigned int to = 0,
from = 0, i, new_rn;
7194 for (i = 0; i < num_in_list; i++)
7216 new_regmask = (1 << num_in_list) - 1;
7220 "{..., pc}: original reg list %.4x, modified "
7221 "list %.4x\n"), rn, writeback ?
"!" :
"",
7222 (
int) insn & 0xffff, new_regmask);
7224 dsc->
modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff);
7250 int rn =
bits (insn1, 0, 3);
7251 int load =
bit (insn1, 4);
7252 int writeback =
bit (insn1, 5);
7261 warning (
_(
"displaced: Unpredictable LDM or STM with "
7262 "base register r15"));
7264 "unpredictable ldm/stm", dsc);
7269 "%.4x%.4x\n", insn1, insn2);
7272 dsc->
u.
block.regmask = (insn2 & 0xdfff);
7275 dsc->
u.
block.load = load;
7277 dsc->
u.
block.increment =
bit (insn1, 7);
7279 dsc->
u.
block.writeback = writeback;
7285 if (dsc->
u.
block.regmask == 0xffff)
7292 unsigned int regmask = dsc->
u.
block.regmask;
7293 unsigned int num_in_list =
bitcount (regmask), new_regmask,
bit = 1;
7294 unsigned int to = 0,
from = 0, i, new_rn;
7296 for (i = 0; i < num_in_list; i++)
7302 new_regmask = (1 << num_in_list) - 1;
7306 "{..., pc}: original reg list %.4x, modified "
7307 "list %.4x\n"), rn, writeback ?
"!" :
"",
7308 (
int) dsc->
u.
block.regmask, new_regmask);
7311 dsc->
modinsn[1] = (new_regmask & 0xffff);
7338 "%.8lx\n", (
unsigned long) resume_addr);
7359 if (dsc->
u.
svc.copy_svc_os)
7360 return dsc->
u.
svc.copy_svc_os (gdbarch, regs, dsc);
7375 (
unsigned long) insn);
7404 "displaced: copying undefined insn %.8lx\n",
7405 (
unsigned long) insn);
7419 "%.4x %.4x\n", (
unsigned short) insn1,
7420 (
unsigned short) insn2);
7437 "%.8lx\n", (
unsigned long) insn);
7452 unsigned int op1 =
bits (insn, 20, 26), op2 =
bits (insn, 4, 7);
7453 unsigned int rn =
bits (insn, 16, 19);
7455 if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0)
7457 else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1)
7459 else if ((op1 & 0x60) == 0x20)
7461 else if ((op1 & 0x71) == 0x40)
7464 else if ((op1 & 0x77) == 0x41)
7466 else if ((op1 & 0x77) == 0x45)
7468 else if ((op1 & 0x77) == 0x51)
7475 else if ((op1 & 0x77) == 0x55)
7477 else if (op1 == 0x57)
7486 else if ((op1 & 0x63) == 0x43)
7488 else if ((op2 & 0x1) == 0x0)
7489 switch (op1 & ~0x80)
7495 case 0x71:
case 0x75:
7498 case 0x63:
case 0x67:
case 0x73:
case 0x77:
7512 if (
bit (insn, 27) == 0)
7515 else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20))
7523 case 0x4:
case 0x5:
case 0x6:
case 0x7:
7527 switch ((insn & 0xe00000) >> 21)
7529 case 0x1:
case 0x3:
case 0x4:
case 0x5:
case 0x6:
case 0x7:
7542 int rn_f = (
bits (insn, 16, 19) == 0xf);
7543 switch ((insn & 0xe00000) >> 21)
7553 case 0x4:
case 0x5:
case 0x6:
case 0x7:
7567 if (
bits (insn, 16, 19) == 0xf)
7597 unsigned int op2 =
bits (insn, 4, 6);
7598 unsigned int op =
bits (insn, 21, 22);
7599 unsigned int op1 =
bits (insn, 16, 19);
7649 switch (
bits (insn, 20, 24))
7657 case 0x12:
case 0x16:
7665 uint32_t op1 =
bits (insn, 20, 24), op2 =
bits (insn, 4, 7);
7667 if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0)
7669 else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1)
7671 else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0)
7673 else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8)
7675 else if ((op1 & 0x10) == 0x00 && op2 == 0x9)
7677 else if ((op1 & 0x10) == 0x10 && op2 == 0x9)
7679 else if (op2 == 0xb || (op2 & 0xd) == 0xd)
7694 int a =
bit (insn, 25), b =
bit (insn, 4);
7695 uint32_t op1 =
bits (insn, 20, 24);
7696 int rn_f =
bits (insn, 16, 19) == 0xf;
7698 if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02)
7699 || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b))
7701 else if ((!a && (op1 & 0x17) == 0x02)
7702 || (a && (op1 & 0x17) == 0x02 && !b))
7704 else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03)
7705 || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b))
7707 else if ((!a && (op1 & 0x17) == 0x03)
7708 || (a && (op1 & 0x17) == 0x03 && !b))
7710 else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06)
7711 || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b))
7713 else if ((!a && (op1 & 0x17) == 0x06)
7714 || (a && (op1 & 0x17) == 0x06 && !b))
7716 else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07)
7717 || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b))
7719 else if ((!a && (op1 & 0x17) == 0x07)
7720 || (a && (op1 & 0x17) == 0x07 && !b))
7731 switch (
bits (insn, 20, 24))
7733 case 0x00:
case 0x01:
case 0x02:
case 0x03:
7736 case 0x04:
case 0x05:
case 0x06:
case 0x07:
7739 case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
7740 case 0x0c:
case 0x0d:
case 0x0e:
case 0x0f:
7742 "decode/pack/unpack/saturate/reverse", dsc);
7745 if (
bits (insn, 5, 7) == 0)
7747 if (
bits (insn, 12, 15) == 0xf)
7755 case 0x1a:
case 0x1b:
7756 if (
bits (insn, 5, 6) == 0x2)
7761 case 0x1c:
case 0x1d:
7762 if (
bits (insn, 5, 6) == 0x0)
7764 if (
bits (insn, 0, 3) == 0xf)
7772 case 0x1e:
case 0x1f:
7773 if (
bits (insn, 5, 6) == 0x2)
7799 unsigned int opcode =
bits (insn, 20, 24);
7803 case 0x04:
case 0x05:
7806 case 0x08:
case 0x0a:
case 0x0c:
case 0x0e:
7807 case 0x12:
case 0x16:
7810 case 0x09:
case 0x0b:
case 0x0d:
case 0x0f:
7811 case 0x13:
case 0x17:
7814 case 0x10:
case 0x14:
case 0x18:
case 0x1c:
7815 case 0x11:
case 0x15:
case 0x19:
case 0x1d:
7829 uint16_t insn2,
struct regcache *regs,
7834 unsigned int op =
bits (insn1, 5, 8);
7835 unsigned int rn =
bits (insn1, 0, 3);
7837 if (op == 0x2 && rn == 0xf)
7841 "dp (shift reg)", dsc);
7850 uint16_t insn2,
struct regcache *regs,
7853 unsigned int opcode =
bits (insn1, 4, 8);
7857 case 0x04:
case 0x05:
7859 "vfp/neon vmov", dsc);
7861 case 0x08:
case 0x0c:
7862 case 0x0a:
case 0x0e:
7863 case 0x12:
case 0x16:
7865 "vfp/neon vstm/vpush", dsc);
7867 case 0x09:
case 0x0d:
7868 case 0x0b:
case 0x0f:
7869 case 0x13:
case 0x17:
7871 "vfp/neon vldm/vpop", dsc);
7873 case 0x10:
case 0x14:
case 0x18:
case 0x1c:
7876 case 0x11:
case 0x15:
case 0x19:
case 0x1d:
7888 unsigned int op1 =
bits (insn, 20, 25);
7889 int op =
bit (insn, 4);
7890 unsigned int coproc =
bits (insn, 8, 11);
7891 unsigned int rn =
bits (insn, 16, 19);
7893 if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa)
7895 else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00
7896 && (coproc & 0xe) != 0xa)
7899 else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00
7900 && (coproc & 0xe) != 0xa)
7903 else if ((op1 & 0x3e) == 0x00)
7905 else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa)
7907 else if (op1 == 0x04 && (coproc & 0xe) != 0xa)
7909 else if (op1 == 0x05 && (coproc & 0xe) != 0xa)
7911 else if ((op1 & 0x30) == 0x20 && !op)
7913 if ((coproc & 0xe) == 0xa)
7918 else if ((op1 & 0x30) == 0x20 && op)
7920 else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa)
7922 else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa)
7924 else if ((op1 & 0x30) == 0x30)
7932 uint16_t insn2,
struct regcache *regs,
7935 unsigned int coproc =
bits (insn2, 8, 11);
7936 unsigned int op1 =
bits (insn1, 4, 9);
7937 unsigned int bit_5_8 =
bits (insn1, 5, 8);
7938 unsigned int bit_9 =
bit (insn1, 9);
7939 unsigned int bit_4 =
bit (insn1, 4);
7940 unsigned int rn =
bits (insn1, 0, 3);
7946 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
7948 else if (bit_5_8 == 0)
7953 if ((coproc & 0xe) == 0xa)
7994 int rd,
unsigned int imm)
7998 dsc->
modinsn[0] = (0x3000 | (rd << 8) | imm);
8010 unsigned int rd =
bits (insn, 8, 10);
8011 unsigned int imm8 =
bits (insn, 0, 7);
8015 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
8023 uint16_t insn2,
struct regcache *regs,
8026 unsigned int rd =
bits (insn2, 8, 11);
8031 unsigned int imm_3_8 = insn2 & 0x70ff;
8032 unsigned int imm_i = insn1 & 0x0400;
8036 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
8037 rd, imm_i, imm_3_8, insn1, insn2);
8042 dsc->
modinsn[0] = (0xf1a0 | rd | imm_i);
8043 dsc->
modinsn[1] = ((rd << 8) | imm_3_8);
8048 dsc->
modinsn[0] = (0xf100 | rd | imm_i);
8049 dsc->
modinsn[1] = ((rd << 8) | imm_3_8);
8063 unsigned int rt =
bits (insn1, 8, 10);
8065 int imm8 = (
bits (insn1, 0, 7) << 2);
8079 "displaced: copying thumb ldr r%d [pc #%d]\n"
8088 pc = pc & 0xfffffffc;
8094 dsc->
u.
ldst.xfersize = 4;
8096 dsc->
u.
ldst.immed = 0;
8097 dsc->
u.
ldst.writeback = 0;
8098 dsc->
u.
ldst.restore_r4 = 0;
8114 int non_zero =
bit (insn1, 11);
8115 unsigned int imm5 = (
bit (insn1, 9) << 6) | (
bits (insn1, 3, 7) << 1);
8117 int rn =
bits (insn1, 0, 2);
8120 dsc->
u.
branch.cond = (rn_val && non_zero) || (!rn_val && !non_zero);
8127 dsc->
u.
branch.dest = from + 4 + imm5;
8130 dsc->
u.
branch.dest = from + 2;
8137 " insn %.4x to %.8lx\n", non_zero ?
"cbnz" :
"cbz",
8138 rn, rn_val, insn1, dsc->
u.
branch.dest);
8149 uint16_t insn2,
struct regcache *regs,
8153 int is_tbh =
bit (insn2, 4);
8177 " offset 0x%x\n", is_tbh ?
"tbh" :
"tbb",
8178 (
unsigned int) rn_val, (
unsigned int) rm_val,
8179 (
unsigned int) halfwords);
8213 dsc->
u.
block.regmask = insn1 & 0x00ff;
8238 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
8239 dsc->
u.
block.regmask, insn1);
8241 if (dsc->
u.
block.regmask == 0xff)
8245 dsc->
modinsn[0] = (insn1 & 0xfeff);
8255 unsigned int new_regmask,
bit = 1;
8256 unsigned int to = 0,
from = 0, i, new_rn;
8258 for (i = 0; i < num_in_list + 1; i++)
8261 new_regmask = (1 << (num_in_list + 1)) - 1;
8265 "{..., pc}: original reg list %.4x,"
8266 " modified list %.4x\n"),
8267 (
int) dsc->
u.
block.regmask, new_regmask);
8269 dsc->
u.
block.regmask |= 0x8000;
8270 dsc->
u.
block.writeback = 0;
8273 dsc->
modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff);
8286 unsigned short op_bit_12_15 =
bits (insn1, 12, 15);
8287 unsigned short op_bit_10_11 =
bits (insn1, 10, 11);
8291 switch (op_bit_12_15)
8294 case 0:
case 1:
case 2:
case 3:
8296 "shift/add/sub/mov/cmp",
8300 switch (op_bit_10_11)
8309 unsigned short op =
bits (insn1, 7, 9);
8310 if (op == 6 || op == 7)
8312 else if (
bits (insn1, 6, 7) != 0)
8323 case 5:
case 6:
case 7:
case 8:
case 9:
8327 if (op_bit_10_11 < 2)
8334 switch (
bits (insn1, 8, 11))
8336 case 1:
case 3:
case 9:
case 11:
8346 if (
bits (insn1, 0, 3))
8361 if (op_bit_10_11 < 2)
8367 if (
bits (insn1, 9, 11) != 7)
8381 _(
"thumb_process_displaced_16bit_insn: Instruction decode error"));
8386 uint16_t insn1, uint16_t insn2,
8390 int rt =
bits (insn2, 12, 15);
8391 int rn =
bits (insn1, 0, 3);
8392 int op1 =
bits (insn1, 7, 8);
8395 switch (
bits (insn1, 5, 6))
8414 "ldrb{reg, immediate}/ldrbt",
8422 "pld/unalloc memhint", dsc);
8435 int insn2_bit_8_11 =
bits (insn2, 8, 11);
8439 else if (op1 == 0x1)
8444 if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9)
8447 dsc,
bit (insn2, 8), 1);
8448 else if (insn2_bit_8_11 == 0xe)
8467 uint16_t insn2,
struct regcache *regs,
8471 unsigned short op =
bit (insn2, 15);
8472 unsigned int op1 =
bits (insn1, 11, 12);
8478 switch (
bits (insn1, 9, 10))
8484 if (
bits (insn1, 7, 8) == 1 &&
bits (insn1, 4, 5) == 1
8485 &&
bits (insn2, 5, 7) == 0)
8492 "load/store dual/ex", dsc);
8496 switch (
bits (insn1, 7, 8))
8525 || (
bits (insn1, 7, 9) != 0x7))
8535 int op =
bits (insn1, 4, 8);
8536 int rn =
bits (insn1, 0, 3);
8537 if ((op == 0 || op == 0xa) && rn == 0xf)
8550 switch (
bits (insn1, 9, 10))
8558 "neon elt/struct load/store",
8562 switch (
bits (insn1, 7, 8))
8570 "mul/mua/diff", dsc);
8589 _(
"thumb_process_displaced_32bit_insn: Instruction decode error"));
8604 "at %.8lx\n", insn1, (
unsigned long) from);
8643 "at %.8lx\n", (
unsigned long) insn,
8644 (
unsigned long) from);
8646 if ((insn & 0xf0000000) == 0xf0000000)
8648 else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24))
8650 case 0x0:
case 0x1:
case 0x2:
case 0x3:
8654 case 0x4:
case 0x5:
case 0x6:
8662 case 0x8:
case 0x9:
case 0xa:
case 0xb:
8666 case 0xc:
case 0xd:
case 0xe:
case 0xf:
8673 _(
"arm_process_displaced_insn: Instruction decode error"));
8690 for (i = 0; i < dsc->
numinsns; i++)
8700 (
unsigned short)dsc->
modinsn[i]);
8703 (
unsigned long) to + offset);
8707 byte_order_for_code,
8758 dsc->
cleanup (gdbarch, regs, dsc);
8766 #include "bfd-in2.h"
8767 #include "libcoff.h"
8772 struct gdbarch *gdbarch = info->application_data;
8776 static asymbol *asym;
8777 static combined_entry_type ce;
8778 static struct coff_symbol_struct csym;
8779 static struct bfd fake_bfd;
8780 static bfd_target fake_target;
8782 if (csym.native == NULL)
8790 fake_target.flavour = bfd_target_coff_flavour;
8791 fake_bfd.xvec = &fake_target;
8792 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
8794 csym.symbol.the_bfd = &fake_bfd;
8795 csym.symbol.name =
"fake";
8796 asym = (asymbol *) & csym;
8800 info->symbols = &asym;
8803 info->symbols = NULL;
8805 if (info->endian == BFD_ENDIAN_BIG)
8806 return print_insn_big_arm (memaddr, info);
8808 return print_insn_little_arm (memaddr, info);
8840 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
8841 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
8842 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
8843 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
8858 static const unsigned char *
8875 unsigned short inst1;
8948 _(
"arm_extract_return_value: "
8949 "Floating point model not supported"));
8992 memcpy (valbuf, tmpbuf,
9139 _(
"arm_store_return_value: Floating "
9140 "point model not supported"));
9188 memcpy (tmpbuf, valbuf,
9216 for (i = 0; i < vfp_base_count; i++)
9218 if (reg_char ==
'q')
9222 writebuf + i * unit_length);
9226 readbuf + i * unit_length);
9233 xsnprintf (name_buf,
sizeof (name_buf),
"%c%d", reg_char, i);
9238 writebuf + i * unit_length);
9241 readbuf + i * unit_length);
9307 if (start_addr != 0)
9323 static char *table[15] =
9324 {
"r0",
"r1",
"r2",
"r3",
"r4",
"r5",
"r6",
"r7",
9325 "r8",
"r9",
"sl",
"fp",
"ip",
"sp",
"lr"
9328 int offset = strlen (name) - 2;
9330 for (regno = 0; regno <= 14; regno++)
9331 if (strcmp (&name[offset], table[regno]) == 0)
9338 namelen = strlen (name);
9339 if (name[0] ==
'_' && name[1] ==
'_'
9340 && ((namelen > 2 + strlen (
"_from_thumb")
9341 &&
startswith (name + namelen - strlen (
"_from_thumb"),
"_from_thumb"))
9342 || (namelen > 2 + strlen (
"_from_arm")
9343 &&
startswith (name + namelen - strlen (
"_from_arm"),
"_from_arm"))))
9346 int target_len = namelen - 2;
9351 if (name[namelen - 1] ==
'b')
9352 target_len -= strlen (
"_from_thumb");
9354 target_len -= strlen (
"_from_arm");
9356 target_name = alloca (target_len + 1);
9357 memcpy (target_name, name + 2, target_len);
9358 target_name[target_len] =
'\0';
9361 objfile = (sec == NULL) ? NULL : sec->
objfile;
9363 if (minsym.
minsym != NULL)
9376 \"set arm\" must be followed by an apporpriate subcommand.\n"));
9399 internal_error (__FILE__, __LINE__,
_(
"could not update architecture"));
9416 internal_error (__FILE__, __LINE__,
_(
"Invalid fp model accepted: %s."),
9431 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
9435 The current ARM floating point model is \"%s\".\n"),
9468 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
9480 _(
"The current execution mode assumed "
9481 "(when symbols are unavailable) is \"%s\".\n"),
9492 _(
"The current execution mode assumed "
9493 "(even when symbols are available) is \"%s\".\n"),
9516 && i >= num_regs && i < num_regs + 32)
9518 static const char *
const vfp_pseudo_names[] = {
9519 "s0",
"s1",
"s2",
"s3",
"s4",
"s5",
"s6",
"s7",
9520 "s8",
"s9",
"s10",
"s11",
"s12",
"s13",
"s14",
"s15",
9521 "s16",
"s17",
"s18",
"s19",
"s20",
"s21",
"s22",
"s23",
9522 "s24",
"s25",
"s26",
"s27",
"s28",
"s29",
"s30",
"s31",
9525 return vfp_pseudo_names[i -
num_regs];
9529 && i >= num_regs + 32 && i < num_regs + 32 + 16)
9531 static const char *
const neon_pseudo_names[] = {
9532 "q0",
"q1",
"q2",
"q3",
"q4",
"q5",
"q6",
"q7",
9533 "q8",
"q9",
"q10",
"q11",
"q12",
"q13",
"q14",
"q15",
9536 return neon_pseudo_names[i - num_regs - 32];
9556 gdb_assert (current < num_disassembly_options);
9559 set_arm_regname_option (current);
9568 return (val == C_THUMBEXT
9569 || val == C_THUMBSTAT
9570 || val == C_THUMBEXTFUNC
9571 || val == C_THUMBSTATFUNC
9572 || val == C_THUMBLABEL);
9585 if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type *)sym)->internal_elf_sym)
9586 == ST_BRANCH_TO_THUMB)
9603 for (i = 0; i < objfile->
obfd->section_count; i++)
9611 const char *
name = bfd_asymbol_name (sym);
9617 if (name[1] !=
'a' && name[1] !=
't' && name[1] !=
'd')
9627 objfile->
obfd->section_count,
9630 map_p = &data->section_maps[bfd_get_section (sym)->index];
9632 new_map_sym.
value = sym->value;
9633 new_map_sym.
type = name[1];
9643 if (prev_map_sym->
value >= sym->value)
9690 int offset, double_regnum;
9693 xsnprintf (name_buf,
sizeof (name_buf),
"d%d", regnum << 1);
9706 memcpy (buf + offset, reg_buf, 8);
9712 memcpy (buf + offset, reg_buf, 8);
9724 int offset, double_regnum;
9729 if (
gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
9741 offset = (regnum & 1) ? 0 : 4;
9743 offset = (regnum & 1) ? 4 : 0;
9745 xsnprintf (name_buf,
sizeof (name_buf),
"d%d", regnum >> 1);
9751 memcpy (buf, reg_buf + offset, 4);
9768 int offset, double_regnum;
9770 xsnprintf (name_buf,
sizeof (name_buf),
"d%d", regnum << 1);
9792 int offset, double_regnum;
9797 if (
gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48)
9807 offset = (regnum & 1) ? 0 : 4;
9809 offset = (regnum & 1) ? 4 : 0;
9811 xsnprintf (name_buf,
sizeof (name_buf),
"d%d", regnum >> 1);
9816 memcpy (reg_buf + offset, buf, 4);
9821 static struct value *
9824 const int *reg_p = baton;
9831 unsigned int elfosabi;
9834 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
9836 if (elfosabi == ELFOSABI_ARM)
9839 bfd_map_over_sections (abfd,
9914 static struct gdbarch *
9918 struct gdbarch *gdbarch;
9924 int vfp_register_count = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0;
9925 int have_wmmx_registers = 0;
9927 int have_fpa_registers = 1;
9935 int ei_osabi, e_flags;
9937 switch (bfd_get_flavour (info.
abfd))
9939 case bfd_target_aout_flavour:
9944 case bfd_target_coff_flavour:
9950 case bfd_target_elf_flavour:
9951 ei_osabi = elf_elfheader (info.
abfd)->e_ident[EI_OSABI];
9952 e_flags = elf_elfheader (info.
abfd)->e_flags;
9954 if (ei_osabi == ELFOSABI_ARM)
9961 else if (ei_osabi == ELFOSABI_NONE || ei_osabi == ELFOSABI_GNU)
9963 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
9964 int attr_arch, attr_profile;
9968 case EF_ARM_EABI_UNKNOWN:
9973 case EF_ARM_EABI_VER4:
9974 case EF_ARM_EABI_VER5:
9983 switch (bfd_elf_get_obj_attr_int (info.
abfd,
9987 case AEABI_VFP_args_base:
9993 case AEABI_VFP_args_vfp:
9999 case AEABI_VFP_args_toolchain:
10005 case AEABI_VFP_args_compatible:
10026 warning (
_(
"unknown ARM EABI version 0x%x"), eabi_ver);
10035 attr_arch = bfd_elf_get_obj_attr_int (info.
abfd, OBJ_ATTR_PROC,
10037 attr_profile = bfd_elf_get_obj_attr_int (info.
abfd,
10039 Tag_CPU_arch_profile);
10045 && (attr_arch == TAG_CPU_ARCH_V6_M
10046 || attr_arch == TAG_CPU_ARCH_V6S_M
10047 || attr_profile ==
'M'))
10054 int e_flags = elf_elfheader (info.
abfd)->e_flags;
10056 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
10064 case EF_ARM_SOFT_FLOAT:
10067 case EF_ARM_VFP_FLOAT:
10070 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
10076 if (e_flags & EF_ARM_BE8)
10092 static const char *
const arm_sp_names[] = {
"r13",
"sp", NULL };
10093 static const char *
const arm_lr_names[] = {
"r14",
"lr", NULL };
10094 static const char *
const arm_pc_names[] = {
"r15",
"pc", NULL };
10100 "org.gnu.gdb.arm.core");
10101 if (feature == NULL)
10104 "org.gnu.gdb.arm.m-profile");
10105 if (feature == NULL)
10140 "org.gnu.gdb.arm.fpa");
10141 if (feature != NULL)
10154 have_fpa_registers = 0;
10157 "org.gnu.gdb.xscale.iwmmxt");
10158 if (feature != NULL)
10160 static const char *
const iwmmxt_names[] = {
10161 "wR0",
"wR1",
"wR2",
"wR3",
"wR4",
"wR5",
"wR6",
"wR7",
10162 "wR8",
"wR9",
"wR10",
"wR11",
"wR12",
"wR13",
"wR14",
"wR15",
10163 "wCID",
"wCon",
"wCSSF",
"wCASF",
"",
"",
"",
"",
10164 "wCGR0",
"wCGR1",
"wCGR2",
"wCGR3",
"",
"",
"",
"",
10190 have_wmmx_registers = 1;
10197 "org.gnu.gdb.arm.vfp");
10198 if (feature != NULL)
10200 static const char *
const vfp_double_names[] = {
10201 "d0",
"d1",
"d2",
"d3",
"d4",
"d5",
"d6",
"d7",
10202 "d8",
"d9",
"d10",
"d11",
"d12",
"d13",
"d14",
"d15",
10203 "d16",
"d17",
"d18",
"d19",
"d20",
"d21",
"d22",
"d23",
10204 "d24",
"d25",
"d26",
"d27",
"d28",
"d29",
"d30",
"d31",
10210 for (i = 0; i < 32; i++)
10214 vfp_double_names[i]);
10218 if (!valid_p && i == 16)
10231 have_vfp_pseudos = 1;
10233 vfp_register_count = i;
10239 "org.gnu.gdb.arm.neon");
10240 if (feature != NULL)
10253 have_neon_pseudos = 1;
10286 if (best_arch != NULL)
10288 if (tdesc_data != NULL)
10304 || vfp_register_count == 16
10305 || vfp_register_count == 32);
10316 case BFD_ENDIAN_BIG:
10324 case BFD_ENDIAN_LITTLE:
10334 _(
"arm_gdbarch_init: bad byte order for float format"));
10452 if (tdep->
jb_pc >= 0)
10470 if (have_vfp_pseudos)
10476 int num_pseudos = 32;
10477 if (have_neon_pseudos)
10525 const char *setname;
10526 const char *setdesc;
10527 const char *
const *regnames;
10529 static char *helptext;
10530 char regdesc[1024], *rdptr = regdesc;
10531 size_t rest =
sizeof (regdesc);
10545 bfd_target_elf_flavour,
10562 _(
"Various ARM-specific commands."),
10563 &setarmcmdlist,
"set arm ", 0, &
setlist);
10566 _(
"Various ARM-specific commands."),
10567 &showarmcmdlist,
"show arm ", 0, &
showlist);
10570 parse_arm_disassembler_option (
"reg-names-std");
10578 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
10580 length = snprintf (rdptr, rest,
"%s - %s\n", setname, setdesc);
10585 if (!strcmp (setname,
"std"))
10588 set_arm_regname_option (i);
10597 _(
"The valid values are:\n"),
10599 _(
"The default is \"std\"."));
10605 _(
"Set the disassembly style."),
10606 _(
"Show the disassembly style."),
10611 &setarmcmdlist, &showarmcmdlist);
10614 _(
"Set usage of ARM 32-bit mode."),
10615 _(
"Show usage of ARM 32-bit mode."),
10616 _(
"When off, a 26-bit PC will be used."),
10620 &setarmcmdlist, &showarmcmdlist);
10624 _(
"Set the floating point type."),
10625 _(
"Show the floating point type."),
10626 _(
"auto - Determine the FP typefrom the OS-ABI.\n\
10627 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
10628 fpa - FPA co-processor (GCC compiled).\n\
10629 softvfp - Software FP with pure-endian doubles.\n\
10630 vfp - VFP co-processor."),
10632 &setarmcmdlist, &showarmcmdlist);
10637 _(
"Show the ABI."),
10639 &setarmcmdlist, &showarmcmdlist);
10645 _(
"Set the mode assumed when symbols are unavailable."),
10646 _(
"Show the mode assumed when symbols are unavailable."),
10648 &setarmcmdlist, &showarmcmdlist);
10651 _(
"Set the mode assumed even when symbols are available."),
10652 _(
"Show the mode assumed even when symbols are available."),
10654 &setarmcmdlist, &showarmcmdlist);
10658 _(
"Set ARM debugging."),
10659 _(
"Show ARM debugging."),
10660 _(
"When on, arm-specific debugging is enabled."),
10668 #define ARM_INSN_SIZE_BYTES 4
10669 #define THUMB_INSN_SIZE_BYTES 2
10670 #define THUMB2_INSN_SIZE_BYTES 4
10675 #define INSN_S_L_BIT_NUM 20
10677 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
10680 unsigned int reg_len = LENGTH; \
10683 REGS = XNEWVEC (uint32_t, reg_len); \
10684 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
10689 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
10692 unsigned int mem_len = LENGTH; \
10695 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
10696 memcpy(&MEMS->len, &RECORD_BUF[0], \
10697 sizeof(struct arm_mem_r) * LENGTH); \
10703 #define INSN_RECORDED(ARM_RECORD) \
10704 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
10737 sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t
len, uint32_t sbo)
10739 uint32_t ones =
bits (insn, bit_num - 1, (bit_num -1) + (len - 1));
10786 uint32_t reg_src1 = 0, reg_src2 = 0;
10787 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
10788 uint32_t opcode1 = 0;
10795 if (14 == arm_insn_r->
opcode || 10 == arm_insn_r->
opcode)
10806 u_regval[0] = u_regval[0] + 8;
10808 offset_8 = (immed_high << 4) | immed_low;
10810 if (14 == arm_insn_r->
opcode)
10812 tgt_mem_addr = u_regval[0] + offset_8;
10816 tgt_mem_addr = u_regval[0] - offset_8;
10820 record_buf_mem[0] = 2;
10821 record_buf_mem[1] = tgt_mem_addr;
10826 record_buf_mem[0] = 4;
10827 record_buf_mem[1] = tgt_mem_addr;
10828 record_buf_mem[2] = 4;
10829 record_buf_mem[3] = tgt_mem_addr + 4;
10833 else if (12 == arm_insn_r->
opcode || 8 == arm_insn_r->
opcode)
10842 if (15 == reg_src2)
10845 u_regval[0] = u_regval[0] + 8;
10848 if (12 == arm_insn_r->
opcode)
10850 tgt_mem_addr = u_regval[0] + u_regval[1];
10854 tgt_mem_addr = u_regval[1] - u_regval[0];
10858 record_buf_mem[0] = 2;
10859 record_buf_mem[1] = tgt_mem_addr;
10864 record_buf_mem[0] = 4;
10865 record_buf_mem[1] = tgt_mem_addr;
10866 record_buf_mem[2] = 4;
10867 record_buf_mem[3] = tgt_mem_addr + 4;
10871 else if (11 == arm_insn_r->
opcode || 15 == arm_insn_r->
opcode
10872 || 2 == arm_insn_r->
opcode || 6 == arm_insn_r->
opcode)
10878 offset_8 = (immed_high << 4) | immed_low;
10882 if (15 == arm_insn_r->
opcode || 6 == arm_insn_r->
opcode)
10884 tgt_mem_addr = u_regval[0] + offset_8;
10888 tgt_mem_addr = u_regval[0] - offset_8;
10892 record_buf_mem[0] = 2;
10893 record_buf_mem[1] = tgt_mem_addr;
10898 record_buf_mem[0] = 4;
10899 record_buf_mem[1] = tgt_mem_addr;
10900 record_buf_mem[2] = 4;
10901 record_buf_mem[3] = tgt_mem_addr + 4;
10908 else if (9 == arm_insn_r->
opcode || 13 == arm_insn_r->
opcode
10909 || 0 == arm_insn_r->
opcode || 4 == arm_insn_r->
opcode)
10918 if (13 == arm_insn_r->
opcode || 4 == arm_insn_r->
opcode)
10920 tgt_mem_addr = u_regval[0] + u_regval[1];
10924 tgt_mem_addr = u_regval[1] - u_regval[0];
10928 record_buf_mem[0] = 2;
10929 record_buf_mem[1] = tgt_mem_addr;
10934 record_buf_mem[0] = 4;
10935 record_buf_mem[1] = tgt_mem_addr;
10936 record_buf_mem[2] = 4;
10937 record_buf_mem[3] = tgt_mem_addr + 4;
10953 uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0;
10954 uint32_t record_buf[8], record_buf_mem[8];
10955 uint32_t reg_src1 = 0;
10956 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
10965 if (arm_insn_r->
cond)
10969 if (5 == ((opcode1 & 0xE0) >> 5))
10981 if (3 == opcode1 &&
bit (arm_insn_r->
arm_insn, 4))
10993 if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->
cond
10997 if (0 <= insn_op1 && 3 >= insn_op1)
11003 else if (4 <= insn_op1 && 15 >= insn_op1)
11019 if (!opcode1 && 2 == opcode2 && !
bit (arm_insn_r->
arm_insn, 20)
11026 if ((0 == insn_op1) || (2 == insn_op1))
11032 else if (1 == insn_op1)
11038 else if (3 == insn_op1)
11043 "instruction 0x%0x at address %s.\n"),
11058 else if (3 == insn_op1)
11088 "instruction 0x%0x at address %s.\n"),
11099 if (0 == insn_op1 || 1 == insn_op1)
11108 else if (2 == insn_op1)
11115 else if (3 == insn_op1)
11132 else if (3 == insn_op1)
11137 "instruction 0x%0x at address %s.\n"),
11165 if (8 == arm_insn_r->
opcode)
11167 record_buf_mem[0] = 4;
11172 record_buf_mem[0] = 1;
11174 record_buf_mem[1] = u_regval;
11179 else if (1 == insn_op1 && !
bit (arm_insn_r->
arm_insn, 20))
11185 else if (2 == insn_op1 && !
bit (arm_insn_r->
arm_insn, 20))
11189 record_buf[1] = record_buf[0] + 1;
11192 else if (3 == insn_op1 && !
bit (arm_insn_r->
arm_insn, 20))
11198 else if (
bit (arm_insn_r->
arm_insn, 20) && insn_op1 <= 3)
11208 if (24 == opcode1 &&
bit (arm_insn_r->
arm_insn, 21)
11218 "at address %s.\n"),arm_insn_r->
arm_insn,
11234 uint32_t record_buf[8], record_buf_mem[8];
11237 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
11238 uint32_t immed_high = 0, immed_low = 0, offset_8 = 0, tgt_mem_addr = 0;
11239 uint32_t opcode1 = 0;
11246 if (9 == arm_insn_r->
decode
11247 && ((4 <= arm_insn_r->
opcode && 7 >= arm_insn_r->
opcode)
11248 || (0 == arm_insn_r->
opcode || 1 == arm_insn_r->
opcode)))
11252 if (0 == arm_insn_r->
opcode || 1 == arm_insn_r->
opcode)
11259 else if (4 <= arm_insn_r->
opcode && 7 >= arm_insn_r->
opcode)
11269 && (11 == arm_insn_r->
decode || 13 == arm_insn_r->
decode))
11279 if (15 != reg_dest)
11286 record_buf[0] = reg_dest;
11291 else if ((9 == arm_insn_r->
opcode || 11 == arm_insn_r->
opcode)
11297 if (9 == arm_insn_r->
opcode)
11308 "0x%0x at address %s.\n"),
11314 else if (9 == arm_insn_r->
decode
11315 && (8 == arm_insn_r->
opcode || 10 == arm_insn_r->
opcode)
11325 if (8 == arm_insn_r->
opcode)
11327 record_buf_mem[0] = 4;
11332 record_buf_mem[0] = 1;
11334 record_buf_mem[1] = u_regval[0];
11339 else if (3 == arm_insn_r->
decode && 0x12 == opcode1
11343 if (9 == arm_insn_r->
opcode)
11352 else if (7 == arm_insn_r->
decode && 0x12 == opcode1)
11367 "0x%0x at address %s.\n"),arm_insn_r->
arm_insn,
11372 else if (11 == arm_insn_r->
decode
11381 else if (1 == arm_insn_r->
decode && 0x12 == opcode1
11389 else if (1 == arm_insn_r->
decode && 0x16 == opcode1
11398 && (8 == arm_insn_r->
opcode || 10 == arm_insn_r->
opcode)
11407 else if (arm_insn_r->
opcode <= 15)
11431 uint32_t record_buf[8], record_buf_mem[8];
11436 if ((9 == arm_insn_r->
opcode || 11 == arm_insn_r->
opcode)
11442 if (9 == arm_insn_r->
opcode)
11453 else if (arm_insn_r->
opcode <= 15)
11479 uint32_t reg_base , reg_dest;
11480 uint32_t offset_12, tgt_mem_addr;
11481 uint32_t record_buf[8], record_buf_mem[8];
11482 unsigned char wback;
11523 tgt_mem_addr = (uint32_t) u_regval + offset_12;
11528 tgt_mem_addr = (uint32_t) u_regval - offset_12;
11536 record_buf_mem[0] = 1;
11541 record_buf_mem[0] = 4;
11546 record_buf_mem[1] = tgt_mem_addr;
11548 record_buf_mem[1] = (uint32_t) u_regval;
11570 uint32_t shift_imm = 0;
11571 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
11572 uint32_t offset_12 = 0, tgt_mem_addr = 0;
11573 uint32_t record_buf[8], record_buf_mem[8];
11593 if (15 != reg_dest)
11600 record_buf[0] = reg_dest;
11619 if (15 == reg_src2)
11623 u_regval[0] = u_regval[0] + 8;
11629 tgt_mem_addr = u_regval[0] + u_regval[1];
11633 tgt_mem_addr = u_regval[1] - u_regval[0];
11636 switch (arm_insn_r->
opcode)
11650 record_buf_mem[0] = 4;
11665 record_buf_mem[0] = 1;
11672 record_buf_mem[1] = tgt_mem_addr;
11675 if (9 == arm_insn_r->
opcode || 11 == arm_insn_r->
opcode
11676 || 13 == arm_insn_r->
opcode || 15 == arm_insn_r->
opcode
11685 record_buf[0] = reg_src2;
11707 offset_12 = u_regval[0] << shift_imm;
11711 offset_12 = (!shift_imm)?0:u_regval[0] >> shift_imm;
11717 if (
bit (u_regval[0], 31))
11719 offset_12 = 0xFFFFFFFF;
11729 offset_12 = s_word >> shift_imm;
11739 offset_12 = (((
bit (u_regval[1], 29)) << 31) \
11740 | (u_regval[0]) >> 1);
11744 offset_12 = (u_regval[0] >> shift_imm) \
11746 (
sizeof(uint32_t) - shift_imm));
11759 tgt_mem_addr = u_regval[1] + offset_12;
11763 tgt_mem_addr = u_regval[1] - offset_12;
11766 switch (arm_insn_r->
opcode)
11780 record_buf_mem[0] = 4;
11795 record_buf_mem[0] = 1;
11802 record_buf_mem[1] = tgt_mem_addr;
11805 if (9 == arm_insn_r->
opcode || 11 == arm_insn_r->
opcode
11806 || 13 == arm_insn_r->
opcode || 15 == arm_insn_r->
opcode
11815 record_buf[0] = reg_src2;
11832 uint32_t register_count = 0, register_bits;
11833 uint32_t reg_base, addr_mode;
11834 uint32_t record_buf[24], record_buf_mem[48];
11854 while (register_bits)
11856 if (register_bits & 0x00000001)
11858 register_bits = register_bits >> 1;
11880 while (register_bits)
11882 if (register_bits & 0x00000001)
11884 register_bits = register_bits >> 1;
11891 record_buf_mem[1] = (uint32_t) u_regval
11896 record_buf_mem[1] = (uint32_t) u_regval;
11900 record_buf_mem[1] = (uint32_t) u_regval
11931 uint32_t record_buf[8];
11954 "0x%0x at address %s.\n"),arm_insn_r->
arm_insn,
11965 uint32_t bits_a, bit_c, bit_l, reg_t, reg_v;
11966 uint32_t record_buf[4];
11976 if (bit_l && bit_c)
11978 record_buf[0] = reg_t;
11981 else if (bit_l && !bit_c)
11984 if (bits_a == 0x00)
11987 record_buf[0] = reg_t;
11989 record_buf[0] = num_regs + (
bit (arm_insn_r->
arm_insn, 7) |
11995 else if (bits_a == 0x07)
12000 record_buf[0] = reg_t;
12004 else if (!bit_l && !bit_c)
12007 if (bits_a == 0x00)
12010 record_buf[0] = reg_t;
12012 record_buf[0] = num_regs + (
bit (arm_insn_r->
arm_insn, 7) |
12018 else if (bits_a == 0x07)
12024 else if (!bit_l && bit_c)
12027 if (!(bits_a & 0x04))
12029 record_buf[0] = (reg_v | (
bit (arm_insn_r->
arm_insn, 7) << 4))
12038 reg_v = reg_v | (
bit (arm_insn_r->
arm_insn, 7) << 4);
12040 record_buf[1] = reg_v + ARM_D0_REGNUM + 1;
12045 reg_v = reg_v | (
bit (arm_insn_r->
arm_insn, 7) << 4);
12061 uint32_t opcode, single_reg;
12062 uint8_t op_vldm_vstm;
12063 uint32_t record_buf[8], record_buf_mem[128];
12071 op_vldm_vstm = opcode & 0x1b;
12074 if ((opcode & 0x1e) == 0x04)
12084 uint8_t reg_m = (
bits (arm_insn_r->
arm_insn, 0, 3) << 1)
12089 record_buf[0] = num_regs + reg_m;
12090 record_buf[1] = num_regs + reg_m + 1;
12101 else if (op_vldm_vstm == 0x08 || op_vldm_vstm == 0x0a
12102 || op_vldm_vstm == 0x12)
12104 uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count;
12105 uint32_t memory_index = 0;
12110 imm_off32 = imm_off8 << 24;
12111 memory_count = imm_off8;
12114 start_address = u_regval;
12116 start_address = u_regval - imm_off32;
12120 record_buf[0] = reg_rn;
12124 while (memory_count > 0)
12128 record_buf_mem[memory_index] = start_address;
12129 record_buf_mem[memory_index + 1] = 4;
12130 start_address = start_address + 4;
12131 memory_index = memory_index + 2;
12135 record_buf_mem[memory_index] = start_address;
12136 record_buf_mem[memory_index + 1] = 4;
12137 record_buf_mem[memory_index + 2] = start_address + 4;
12138 record_buf_mem[memory_index + 3] = 4;
12139 start_address = start_address + 8;
12140 memory_index = memory_index + 4;
12147 else if (op_vldm_vstm == 0x09 || op_vldm_vstm == 0x0b
12148 || op_vldm_vstm == 0x13)
12150 uint32_t reg_count, reg_vd;
12151 uint32_t reg_index = 0;
12157 reg_vd = reg_vd | (
bit (arm_insn_r->
arm_insn, 22) << 4);
12159 reg_vd = (reg_vd << 1) |
bit (arm_insn_r->
arm_insn, 22);
12162 record_buf[reg_index++] =
bits (arm_insn_r->
arm_insn, 16, 19);
12164 while (reg_count > 0)
12167 record_buf[reg_index++] = num_regs + reg_vd + reg_count - 1;
12169 record_buf[reg_index++] =
ARM_D0_REGNUM + reg_vd + reg_count - 1;
12176 else if ((opcode & 0x13) == 0x10)
12178 uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count;
12179 uint32_t memory_index = 0;
12184 imm_off32 = imm_off8 << 24;
12185 memory_count = imm_off8;
12188 start_address = u_regval + imm_off32;
12190 start_address = u_regval - imm_off32;
12194 record_buf_mem[memory_index] = start_address;
12195 record_buf_mem[memory_index + 1] = 4;
12200 record_buf_mem[memory_index] = start_address;
12201 record_buf_mem[memory_index + 1] = 4;
12202 record_buf_mem[memory_index + 2] = start_address + 4;
12203 record_buf_mem[memory_index + 3] = 4;
12208 else if ((opcode & 0x13) == 0x11)
12210 uint32_t reg_vd =
bits (arm_insn_r->
arm_insn, 12, 15);
12214 reg_vd = reg_vd | (
bit (arm_insn_r->
arm_insn, 22) << 4);
12219 reg_vd = (reg_vd << 1) |
bit (arm_insn_r->
arm_insn, 22);
12220 record_buf[0] = num_regs + reg_vd;
12235 uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd;
12236 uint32_t record_buf[4];
12237 enum insn_types {INSN_T0, INSN_T1, INSN_T2, INSN_T3, INSN_INV};
12238 enum insn_types curr_insn_type = INSN_INV;
12246 opc1 = opc1 & 0x04;
12254 curr_insn_type = INSN_T0;
12256 curr_insn_type = INSN_T1;
12261 curr_insn_type = INSN_T1;
12263 curr_insn_type = INSN_T2;
12267 else if (opc1 == 0x01)
12270 curr_insn_type = INSN_T1;
12272 curr_insn_type = INSN_T2;
12275 else if (opc1 == 0x02 && !(opc3 & 0x01))
12280 curr_insn_type = INSN_T0;
12282 curr_insn_type = INSN_T1;
12287 curr_insn_type = INSN_T1;
12289 curr_insn_type = INSN_T2;
12293 else if (opc1 == 0x03)
12298 curr_insn_type = INSN_T0;
12300 curr_insn_type = INSN_T1;
12305 curr_insn_type = INSN_T1;
12307 curr_insn_type = INSN_T2;
12311 else if (opc1 == 0x0b)
12314 curr_insn_type = INSN_T1;
12316 curr_insn_type = INSN_T2;
12319 else if (opc1 == 0x0b)
12322 if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01))
12327 curr_insn_type = INSN_T0;
12329 curr_insn_type = INSN_T1;
12334 curr_insn_type = INSN_T1;
12336 curr_insn_type = INSN_T2;
12340 else if ((opc2 == 0x01 && opc3 == 0x01)
12341 || (opc2 == 0x00 && opc3 == 0x03))
12346 curr_insn_type = INSN_T0;
12348 curr_insn_type = INSN_T1;
12353 curr_insn_type = INSN_T1;
12355 curr_insn_type = INSN_T2;
12359 else if (opc2 == 0x01 && opc3 == 0x03)
12362 curr_insn_type = INSN_T1;
12364 curr_insn_type = INSN_T2;
12367 else if (opc2 == 0x07 && opc3 == 0x03)
12370 curr_insn_type = INSN_T1;
12372 curr_insn_type = INSN_T2;
12374 else if (opc3 & 0x01)
12377 if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c)
12380 curr_insn_type = INSN_T2;
12384 curr_insn_type = INSN_T1;
12386 curr_insn_type = INSN_T2;
12390 else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e)
12393 curr_insn_type = INSN_T1;
12395 curr_insn_type = INSN_T2;
12398 else if ((opc2 & 0x0e) == 0x02)
12399 curr_insn_type = INSN_T2;
12401 else if ((opc2 & 0x0e) == 0x04)
12402 curr_insn_type = INSN_T3;
12406 switch (curr_insn_type)
12409 reg_vd = reg_vd | (bit_d << 4);
12411 record_buf[1] = reg_vd + ARM_D0_REGNUM + 1;
12416 reg_vd = reg_vd | (bit_d << 4);
12422 reg_vd = (reg_vd << 1) | bit_d;
12446 uint32_t op, op1, op1_sbit, op1_ebit, coproc;
12452 if ((coproc & 0x0e) == 0x0a)
12459 if ((op1 & 0x3e) == 0x04)
12500 uint32_t op, op1_sbit, op1_ebit, coproc;
12518 svc_operand = (0x00ffffff & arm_insn_r->
arm_insn);
12521 svc_number = svc_operand - 0x900000;
12534 if ((coproc & 0x0e) == 0x0a)
12537 if (!op1_sbit && !op)
12541 if (!op1_sbit && op)
12547 if (!op1_sbit && !op)
12551 if (!op1_sbit && !op1_ebit && op)
12555 if (!op1_sbit && op1_ebit && op)
12557 uint32_t record_buf[1];
12560 if (record_buf[0] == 15)
12578 uint32_t record_buf[8];
12579 uint32_t reg_src1 = 0;
12584 record_buf[1] = reg_src1;
12598 uint32_t record_buf[8];
12599 uint32_t reg_src1 = 0;
12604 record_buf[1] = reg_src1;
12618 uint32_t record_buf[8], record_buf_mem[8];
12620 uint32_t reg_src1 = 0, reg_src2 = 0;
12621 uint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0;
12631 if (opcode2 >= 12 && opcode2 <= 15)
12635 record_buf[0] = reg_src1;
12638 else if (opcode2 >= 8 && opcode2 <= 10)
12646 record_buf_mem[0] = 4;
12647 else if (10 == opcode2)
12648 record_buf_mem[0] = 1;
12649 else if (9 == opcode2)
12650 record_buf_mem[0] = 2;
12651 record_buf_mem[1] = u_regval[0] + u_regval[1];
12660 record_buf[0] = reg_src1;
12667 if ((3 == opcode2) && (!opcode3))
12678 record_buf[1] = reg_src1;
12688 reg_src1 = reg_src1 + 8;
12691 record_buf[1] = reg_src1;
12708 uint32_t record_buf[8], record_buf_mem[8];
12710 uint32_t reg_src1 = 0;
12711 uint32_t opcode = 0, immed_5 = 0;
12721 record_buf[0] = reg_src1;
12730 record_buf_mem[0] = 4;
12731 record_buf_mem[1] = u_regval + (immed_5 * 4);
12748 uint32_t record_buf[8], record_buf_mem[8];
12750 uint32_t reg_src1 = 0;
12751 uint32_t opcode = 0, immed_8 = 0, immed_5 = 0;
12761 record_buf[0] = reg_src1;
12764 else if (1 == opcode)
12768 record_buf[0] = reg_src1;
12771 else if (2 == opcode)
12776 record_buf_mem[0] = 4;
12777 record_buf_mem[1] = u_regval + (immed_8 * 4);
12780 else if (0 == opcode)
12786 record_buf_mem[0] = 2;
12787 record_buf_mem[1] = u_regval + (immed_5 * 2);
12805 uint32_t opcode = 0, opcode1 = 0, opcode2 = 0;
12806 uint32_t register_bits = 0, register_count = 0;
12807 uint32_t register_list[8] = {0}, index = 0, start_address = 0;
12808 uint32_t record_buf[24], record_buf_mem[48];
12821 while (register_bits)
12823 if (register_bits & 0x00000001)
12824 record_buf[index++] = register_count;
12825 register_bits = register_bits >> 1;
12832 else if (10 == opcode2)
12837 while (register_bits)
12839 if (register_bits & 0x00000001)
12841 register_bits = register_bits >> 1;
12843 start_address = u_regval - \
12844 (4 * (
bit (thumb_insn_r->
arm_insn, 8) + register_count));
12846 while (register_count)
12848 record_buf_mem[(register_count * 2) - 1] = start_address;
12849 record_buf_mem[(register_count * 2) - 2] = 4;
12850 start_address = start_address + 4;
12856 else if (0x1E == opcode1)
12870 "0x%0x at address %s.\n"),
12876 else if ((0 == opcode) || (1 == opcode))
12880 record_buf[0] = reg_src1;
12883 else if (2 == opcode)
12907 uint32_t reg_src1 = 0;
12908 uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0;
12909 uint32_t register_list[8] = {0}, index = 0, start_address = 0;
12910 uint32_t record_buf[24], record_buf_mem[48];
12924 while (register_bits)
12926 if (register_bits & 0x00000001)
12927 record_buf[index++] = register_count;
12928 register_bits = register_bits >> 1;
12931 record_buf[index++] = reg_src1;
12934 else if (0 == opcode2)
12941 while (register_bits)
12943 if (register_bits & 0x00000001)
12945 register_bits = register_bits >> 1;
12947 start_address = u_regval;
12949 while (register_count)
12951 record_buf_mem[(register_count * 2) - 1] = start_address;
12952 record_buf_mem[(register_count * 2) - 2] = 4;
12953 start_address = start_address + 4;
12957 else if (0x1F == opcode1)
12987 uint32_t record_buf[8];
12988 uint32_t bits_h = 0;
12992 if (2 == bits_h || 3 == bits_h)
12998 else if (1 == bits_h)
13021 uint32_t reg_rn, op;
13022 uint32_t register_bits = 0, register_count = 0;
13023 uint32_t index = 0, start_address = 0;
13024 uint32_t record_buf[24], record_buf_mem[48];
13031 if (0 == op || 3 == op)
13045 else if (1 == op || 2 == op)
13050 register_bits =
bits (thumb2_insn_r->
arm_insn, 0, 15);
13051 while (register_bits)
13053 if (register_bits & 0x00000001)
13054 record_buf[index++] = register_count;
13057 register_bits = register_bits >> 1;
13059 record_buf[index++] = reg_rn;
13066 register_bits =
bits (thumb2_insn_r->
arm_insn, 0, 15);
13068 while (register_bits)
13070 if (register_bits & 0x00000001)
13073 register_bits = register_bits >> 1;
13079 start_address = u_regval;
13084 start_address = u_regval - register_count * 4;
13088 while (register_count)
13090 record_buf_mem[register_count * 2 - 1] = start_address;
13091 record_buf_mem[register_count * 2 - 2] = 4;
13092 start_address = start_address + 4;
13095 record_buf[0] = reg_rn;
13116 uint32_t reg_rd, reg_rn, offset_imm;
13117 uint32_t reg_dest1, reg_dest2;
13118 uint32_t address, offset_addr;
13119 uint32_t record_buf[8], record_buf_mem[8];
13120 uint32_t op1, op2, op3;
13131 if(!(1 == op1 && 1 == op2 && (0 == op3 || 1 == op3)))
13134 record_buf[0] = reg_dest1;
13139 if (3 == op2 || (op1 & 2) || (1 == op1 && 1 == op2 && 7 == op3))
13142 record_buf[2] = reg_dest2;
13151 if (0 == op1 && 0 == op2)
13155 address = u_regval[0] + (offset_imm * 4);
13156 record_buf_mem[0] = 4;
13157 record_buf_mem[1] = address;
13160 record_buf[0] = reg_rd;
13163 else if (1 == op1 && 0 == op2)
13166 record_buf[0] = reg_rd;
13168 address = u_regval[0];
13169 record_buf_mem[1] = address;
13174 record_buf_mem[0] = 1;
13180 record_buf_mem[0] = 2 ;
13186 address = u_regval[0];
13187 record_buf_mem[0] = 4;
13188 record_buf_mem[2] = 4;
13189 record_buf_mem[3] = address + 4;
13200 offset_addr = u_regval[0] + (offset_imm * 4);
13202 offset_addr = u_regval[0] - (offset_imm * 4);
13204 address = offset_addr;
13207 address = u_regval[0];
13209 record_buf_mem[0] = 4;
13210 record_buf_mem[1] = address;
13211 record_buf_mem[2] = 4;
13212 record_buf_mem[3] = address + 4;
13214 record_buf[0] = reg_rn;
13232 uint32_t reg_rd, op;
13233 uint32_t record_buf[8];
13238 if ((0 == op || 4 == op || 8 == op || 13 == op) && 15 == reg_rd)
13245 record_buf[0] = reg_rd;
13262 uint32_t record_buf[8];
13266 record_buf[0] = reg_rd;
13280 uint32_t op, op1, op2;
13281 uint32_t record_buf[8];
13288 if (!(op1 & 0x2) && 0x38 == op)
13302 else if (4 == (op1 & 0x5) || 5 == (op1 & 0x5))
13322 uint32_t reg_rn, reg_rm, offset_imm, shift_imm;
13323 uint32_t address, offset_addr;
13324 uint32_t record_buf[8], record_buf_mem[8];
13338 offset_addr = u_regval[0] + offset_imm;
13339 address = offset_addr;
13344 if ((0 == op1 || 1 == op1 || 2 == op1) && !(op2 & 0x20))
13350 offset_addr = u_regval[1] << shift_imm;
13351 address = u_regval[0] + offset_addr;
13359 offset_addr = u_regval[0] + offset_imm;
13361 offset_addr = u_regval[0] - offset_imm;
13363 address = offset_addr;
13366 address = u_regval[0];
13375 record_buf_mem[0] = 1;
13380 record_buf_mem[0] = 2;
13385 record_buf_mem[0] = 4;
13393 record_buf_mem[1] = address;
13395 record_buf[0] = reg_rn;
13410 uint32_t record_buf[8];
13411 uint32_t reg_rt, reg_rn;
13418 record_buf[0] = reg_rt;
13419 record_buf[1] = reg_rn;
13436 uint32_t opcode1 = 0, opcode2 = 0;
13437 uint32_t record_buf[8];
13439 record_buf[0] =
bits (thumb2_insn_r->
arm_insn, 12, 15);
13454 uint32_t opcode1 = 0, opcode2 = 0;
13455 uint32_t record_buf[8];
13456 uint32_t reg_src1 = 0;
13461 if (0 == opcode1 || 2 == opcode1 || (opcode1 >= 4 && opcode1 <= 6))
13465 record_buf[0] =
bits (thumb2_insn_r->
arm_insn, 16, 19);
13466 record_buf[1] =
bits (thumb2_insn_r->
arm_insn, 12, 15);
13470 else if (1 == opcode1 || 3 == opcode2)
13473 record_buf[0] =
bits (thumb2_insn_r->
arm_insn, 16, 19);
13474 record_buf[1] =
bits (thumb2_insn_r->
arm_insn, 12, 15);
13503 uint32_t l_bit, a_bit, b_bits;
13504 uint32_t record_buf[128], record_buf_mem[128];
13505 uint32_t reg_rn, reg_vd, address, f_esize, f_elem;
13506 uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0;
13514 reg_vd = (
bit (thumb2_insn_r->
arm_insn, 22) << 4) | reg_vd;
13515 f_ebytes = (1 <<
bits (thumb2_insn_r->
arm_insn, 6, 7));
13516 f_esize = 8 * f_ebytes;
13517 f_elem = 8 / f_ebytes;
13523 address = u_regval;
13528 if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06)
13530 if (b_bits == 0x07)
13532 else if (b_bits == 0x0a)
13534 else if (b_bits == 0x06)
13536 else if (b_bits == 0x02)
13541 for (index_r = 0; index_r < bf_regs; index_r++)
13543 for (index_e = 0; index_e < f_elem; index_e++)
13545 record_buf_mem[index_m++] = f_ebytes;
13546 record_buf_mem[index_m++] = address;
13547 address = address + f_ebytes;
13553 else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08)
13555 if (b_bits == 0x09 || b_bits == 0x08)
13557 else if (b_bits == 0x03)
13562 for (index_r = 0; index_r < bf_regs; index_r++)
13563 for (index_e = 0; index_e < f_elem; index_e++)
13565 for (loop_t = 0; loop_t < 2; loop_t++)
13567 record_buf_mem[index_m++] = f_ebytes;
13568 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
13571 address = address + (2 * f_ebytes);
13575 else if ((b_bits & 0x0e) == 0x04)
13577 for (index_e = 0; index_e < f_elem; index_e++)
13579 for (loop_t = 0; loop_t < 3; loop_t++)
13581 record_buf_mem[index_m++] = f_ebytes;
13582 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
13585 address = address + (3 * f_ebytes);
13589 else if (!(b_bits & 0x0e))
13591 for (index_e = 0; index_e < f_elem; index_e++)
13593 for (loop_t = 0; loop_t < 4; loop_t++)
13595 record_buf_mem[index_m++] = f_ebytes;
13596 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
13599 address = address + (4 * f_ebytes);
13605 uint8_t bft_size =
bits (thumb2_insn_r->
arm_insn, 10, 11);
13607 if (bft_size == 0x00)
13609 else if (bft_size == 0x01)
13611 else if (bft_size == 0x02)
13617 if (!(b_bits & 0x0b) || b_bits == 0x08)
13620 else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09)
13623 else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a)
13626 else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b)
13629 for (index_m = 0; index_m < thumb2_insn_r->
mem_rec_count; index_m++)
13631 record_buf_mem[index_m] = f_ebytes;
13632 record_buf_mem[index_m] = address + (index_m * f_ebytes);
13641 if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06)
13644 else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08)
13647 else if ((b_bits & 0x0e) == 0x04)
13650 else if (!(b_bits & 0x0e))
13656 if (!(b_bits & 0x0b) || b_bits == 0x08 || b_bits == 0x0c)
13659 else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09 || b_bits == 0x0d)
13662 else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a || b_bits == 0x0e)
13665 else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b || b_bits == 0x0f)
13668 for (index_r = 0; index_r < thumb2_insn_r->
reg_rec_count; index_r++)
13675 record_buf[index_r] = reg_rn;
13688 static unsigned int
13691 uint32_t op, op1, op2;
13699 if (!(op2 & 0x64 ))
13704 else if (!((op2 & 0x64) ^ 0x04))
13709 else if (!((op2 & 0x20) ^ 0x20))
13714 else if (op2 & 0x40)
13720 else if (op1 == 0x02)
13727 else if (op2 & 0x20)
13738 else if (op1 == 0x03)
13740 if (!(op2 & 0x71 ))
13745 else if (!((op2 & 0x71) ^ 0x10))
13750 else if (!((op2 & 0x67) ^ 0x01))
13755 else if (!((op2 & 0x67) ^ 0x03))
13760 else if (!((op2 & 0x67) ^ 0x05))
13765 else if (!((op2 & 0x70) ^ 0x20))
13770 else if (!((op2 & 0x78) ^ 0x30))
13775 else if (!((op2 & 0x78) ^ 0x38))
13780 else if (op2 & 0x40)
13798 memset (&buf[0], 0, insn_size);
13815 uint32_t insn_size)
13834 thumb_record_shift_add_sub,
13845 uint32_t insn_id = 0;
13852 "addr %s len = %d.\n"),
13866 ret = arm_handle_insn[insn_id] (arm_record);
13872 arm_record->
cond = -1;
13874 ret = thumb_handle_insn[insn_id] (arm_record);
13879 arm_record->
cond = -1;
13923 uint32_t no_of_rec = 0;
13934 arm_record.
gdbarch = gdbarch;
13949 "addr %s len = %d.\n"),
13962 if (!(u_regval & t_bit))
13971 if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id))
13989 for (no_of_rec = 0; no_of_rec < arm_record.
reg_rec_count; no_of_rec++)
13999 for (no_of_rec = 0; no_of_rec < arm_record.
mem_rec_count; no_of_rec++)
struct gdbarch * target_gdbarch(void)
void set_gdbarch_num_regs(struct gdbarch *gdbarch, int num_regs)
static void arm_update_current_architecture(void)
static void arm_prologue_this_id(struct frame_info *this_frame, void **this_cache, struct frame_id *this_id)
static int arm_record_asimd_vfp_coproc(insn_decode_record *arm_insn_r)
void set_gdbarch_frame_align(struct gdbarch *gdbarch, gdbarch_frame_align_ftype frame_align)
void set_gdbarch_have_nonsteppable_watchpoint(struct gdbarch *gdbarch, int have_nonsteppable_watchpoint)
struct displaced_step_closure::@19::@22 block
void set_gdbarch_float_format(struct gdbarch *gdbarch, const struct floatformat **float_format)
ULONGEST extract_unsigned_integer(const gdb_byte *, int, enum bfd_endian)
static enum arm_float_model arm_fp_model
#define target_has_registers
CORE_ADDR(* syscall_next_pc)(struct frame_info *frame)
struct cmd_list_element * add_prefix_cmd(const char *name, enum command_class theclass, cmd_cfunc_ftype *fun, const char *doc, struct cmd_list_element **prefixlist, const char *prefixname, int allow_unknown, struct cmd_list_element **list)
static CORE_ADDR arm_unwind_sp(struct gdbarch *gdbarch, struct frame_info *this_frame)
static int insn_references_pc(uint32_t insn, uint32_t bitmask)
static int arm_vfp_cprc_reg_char(enum arm_vfp_cprc_base_type b)
static int thumb_record_ld_st_imm_offset(insn_decode_record *thumb_insn_r)
static int skip_prologue_function(struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb)
static int extract_arm_insn(insn_decode_record *insn_record, uint32_t insn_size)
static int arm_record_data_proc_imm(insn_decode_record *arm_insn_r)
struct frame_id frame_id_build(CORE_ADDR stack_addr, CORE_ADDR code_addr)
#define ARM_INSN_SIZE_BYTES
static struct gdbarch * arm_gdbarch_init(struct gdbarch_info info, struct gdbarch_list *arches)
static CORE_ADDR arm_skip_prologue(struct gdbarch *gdbarch, CORE_ADDR pc)
void set_gdbarch_get_longjmp_target(struct gdbarch *gdbarch, gdbarch_get_longjmp_target_ftype get_longjmp_target)
static int thumb2_copy_alu_imm(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, struct displaced_step_closure *dsc)
static const char * arm_force_mode_string
CORE_ADDR get_frame_address_in_block(struct frame_info *this_frame)
static void branch_write_pc(struct regcache *regs, struct displaced_step_closure *dsc, ULONGEST val)
#define OBSTACK_CALLOC(OBSTACK, NUMBER, TYPE)
static void arm_exidx_data_free(struct objfile *objfile, void *arg)
void set_gdbarch_coff_make_msymbol_special(struct gdbarch *gdbarch, gdbarch_coff_make_msymbol_special_ftype coff_make_msymbol_special)
static int sbo_sbz(uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo)
static int arm_decode_unconditional(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc)
static void initialize_tdesc_arm_with_m_fpa_layout(void)
#define EXTRACT_MOVW_MOVT_IMM_A(insn)
static void arm_store_return_value(struct type *type, struct regcache *regs, const gdb_byte *valbuf)
static CORE_ADDR arm_push_dummy_call(struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr)
static enum arm_abi_kind arm_abi_global
struct type * builtin_func_ptr
static struct stack_item * pop_stack_item(struct stack_item *si)
void set_tdesc_pseudo_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype *pseudo_name)
CORE_ADDR get_frame_pc(struct frame_info *frame)
static int thumb2_record_coproc_insn(insn_decode_record *thumb2_insn_r)
const gdb_byte * thumb_breakpoint
struct insn_decode_record_t insn_decode_record
#define MSYMBOL_LINKAGE_NAME(symbol)
static struct arm_prologue_cache * arm_exidx_fill_cache(struct frame_info *this_frame, gdb_byte *entry)
int trad_frame_realreg_p(struct trad_frame_saved_reg this_saved_regs[], int regnum)
static int thumb_copy_bx_blx_reg(struct gdbarch *gdbarch, uint16_t insn, struct regcache *regs, struct displaced_step_closure *dsc)
struct frame_info * get_current_frame(void)
#define DISPLACED_STEPPING_ARCH_VERSION
unsigned long modinsn[DISPLACED_MODIFIED_INSNS]
void floatformat_from_doublest(const struct floatformat *fmt, const DOUBLEST *in, void *out)
static void thumb_process_displaced_16bit_insn(struct gdbarch *gdbarch, uint16_t insn1, struct regcache *regs, struct displaced_step_closure *dsc)
void gdbarch_init_osabi(struct gdbarch_info info, struct gdbarch *gdbarch)
static struct type * arm_neon_quad_type(struct gdbarch *gdbarch)
static int thumb2_record_str_single_data(insn_decode_record *thumb2_insn_r)
static void install_load_store(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc, int load, int immed, int writeback, int size, int usermode, int rt, int rm, int rn)
pv_t pv_add_constant(pv_t v, CORE_ADDR k)
int arm_software_single_step(struct frame_info *frame)
static int arm_copy_alu_shifted_reg(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc)
struct value * trad_frame_get_prev_register(struct frame_info *this_frame, struct trad_frame_saved_reg this_saved_regs[], int regnum)
static enum unwind_stop_reason arm_prologue_unwind_stop_reason(struct frame_info *this_frame, void **this_cache)
static struct arm_prologue_cache * arm_make_prologue_cache(struct frame_info *this_frame)
static void set_arm_command(char *args, int from_tty)
static struct stack_item * push_stack_item(struct stack_item *prev, const void *contents, int len)
const struct floatformat * floatformats_ieee_double[BFD_ENDIAN_UNKNOWN]
int trad_frame_addr_p(struct trad_frame_saved_reg this_saved_regs[], int regnum)
static int arm_type_align(struct type *t)
static void cleanup_svc(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc)
static int thumb2_copy_load_literal(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, struct displaced_step_closure *dsc, int size)
void store_signed_integer(gdb_byte *, int, enum bfd_endian, LONGEST)
int record_full_arch_list_add_reg(struct regcache *regcache, int regnum)
static void install_copro_load_store(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc, int writeback, unsigned int rn)
struct gdbarch * get_regcache_arch(const struct regcache *regcache)
void write_memory_unsigned_integer(CORE_ADDR addr, int len, enum bfd_endian byte_order, ULONGEST value)
#define IS_THUMB_ADDR(addr)
static void initialize_tdesc_arm_with_m(void)
void add_setshow_enum_cmd(const char *name, enum command_class theclass, const char *const *enumlist, const char **var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_sfunc_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
static int thumb_copy_unmodified_16bit(struct gdbarch *gdbarch, unsigned int insn, const char *iname, struct displaced_step_closure *dsc)
struct bfd_section * the_bfd_section
#define BMSYMBOL_VALUE_ADDRESS(symbol)
static int arm_exidx_unwind_sniffer(const struct frame_unwind *self, struct frame_info *this_frame, void **this_prologue_cache)
void set_gdbarch_skip_trampoline_code(struct gdbarch *gdbarch, gdbarch_skip_trampoline_code_ftype skip_trampoline_code)
void warning(const char *fmt,...)
struct displaced_step_closure::@19::@23 preload
int fputc_filtered(int c, struct ui_file *stream)
#define THUMB_INSN_SIZE_BYTES
static int thumb_instruction_restores_sp(unsigned short insn)
static CORE_ADDR arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch)
#define obj_section_offset(s)
static const char *const arm_mode_strings[]
static CORE_ADDR thumb_get_next_pc_raw(struct frame_info *frame, CORE_ADDR pc)
#define TYPE_NAME(thistype)
static int gdb_print_insn_arm(bfd_vma memaddr, disassemble_info *info)
void set_gdbarch_write_pc(struct gdbarch *gdbarch, gdbarch_write_pc_ftype write_pc)
void set_gdbarch_addr_bits_remove(struct gdbarch *gdbarch, gdbarch_addr_bits_remove_ftype addr_bits_remove)
static int thumb_copy_cbnz_cbz(struct gdbarch *gdbarch, uint16_t insn1, struct regcache *regs, struct displaced_step_closure *dsc)
static CORE_ADDR arm_addr_bits_remove(struct gdbarch *gdbarch, CORE_ADDR val)
char * ui_file_xstrdup(struct ui_file *file, long *length)
int arm_psr_thumb_bit(struct gdbarch *gdbarch)
static void show_arm_command(char *args, int from_tty)
static int arm_record_unsupported_insn(insn_decode_record *arm_insn_r)
static const char *const arm_register_names[]
static int thumb2_record_data_proc_sreg_mimm(insn_decode_record *thumb2_insn_r)
struct displaced_step_closure::@19::@20 ldst
static int decode_insn(insn_decode_record *arm_record, record_type_t record_type, uint32_t insn_size)
static unsigned int thumb_expand_immediate(unsigned int imm)
struct type * arch_float_type(struct gdbarch *gdbarch, int bit, char *name, const struct floatformat **floatformats)
void ui_file_delete(struct ui_file *file)
static int thumb_copy_b(struct gdbarch *gdbarch, unsigned short insn, struct displaced_step_closure *dsc)
static int arm_register_sim_regno(struct gdbarch *gdbarch, int regnum)
static void cleanup_block_load_all(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc)
struct cleanup * make_cleanup_free_pv_area(struct pv_area *area)
static void install_bx_blx_reg(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc, int link, unsigned int cond, unsigned int rm)
ULONGEST frame_unwind_register_unsigned(struct frame_info *frame, int regnum)
static int arm_m_exception_unwind_sniffer(const struct frame_unwind *self, struct frame_info *this_frame, void **this_prologue_cache)
int arm_frame_is_thumb(struct frame_info *frame)
static void arm_dump_tdep(struct gdbarch *gdbarch, struct ui_file *file)
enum arm_float_model fp_model
struct ui_file * gdb_stdout
static int thumb_record_ld_st_stack(insn_decode_record *thumb_insn_r)
static int arm_record_vdata_transfer_insn(insn_decode_record *arm_insn_r)
const struct builtin_type * builtin_type(struct gdbarch *gdbarch)
char * phex(ULONGEST l, int sizeof_l)
static void initialize_tdesc_arm_with_vfpv3(void)
#define INSN_RECORDED(ARM_RECORD)
static void install_pc_relative(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc, int rd)
static int thumb2_record_ld_st_multiple(insn_decode_record *thumb2_insn_r)
CORE_ADDR arm_get_next_pc(struct frame_info *frame, CORE_ADDR pc)
static void set_disassembly_style(void)
static gdb_byte * arm_find_exidx_entry(CORE_ADDR memaddr, CORE_ADDR *start)
int pv_is_register(pv_t a, int r)
void internal_error(const char *file, int line, const char *fmt,...)
static const char *const fp_model_strings[]
int gdbarch_update_p(struct gdbarch_info info)
static int thumb_copy_unmodified_32bit(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, const char *iname, struct displaced_step_closure *dsc)
unsigned int record_debug
static int arm_copy_unmodified(struct gdbarch *gdbarch, uint32_t insn, const char *iname, struct displaced_step_closure *dsc)
static int arm_compare_exidx_entries(const struct arm_exidx_entry *lhs, const struct arm_exidx_entry *rhs)
#define THUMB_LE_BREAKPOINT
struct type * builtin_uint8
static void show_fp_model(struct ui_file *file, int from_tty, struct cmd_list_element *c, const char *value)
static void initialize_tdesc_arm_with_vfpv2(void)
static char arm_find_mapping_symbol(CORE_ADDR memaddr, CORE_ADDR *start)
static void arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
void gdbarch_register_osabi_sniffer(enum bfd_architecture arch, enum bfd_flavour flavour, enum gdb_osabi(*sniffer_fn)(bfd *))
struct type * builtin_uint16
void set_gdbarch_register_reggroup_p(struct gdbarch *gdbarch, gdbarch_register_reggroup_p_ftype register_reggroup_p)
int safe_read_memory_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order, LONGEST *return_value)
#define THUMB2_INSN_SIZE_BYTES
union dwarf2_frame_state_reg::@51 loc
int pv_area_find_reg(struct pv_area *area, struct gdbarch *gdbarch, int reg, CORE_ADDR *offset_p)
const gdb_byte * arm_breakpoint
#define MSYMBOL_IS_SPECIAL(msym)
void arm_insert_single_step_breakpoint(struct gdbarch *gdbarch, struct address_space *aspace, CORE_ADDR pc)
int arm_deal_with_atomic_sequence(struct frame_info *frame)
struct type * arch_composite_type(struct gdbarch *gdbarch, char *name, enum type_code code)
static const struct @18 arm_register_aliases[]
static void thumb_process_displaced_insn(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct regcache *regs, struct displaced_step_closure *dsc)
#define ALL_OBJFILE_OSECTIONS(objfile, osect)
struct gdbarch_list * gdbarch_list_lookup_by_info(struct gdbarch_list *arches, const struct gdbarch_info *info)
ULONGEST tmp[DISPLACED_TEMPS]
CORE_ADDR skip_prologue_using_sal(struct gdbarch *gdbarch, CORE_ADDR func_addr)
#define VEC_safe_push(T, V, O)
static const gdb_byte arm_default_thumb_be_breakpoint[]
void generic_elf_osabi_sniff_abi_tag_sections(bfd *abfd, asection *sect, void *obj)
static int arm_record_ld_st_reg_offset(insn_decode_record *arm_insn_r)
struct gdbarch_list * next
#define INT_REGISTER_SIZE
struct reggroup *const restore_reggroup
static int thumb2_record_ld_st_dual_ex_tbb(insn_decode_record *thumb2_insn_r)
struct address_space * get_frame_address_space(struct frame_info *frame)
int gdbarch_num_regs(struct gdbarch *gdbarch)
#define VEC_lower_bound(T, V, O, LT)
static void install_preload(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc, unsigned int rn)
struct reggroup *const all_reggroup
initialize_file_ftype _initialize_arm_tdep
ULONGEST get_frame_memory_unsigned(struct frame_info *this_frame, CORE_ADDR addr, int len)
static const char * arm_register_name(struct gdbarch *gdbarch, int i)
static struct value * value_of_arm_user_reg(struct frame_info *frame, const void *baton)
static const char * disassembly_style
static int arm_instruction_restores_sp(unsigned int insn)
void set_gdbarch_dwarf2_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_dwarf2_reg_to_regnum_ftype dwarf2_reg_to_regnum)
static int arm_record_data_proc_misc_ld_str(insn_decode_record *arm_insn_r)
static int thumb2_decode_svc_copro(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, struct displaced_step_closure *dsc)
static void initialize_tdesc_arm_with_neon(void)
struct gdbarch_tdep * gdbarch_tdep(struct gdbarch *gdbarch)
static void arm_extract_return_value(struct type *type, struct regcache *regs, gdb_byte *valbuf)
static void print_fpu_flags(struct ui_file *file, int flags)
static int arm_copy_bx_blx_reg(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc)
void tdesc_data_cleanup(void *data_untyped)
static void cleanup_alu_shifted_reg(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc)
#define TYPE_FIELD_TYPE(thistype, n)
static void arm_stub_this_id(struct frame_info *this_frame, void **this_cache, struct frame_id *this_id)
static void arm_show_abi(struct ui_file *file, int from_tty, struct cmd_list_element *c, const char *value)
static unsigned int thumb2_record_decode_insn_handler(insn_decode_record *thumb2_insn_r)
void frame_unwind_append_unwinder(struct gdbarch *gdbarch, const struct frame_unwind *unwinder)
static int thumb2_copy_preload(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, struct displaced_step_closure *dsc)
static int condition_true(unsigned long cond, unsigned long status_reg)
pv_t pv_constant(CORE_ADDR k)
static const gdb_byte arm_default_arm_le_breakpoint[]
void set_gdbarch_elf_make_msymbol_special(struct gdbarch *gdbarch, gdbarch_elf_make_msymbol_special_ftype elf_make_msymbol_special)
static void arm_write_pc(struct regcache *regcache, CORE_ADDR pc)
void floatformat_to_doublest(const struct floatformat *fmt, const void *in, DOUBLEST *out)
#define FRAME_OBSTACK_ZALLOC(TYPE)
static int arm_override_mode
void store_unsigned_integer(gdb_byte *, int, enum bfd_endian, ULONGEST)
static int arm_copy_copro_load_store(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc)
const char * paddress(struct gdbarch *gdbarch, CORE_ADDR addr)
enum arm_abi_kind arm_abi
struct value * frame_unwind_got_constant(struct frame_info *frame, int regnum, ULONGEST val)
static void install_alu_reg(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc, unsigned int rd, unsigned int rn, unsigned int rm)
static int thumb2_copy_copro_load_store(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, struct displaced_step_closure *dsc)
void arm_displaced_init_closure(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct displaced_step_closure *dsc)
struct type * neon_double_type
static struct type * arm_register_type(struct gdbarch *gdbarch, int regnum)
struct compunit_symtab * find_pc_compunit_symtab(CORE_ADDR pc)
static void deallocate_reg_mem(insn_decode_record *record)
void gdbarch_register(enum bfd_architecture bfd_architecture, gdbarch_init_ftype *init, gdbarch_dump_tdep_ftype *dump_tdep)
#define obj_section_addr(s)
static void cleanup_store(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc)
struct minimal_symbol * lookup_minimal_symbol_by_pc_name(CORE_ADDR pc, const char *name, struct objfile *objf)
union displaced_step_closure::@19 u
struct obstack objfile_obstack
mach_port_t kern_return_t mach_port_t msgports mach_port_t kern_return_t pid_t pid mach_port_t kern_return_t mach_port_t task mach_port_t kern_return_t int flags
void null_cleanup(void *arg)
static int thumb_copy_svc(struct gdbarch *gdbarch, uint16_t insn, struct regcache *regs, struct displaced_step_closure *dsc)
#define bits(obj, st, fn)
struct reggroup *const float_reggroup
static int thumb2_record_branch_misc_cntrl(insn_decode_record *thumb2_insn_r)
int tdesc_numbered_register(const struct tdesc_feature *feature, struct tdesc_arch_data *data, int regno, const char *name)
void frame_base_set_default(struct gdbarch *gdbarch, const struct frame_base *default_base)
struct cmd_list_element * setlist
#define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2)
enum frame_type get_frame_type(struct frame_info *frame)
void set_gdbarch_pseudo_register_write(struct gdbarch *gdbarch, gdbarch_pseudo_register_write_ftype pseudo_register_write)
static int arm_deal_with_atomic_sequence_raw(struct frame_info *frame)
int arm_process_record(struct gdbarch *gdbarch, struct regcache *regcache, CORE_ADDR insn_addr)
static void install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc, unsigned int rn, unsigned int rm)
static int arm_decode_miscellaneous(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc)
static void arm_remote_breakpoint_from_pc(struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *kindptr)
static void cleanup_block_store_pc(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc)
static int thumb2_copy_table_branch(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, struct displaced_step_closure *dsc)
static void arm_m_exception_this_id(struct frame_info *this_frame, void **this_cache, struct frame_id *this_id)
void set_gdbarch_register_type(struct gdbarch *gdbarch, gdbarch_register_type_ftype register_type)
static int arm_register_reggroup_p(struct gdbarch *gdbarch, int regnum, struct reggroup *group)
struct type * check_typedef(struct type *type)
static int arm_instruction_changes_pc(uint32_t this_instr)
static int arm_copy_ldr_str_ldrb_strb(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc, int load, int size, int usermode)
#define ARM_LE_BREAKPOINT
const gdb_byte * value_contents(struct value *value)
int tdesc_numbered_register_choices(const struct tdesc_feature *feature, struct tdesc_arch_data *data, int regno, const char *const names[])
struct cleanup * make_cleanup_restore_integer(int *variable)
static void initialize_tdesc_arm_with_m_vfp_d16(void)
void register_remote_g_packet_guess(struct gdbarch *gdbarch, int bytes, const struct target_desc *tdesc)
int thumb_breakpoint_size
void displaced_write_reg(struct regcache *regs, struct displaced_step_closure *dsc, int regno, ULONGEST val, enum pc_write_style write_pc)
static int arm_stack_frame_destroyed_p(struct gdbarch *gdbarch, CORE_ADDR pc)
void dwarf2_frame_set_init_reg(struct gdbarch *gdbarch, void(*init_reg)(struct gdbarch *, int, struct dwarf2_frame_state_reg *, struct frame_info *))
static void arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
enum struct_return struct_return
void arm_displaced_step_fixup(struct gdbarch *gdbarch, struct displaced_step_closure *dsc, CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
CORE_ADDR gdbarch_addr_bits_remove(struct gdbarch *gdbarch, CORE_ADDR addr)
static int arm_copy_alu_imm(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc)
void initialize_file_ftype(void)
static struct value * arm_dwarf2_prev_register(struct frame_info *this_frame, void **this_cache, int regnum)
struct target_desc * tdesc_arm_with_m_fpa_layout
void fprintf_filtered(struct ui_file *stream, const char *format,...)
static struct value * arm_m_exception_prev_register(struct frame_info *this_frame, void **this_cache, int prev_regnum)
mach_port_t mach_port_t name mach_port_t mach_port_t name error_t err
void set_gdbarch_stack_frame_destroyed_p(struct gdbarch *gdbarch, gdbarch_stack_frame_destroyed_p_ftype stack_frame_destroyed_p)
static int thumb2_copy_block_xfer(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, struct displaced_step_closure *dsc)
enum register_status regcache_cooked_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
static void cleanup_alu_reg(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc)
void set_gdbarch_sp_regnum(struct gdbarch *gdbarch, int sp_regnum)
void(* cleanup)(struct gdbarch *, struct regcache *, struct displaced_step_closure *)
void set_gdbarch_dummy_id(struct gdbarch *gdbarch, gdbarch_dummy_id_ftype dummy_id)
static int thumb_record_shift_add_sub(insn_decode_record *thumb_insn_r)
void fprintf_unfiltered(struct ui_file *stream, const char *format,...)
static int thumb2_instruction_changes_pc(unsigned short inst1, unsigned short inst2)
mach_port_t mach_port_t name mach_port_t mach_port_t name error_t int status
static int thumb2_copy_b_bl_blx(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, struct displaced_step_closure *dsc)
struct cmd_list_element * showlist
static int thumb_insn_size(unsigned short inst1)
static int thumb2_record_lmul_lmla_div(insn_decode_record *thumb2_insn_r)
void fputs_filtered(const char *linebuffer, struct ui_file *stream)
static void thumb_scan_prologue(struct gdbarch *gdbarch, CORE_ADDR prev_pc, CORE_ADDR block_addr, struct arm_prologue_cache *cache)
static const char * arm_fallback_mode_string
const struct floatformat * floatformats_ieee_double_littlebyte_bigword[BFD_ENDIAN_UNKNOWN]
void insert_single_step_breakpoint(struct gdbarch *gdbarch, struct address_space *aspace, CORE_ADDR next_pc)
#define gdb_assert_not_reached(message)
static int arm_record_strx(insn_decode_record *arm_insn_r, uint32_t *record_buf, uint32_t *record_buf_mem, arm_record_strx_t str_type)
static int thumb2_record_ld_mem_hints(insn_decode_record *thumb2_insn_r)
void set_gdbarch_adjust_breakpoint_address(struct gdbarch *gdbarch, gdbarch_adjust_breakpoint_address_ftype adjust_breakpoint_address)
static int arm_decode_misc_memhint_neon(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc)
static CORE_ADDR arm_get_next_pc_raw(struct frame_info *frame, CORE_ADDR pc)
enum bfd_endian gdbarch_byte_order(struct gdbarch *gdbarch)
void set_gdbarch_register_sim_regno(struct gdbarch *gdbarch, gdbarch_register_sim_regno_ftype register_sim_regno)
struct cleanup * make_cleanup(make_cleanup_ftype *function, void *arg)
static CORE_ADDR thumb_analyze_prologue(struct gdbarch *gdbarch, CORE_ADDR start, CORE_ADDR limit, struct arm_prologue_cache *cache)
static struct arm_prologue_cache * arm_m_exception_cache(struct frame_info *this_frame)
struct displaced_step_closure * arm_displaced_step_copy_insn(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
static void arm_record_special_symbol(struct gdbarch *gdbarch, struct objfile *objfile, asymbol *sym)
static void set_disassembly_style_sfunc(char *, int, struct cmd_list_element *)
static void install_b_bl_blx(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc, unsigned int cond, int exchange, int link, long offset)
int find_pc_partial_function(CORE_ADDR pc, const char **name, CORE_ADDR *address, CORE_ADDR *endaddr)
struct type * init_vector_type(struct type *elt_type, int n)
static int thumb_copy_16bit_ldr_literal(struct gdbarch *gdbarch, unsigned short insn1, struct regcache *regs, struct displaced_step_closure *dsc)
struct type * builtin_int0
void arm_process_displaced_insn(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct regcache *regs, struct displaced_step_closure *dsc)
static int thumb2_record_ps_dest_generic(insn_decode_record *thumb2_insn_r)
#define VEC_index(T, V, I)
static int arm_vfp_cprc_sub_candidate(struct type *t, enum arm_vfp_cprc_base_type *base_type)
static int thumb2_decode_dp_shift_reg(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, struct displaced_step_closure *dsc)
void set_gdbarch_unwind_pc(struct gdbarch *gdbarch, gdbarch_unwind_pc_ftype unwind_pc)
static void cleanup_block_load_pc(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc)
struct frame_unwind arm_prologue_unwind
void set_gdbarch_breakpoint_from_pc(struct gdbarch *gdbarch, gdbarch_breakpoint_from_pc_ftype breakpoint_from_pc)
struct type * builtin_uint32
static const gdb_byte arm_default_thumb_le_breakpoint[]
int default_frame_sniffer(const struct frame_unwind *self, struct frame_info *this_frame, void **this_prologue_cache)
void pv_area_store(struct pv_area *area, pv_t addr, CORE_ADDR size, pv_t value)
#define COMPUNIT_PRODUCER(cust)
static void install_alu_shifted_reg(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc, unsigned int rd, unsigned int rn, unsigned int rm, unsigned rs)
#define REG_ALLOC(REGS, LENGTH, RECORD_BUF)
static int arm_copy_alu_reg(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc)
#define MAKE_THUMB_ADDR(addr)
int pv_area_store_would_trash(struct pv_area *area, pv_t addr)
static void arm_scan_prologue(struct frame_info *this_frame, struct arm_prologue_cache *cache)
static void arm_set_abi(char *args, int from_tty, struct cmd_list_element *c)
const char * gdbarch_register_name(struct gdbarch *gdbarch, int regnr)
static int startswith(const char *string, const char *pattern)
static int thumb_copy_pc_relative_32bit(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, struct displaced_step_closure *dsc)
static struct type * arm_neon_double_type(struct gdbarch *gdbarch)
enum register_status regcache_raw_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
static int bitcount(unsigned long val)
static int arm_vfp_call_candidate(struct type *t, enum arm_vfp_cprc_base_type *base_type, int *count)
#define ARM_BE_BREAKPOINT
static int arm_record_exreg_ld_st_insn(insn_decode_record *arm_insn_r)
int gdbarch_addr_bit(struct gdbarch *gdbarch)
void set_gdbarch_unwind_sp(struct gdbarch *gdbarch, gdbarch_unwind_sp_ftype unwind_sp)
static void load_write_pc(struct regcache *regs, struct displaced_step_closure *dsc, ULONGEST val)
static int arm_dwarf_reg_to_regnum(struct gdbarch *gdbarch, int reg)
static int thumb_decode_pc_relative_16bit(struct gdbarch *gdbarch, uint16_t insn, struct regcache *regs, struct displaced_step_closure *dsc)
static void arm_show_force_mode(struct ui_file *file, int from_tty, struct cmd_list_element *c, const char *value)
void set_gdbarch_remote_breakpoint_from_pc(struct gdbarch *gdbarch, gdbarch_remote_breakpoint_from_pc_ftype remote_breakpoint_from_pc)
static int arm_copy_preload_reg(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc)
static int arm_record_extension_space(insn_decode_record *arm_insn_r)
#define MAX_IT_BLOCK_PREFIX
static CORE_ADDR arm_frame_align(struct gdbarch *gdbarch, CORE_ADDR sp)
static int arm_copy_unpred(struct gdbarch *gdbarch, uint32_t insn, struct displaced_step_closure *dsc)
void printf_unfiltered(const char *format,...)
static void arm_print_float_info(struct gdbarch *gdbarch, struct ui_file *file, struct frame_info *frame, const char *args)
struct cmd_list_element * setdebuglist
static void initialize_tdesc_arm_with_iwmmxt(void)
static void convert_to_extended(const struct floatformat *, void *, const void *, int)
static int arm_decode_svc_copro(struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to, struct regcache *regs, struct displaced_step_closure *dsc)
struct obj_section * find_pc_section(CORE_ADDR pc)
int user_reg_map_name_to_regnum(struct gdbarch *gdbarch, const char *name, int len)
ULONGEST get_frame_register_unsigned(struct frame_info *frame, int regnum)
static int thumb_copy_pc_relative_16bit(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc, int rd, unsigned int imm)
struct ui_file * gdb_stdlog
int arm_pc_is_thumb(struct gdbarch *gdbarch, CORE_ADDR memaddr)
struct ui_file * mem_fileopen(void)
#define TYPE_FIELD_BITSIZE(thistype, n)
ULONGEST displaced_read_reg(struct regcache *regs, struct displaced_step_closure *dsc, int regno)
LONGEST unpack_long(struct type *type, const gdb_byte *valaddr)
void cmd_show_list(struct cmd_list_element *list, int from_tty, const char *prefix)
static int arm_copy_undef(struct gdbarch *gdbarch, uint32_t insn, struct displaced_step_closure *dsc)
#define TYPE_FIELD_BITPOS(thistype, n)
static gdb_byte * extend_buffer_earlier(gdb_byte *buf, CORE_ADDR endaddr, int old_len, int new_len)
static int thumb_record_misc(insn_decode_record *thumb_insn_r)
static int arm_get_longjmp_target(struct frame_info *frame, CORE_ADDR *pc)
int record_full_arch_list_add_mem(CORE_ADDR addr, int len)
static int arm_compare_mapping_symbols(const struct arm_mapping_symbol *lhs, const struct arm_mapping_symbol *rhs)
DEF_VEC_O(arm_mapping_symbol_s)
const struct target_desc * target_desc
static int arm_decode_ld_st_word_ubyte(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc)
static enum gdb_osabi arm_elf_osabi_sniffer(bfd *abfd)
int(* arm_syscall_record)(struct regcache *regcache, unsigned long svc_number)
static int arm_decode_media(struct gdbarch *gdbarch, uint32_t insn, struct displaced_step_closure *dsc)
const struct floatformat * floatformats_ieee_single[BFD_ENDIAN_UNKNOWN]
struct type * neon_quad_type
static int thumb_record_ldm_stm_swi(insn_decode_record *thumb_insn_r)
struct pv_area * make_pv_area(int base_reg, int addr_bit)
static void alu_write_pc(struct regcache *regs, struct displaced_step_closure *dsc, ULONGEST val)
static int arm_record_coproc_data_proc(insn_decode_record *arm_insn_r)
struct trad_frame_saved_reg * trad_frame_alloc_saved_regs(struct frame_info *this_frame)
static int arm_return_in_memory(struct gdbarch *gdbarch, struct type *type)
static void arm_show_fallback_mode(struct ui_file *file, int from_tty, struct cmd_list_element *c, const char *value)
static int thumb_advance_itstate(unsigned int itstate)
#define MSYMBOL_SET_SPECIAL(msym)
void tdesc_use_registers(struct gdbarch *gdbarch, const struct target_desc *target_desc, struct tdesc_arch_data *early_data)
static int arm_copy_svc(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc)
#define UNMAKE_THUMB_ADDR(addr)
static unsigned arm_vfp_cprc_unit_length(enum arm_vfp_cprc_base_type b)
static struct frame_id arm_dummy_id(struct gdbarch *gdbarch, struct frame_info *this_frame)
const char const char int
int core_addr_lessthan(CORE_ADDR lhs, CORE_ADDR rhs)
struct frame_info * get_next_frame(struct frame_info *this_frame)
static void set_fp_model_sfunc(char *args, int from_tty, struct cmd_list_element *c)
struct type * arm_ext_type
void append_composite_type_field(struct type *t, char *name, struct type *field)
void help_list(struct cmd_list_element *list, const char *cmdtype, enum command_class theclass, struct ui_file *stream)
static void bx_write_pc(struct regcache *regs, ULONGEST val)
void set_gdbarch_pseudo_register_read(struct gdbarch *gdbarch, gdbarch_pseudo_register_read_ftype pseudo_register_read)
static struct type * arm_ext_type(struct gdbarch *gdbarch)
void set_gdbarch_char_signed(struct gdbarch *gdbarch, int char_signed)
static void arm_objfile_data_free(struct objfile *objfile, void *arg)
const gdb_byte * thumb2_breakpoint
#define TYPE_TARGET_TYPE(thistype)
struct displaced_step_closure::@19::@24 svc
struct type * builtin_double
struct bound_minimal_symbol lookup_minimal_symbol_by_pc(CORE_ADDR pc)
static void cleanup_pop_pc_16bit_all(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc)
int thumb2_breakpoint_size
static const struct objfile_data * arm_exidx_data_key
static int thumb_record_branch(insn_decode_record *thumb_insn_r)
#define VFP_REGISTER_SIZE
int xsnprintf(char *str, size_t size, const char *format,...)
static void arm_register_g_packet_guesses(struct gdbarch *gdbarch)
#define TYPE_CODE(thistype)
static int thumb_stack_frame_destroyed_p(struct gdbarch *gdbarch, CORE_ADDR pc)
struct value * value_of_register(int regnum, struct frame_info *frame)
static struct value * arm_prologue_prev_register(struct frame_info *this_frame, void **this_cache, int prev_regnum)
enum register_status regcache_raw_read(struct regcache *regcache, int regnum, gdb_byte *buf)
void regcache_cooked_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
static int arm_decode_ext_reg_ld_st(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc)
static enum register_status arm_pseudo_read(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, gdb_byte *buf)
static int arm_decode_dp_misc(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc)
int target_read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
struct regcache * regcache
void gdbarch_info_init(struct gdbarch_info *info)
static void thumb_process_displaced_32bit_insn(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, struct displaced_step_closure *dsc)
struct ui_file * gdb_stderr
static int arm_vfp_abi_for_function(struct gdbarch *gdbarch, struct type *func_type)
struct type * builtin_data_ptr
static int in_plt_section(CORE_ADDR pc)
static int thumb2_record_asimd_struct_ld_st(insn_decode_record *thumb2_insn_r)
static const char * arm_abi_string
static int thumb2_record_ld_word(insn_decode_record *thumb2_insn_r)
struct minimal_symbol * minsym
static const char * current_fp_model
void set_gdbarch_record_special_symbol(struct gdbarch *gdbarch, gdbarch_record_special_symbol_ftype record_special_symbol)
static int install_svc(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc)
static enum register_status arm_neon_quad_read(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, gdb_byte *buf)
static CORE_ADDR arm_adjust_breakpoint_address(struct gdbarch *gdbarch, CORE_ADDR bpaddr)
struct type * tdesc_register_type(struct gdbarch *gdbarch, int regno)
void set_gdbarch_print_float_info(struct gdbarch *gdbarch, gdbarch_print_float_info_ftype print_float_info)
#define TYPE_NFIELDS(thistype)
static int arm_copy_preload(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc)
void set_gdbarch_num_pseudo_regs(struct gdbarch *gdbarch, int num_pseudo_regs)
static const struct objfile_data * arm_objfile_data_key
#define THUMB_BE_BREAKPOINT
void dwarf2_append_unwinders(struct gdbarch *gdbarch)
enum register_status regcache_cooked_read(struct regcache *regcache, int regnum, gdb_byte *buf)
static void convert_from_extended(const struct floatformat *, const void *, void *, int)
static int thumb_record_add_sub_cmp_mov(insn_decode_record *thumb_insn_r)
struct target_desc * tdesc_arm_with_m_vfp_d16
static int arm_copy_block_xfer(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc)
struct m32c_reg regs[M32C_MAX_NUM_REGS]
#define CHECK_TYPEDEF(TYPE)
struct displaced_step_closure::@19::@21 branch
static int thumb_32bit_copy_undef(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct displaced_step_closure *dsc)
static int displaced_in_arm_mode(struct regcache *regs)
static int arm_record_ld_st_imm_offset(insn_decode_record *arm_insn_r)
static enum return_value_convention arm_return_value(struct gdbarch *gdbarch, struct value *function, struct type *valtype, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf)
static int thumb_deal_with_atomic_sequence_raw(struct frame_info *frame)
static unsigned long shifted_reg_val(struct frame_info *frame, unsigned long inst, int carry, unsigned long pc_val, unsigned long status_reg)
struct target_desc * tdesc_arm_with_m
enum bfd_endian byte_order_for_code
void set_gdbarch_double_format(struct gdbarch *gdbarch, const struct floatformat **double_format)
struct tdesc_arch_data * tdesc_data_alloc(void)
static struct obj_section * arm_obj_section_from_vma(struct objfile *objfile, bfd_vma vma)
static CORE_ADDR arm_normal_frame_base(struct frame_info *this_frame, void **this_cache)
static const char *const arm_abi_strings[]
static int arm_decode_b_bl_ldmstm(struct gdbarch *gdbarch, int32_t insn, struct regcache *regs, struct displaced_step_closure *dsc)
static int arm_copy_b_bl_blx(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc)
int(* sti_arm_hdl_fp_t)(insn_decode_record *)
static int arm_record_vfp_data_proc_insn(insn_decode_record *arm_insn_r)
unsigned long long ULONGEST
enum unwind_stop_reason default_frame_unwind_stop_reason(struct frame_info *this_frame, void **this_cache)
#define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF)
const struct tdesc_feature * tdesc_find_feature(const struct target_desc *target_desc, const char *name)
struct observer * observer_attach_new_objfile(observer_new_objfile_ftype *f)
void user_reg_add(struct gdbarch *gdbarch, const char *name, user_reg_read_ftype *read, const void *baton)
#define IT_SCAN_THRESHOLD
struct type * value_type(const struct value *value)
enum bfd_endian byte_order_for_code
static struct arm_prologue_cache * arm_make_stub_cache(struct frame_info *this_frame)
static const char ** valid_disassembly_styles
static void arm_exidx_new_objfile(struct objfile *objfile)
void set_gdbarch_return_value(struct gdbarch *gdbarch, gdbarch_return_value_ftype return_value)
const struct bfd_arch_info * gdbarch_bfd_arch_info(struct gdbarch *gdbarch)
struct cmd_list_element * showdebuglist
static int coff_sym_is_thumb(int val)
static void arm_dwarf2_frame_init_reg(struct gdbarch *gdbarch, int regnum, struct dwarf2_frame_state_reg *reg, struct frame_info *this_frame)
void set_gdbarch_long_double_format(struct gdbarch *gdbarch, const struct floatformat **long_double_format)
static int thumb_instruction_changes_pc(unsigned short inst)
#define VEC_safe_insert(T, V, I, O)
int default_register_reggroup_p(struct gdbarch *gdbarch, int regnum, struct reggroup *group)
struct reggroup *const save_reggroup
#define OBSTACK_ZALLOC(OBSTACK, TYPE)
#define TYPE_LENGTH(thistype)
static int thumb2_copy_load_reg_imm(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, struct displaced_step_closure *dsc, int writeback, int immed)
static int arm_stub_unwind_sniffer(const struct frame_unwind *self, struct frame_info *this_frame, void **this_prologue_cache)
void set_gdbarch_push_dummy_call(struct gdbarch *gdbarch, gdbarch_push_dummy_call_ftype push_dummy_call)
static const gdb_byte arm_default_arm_be_breakpoint[]
ULONGEST read_memory_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
#define sbits(obj, st, fn)
static int arm_record_b_bl(insn_decode_record *arm_insn_r)
struct trad_frame_saved_reg * saved_regs
static int num_disassembly_options
struct type * builtin_uint64
struct arm_mem_r * arm_mems
#define DISPLACED_MODIFIED_INSNS
static CORE_ADDR arm_unwind_pc(struct gdbarch *gdbarch, struct frame_info *this_frame)
static void cleanup_branch(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc)
void write_memory(CORE_ADDR memaddr, const bfd_byte *myaddr, ssize_t len)
void set_gdbarch_skip_prologue(struct gdbarch *gdbarch, gdbarch_skip_prologue_ftype skip_prologue)
static void arm_pseudo_write(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buf)
const struct floatformat * floatformats_arm_ext[BFD_ENDIAN_UNKNOWN]
static struct gdbarch_data * tdesc_data
struct bound_minimal_symbol lookup_minimal_symbol(const char *name, const char *sfile, struct objfile *objf)
PTR xcalloc(size_t number, size_t size)
static const unsigned char * arm_breakpoint_from_pc(struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
struct displaced_step_closure * get_displaced_step_closure_by_addr(CORE_ADDR addr)
static int thumb2_decode_ext_reg_ld_st(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, struct displaced_step_closure *dsc)
enum bfd_endian byte_order
static int arm_copy_extra_ld_st(struct gdbarch *gdbarch, uint32_t insn, int unpriveleged, struct regcache *regs, struct displaced_step_closure *dsc)
enum bfd_endian gdbarch_byte_order_for_code(struct gdbarch *gdbarch)
static int thumb_record_ld_st_reg_offset(insn_decode_record *thumb_insn_r)
void set_gdbarch_pc_regnum(struct gdbarch *gdbarch, int pc_regnum)
void set_gdbarch_max_insn_length(struct gdbarch *gdbarch, ULONGEST max_insn_length)
struct type * builtin_void
int record_full_arch_list_add_end(void)
static CORE_ADDR arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch, unsigned int *destreg, int *offset)
pv_t pv_add(pv_t a, pv_t b)
int tdesc_has_registers(const struct target_desc *target_desc)
static void cleanup_copro_load_store(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc)
void set_gdbarch_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype register_name)
int pv_is_constant(pv_t a)
CORE_ADDR get_frame_func(struct frame_info *this_frame)
static void arm_neon_quad_write(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buf)
static int thumb_copy_pop_pc_16bit(struct gdbarch *gdbarch, unsigned short insn1, struct regcache *regs, struct displaced_step_closure *dsc)
enum dwarf2_frame_reg_rule how
void error(const char *fmt,...)
pv_t pv_register(int reg, CORE_ADDR k)
struct gdbarch * gdbarch_alloc(const struct gdbarch_info *info, struct gdbarch_tdep *tdep)
void set_gdbarch_inner_than(struct gdbarch *gdbarch, gdbarch_inner_than_ftype inner_than)
static int thumb_copy_alu_reg(struct gdbarch *gdbarch, uint16_t insn, struct regcache *regs, struct displaced_step_closure *dsc)
static void cleanup_load(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc)
CORE_ADDR arm_skip_stub(struct frame_info *frame, CORE_ADDR pc)
static void cleanup_alu_imm(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc)
struct gdbarch * get_frame_arch(struct frame_info *this_frame)
static void cleanup_preload(struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc)
#define BranchDest(addr, instr)
static CORE_ADDR arm_analyze_prologue(struct gdbarch *gdbarch, CORE_ADDR prologue_start, CORE_ADDR prologue_end, struct arm_prologue_cache *cache)
void do_cleanups(struct cleanup *old_chain)
void add_setshow_boolean_cmd(const char *name, enum command_class theclass, int *var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_sfunc_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
void regcache_cooked_write(struct regcache *regcache, int regnum, const gdb_byte *buf)
static int decode_thumb_32bit_ld_mem_hints(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, struct displaced_step_closure *dsc)
static int arm_record_ld_st_multiple(insn_decode_record *arm_insn_r)
int tdesc_unnumbered_register(const struct tdesc_feature *feature, const char *name)
void set_gdbarch_print_insn(struct gdbarch *gdbarch, gdbarch_print_insn_ftype print_insn)
struct value *(* fn)(struct frame_info *this_frame, void **this_cache, int regnum)
struct type * builtin_float
const struct target_desc * gdbarch_target_desc(struct gdbarch *gdbarch)
static CORE_ADDR arm_skip_bx_reg(struct frame_info *frame, CORE_ADDR pc)
void regcache_raw_write(struct regcache *regcache, int regnum, const gdb_byte *buf)
const ULONGEST const LONGEST len
void set_gdbarch_vbit_in_delta(struct gdbarch *gdbarch, int vbit_in_delta)
const struct floatformat * floatformat_from_type(const struct type *type)
enum register_status regcache_raw_read_signed(struct regcache *regcache, int regnum, LONGEST *val)