GDB (xrefs)
/tmp/gdb-7.10/gdb/ppc-linux-nat.c
Go to the documentation of this file.
1 /* PPC GNU/Linux native support.
2 
3  Copyright (C) 1988-2015 Free Software Foundation, Inc.
4 
5  This file is part of GDB.
6 
7  This program is free software; you can redistribute it and/or modify
8  it under the terms of the GNU General Public License as published by
9  the Free Software Foundation; either version 3 of the License, or
10  (at your option) any later version.
11 
12  This program is distributed in the hope that it will be useful,
13  but WITHOUT ANY WARRANTY; without even the implied warranty of
14  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  GNU General Public License for more details.
16 
17  You should have received a copy of the GNU General Public License
18  along with this program. If not, see <http://www.gnu.org/licenses/>. */
19 
20 #include "defs.h"
21 #include "observer.h"
22 #include "frame.h"
23 #include "inferior.h"
24 #include "gdbthread.h"
25 #include "gdbcore.h"
26 #include "regcache.h"
27 #include "target.h"
28 #include "linux-nat.h"
29 #include <sys/types.h>
30 #include <signal.h>
31 #include <sys/user.h>
32 #include <sys/ioctl.h>
33 #include "gdb_wait.h"
34 #include <fcntl.h>
35 #include <sys/procfs.h>
36 #include <sys/ptrace.h>
37 
38 /* Prototypes for supply_gregset etc. */
39 #include "gregset.h"
40 #include "ppc-tdep.h"
41 #include "ppc-linux-tdep.h"
42 
43 /* Required when using the AUXV. */
44 #include "elf/common.h"
45 #include "auxv.h"
46 
47 #include "nat/ppc-linux.h"
48 
49 /* Similarly for the hardware watchpoint support. These requests are used
50  when the PowerPC HWDEBUG ptrace interface is not available. */
51 #ifndef PTRACE_GET_DEBUGREG
52 #define PTRACE_GET_DEBUGREG 25
53 #endif
54 #ifndef PTRACE_SET_DEBUGREG
55 #define PTRACE_SET_DEBUGREG 26
56 #endif
57 #ifndef PTRACE_GETSIGINFO
58 #define PTRACE_GETSIGINFO 0x4202
59 #endif
60 
61 /* These requests are used when the PowerPC HWDEBUG ptrace interface is
62  available. It exposes the debug facilities of PowerPC processors, as well
63  as additional features of BookE processors, such as ranged breakpoints and
64  watchpoints and hardware-accelerated condition evaluation. */
65 #ifndef PPC_PTRACE_GETHWDBGINFO
66 
67 /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the PowerPC HWDEBUG
68  ptrace interface is not present in ptrace.h, so we'll have to pretty much
69  include it all here so that the code at least compiles on older systems. */
70 #define PPC_PTRACE_GETHWDBGINFO 0x89
71 #define PPC_PTRACE_SETHWDEBUG 0x88
72 #define PPC_PTRACE_DELHWDEBUG 0x87
73 
75 {
76  uint32_t version; /* Only version 1 exists to date. */
78  uint32_t num_data_bps;
81  uint32_t sizeof_condition; /* size of the DVC register. */
82  uint64_t features;
83 };
84 
85 /* Features will have bits indicating whether there is support for: */
86 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
87 #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
88 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
89 #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
90 
92 {
93  uint32_t version; /* currently, version must be 1 */
94  uint32_t trigger_type; /* only some combinations allowed */
95  uint32_t addr_mode; /* address match mode */
96  uint32_t condition_mode; /* break/watchpoint condition flags */
97  uint64_t addr; /* break/watchpoint address */
98  uint64_t addr2; /* range end or mask */
99  uint64_t condition_value; /* contents of the DVC register */
100 };
101 
102 /* Trigger type. */
103 #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
104 #define PPC_BREAKPOINT_TRIGGER_READ 0x2
105 #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
106 #define PPC_BREAKPOINT_TRIGGER_RW 0x6
107 
108 /* Address mode. */
109 #define PPC_BREAKPOINT_MODE_EXACT 0x0
110 #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
111 #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
112 #define PPC_BREAKPOINT_MODE_MASK 0x3
113 
114 /* Condition mode. */
115 #define PPC_BREAKPOINT_CONDITION_NONE 0x0
116 #define PPC_BREAKPOINT_CONDITION_AND 0x1
117 #define PPC_BREAKPOINT_CONDITION_EXACT 0x1
118 #define PPC_BREAKPOINT_CONDITION_OR 0x2
119 #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
120 #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
121 #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
122 #define PPC_BREAKPOINT_CONDITION_BE(n) \
123  (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
124 #endif /* PPC_PTRACE_GETHWDBGINFO */
125 
126 /* Feature defined on Linux kernel v3.9: DAWR interface, that enables wider
127  watchpoint (up to 512 bytes). */
128 #ifndef PPC_DEBUG_FEATURE_DATA_BP_DAWR
129 #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10
130 #endif /* PPC_DEBUG_FEATURE_DATA_BP_DAWR */
131 
132 /* Similarly for the general-purpose (gp0 -- gp31)
133  and floating-point registers (fp0 -- fp31). */
134 #ifndef PTRACE_GETREGS
135 #define PTRACE_GETREGS 12
136 #endif
137 #ifndef PTRACE_SETREGS
138 #define PTRACE_SETREGS 13
139 #endif
140 #ifndef PTRACE_GETFPREGS
141 #define PTRACE_GETFPREGS 14
142 #endif
143 #ifndef PTRACE_SETFPREGS
144 #define PTRACE_SETFPREGS 15
145 #endif
146 
147 /* This oddity is because the Linux kernel defines elf_vrregset_t as
148  an array of 33 16 bytes long elements. I.e. it leaves out vrsave.
149  However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return
150  the vrsave as an extra 4 bytes at the end. I opted for creating a
151  flat array of chars, so that it is easier to manipulate for gdb.
152 
153  There are 32 vector registers 16 bytes longs, plus a VSCR register
154  which is only 4 bytes long, but is fetched as a 16 bytes
155  quantity. Up to here we have the elf_vrregset_t structure.
156  Appended to this there is space for the VRSAVE register: 4 bytes.
157  Even though this vrsave register is not included in the regset
158  typedef, it is handled by the ptrace requests.
159 
160  Note that GNU/Linux doesn't support little endian PPC hardware,
161  therefore the offset at which the real value of the VSCR register
162  is located will be always 12 bytes.
163 
164  The layout is like this (where x is the actual value of the vscr reg): */
165 
166 /* *INDENT-OFF* */
167 /*
168  |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|
169  <-------> <-------><-------><->
170  VR0 VR31 VSCR VRSAVE
171 */
172 /* *INDENT-ON* */
173 
174 #define SIZEOF_VRREGS 33*16+4
175 
177 
178 /* This is the layout of the POWER7 VSX registers and the way they overlap
179  with the existing FPR and VMX registers.
180 
181  VSR doubleword 0 VSR doubleword 1
182  ----------------------------------------------------------------
183  VSR[0] | FPR[0] | |
184  ----------------------------------------------------------------
185  VSR[1] | FPR[1] | |
186  ----------------------------------------------------------------
187  | ... | |
188  | ... | |
189  ----------------------------------------------------------------
190  VSR[30] | FPR[30] | |
191  ----------------------------------------------------------------
192  VSR[31] | FPR[31] | |
193  ----------------------------------------------------------------
194  VSR[32] | VR[0] |
195  ----------------------------------------------------------------
196  VSR[33] | VR[1] |
197  ----------------------------------------------------------------
198  | ... |
199  | ... |
200  ----------------------------------------------------------------
201  VSR[62] | VR[30] |
202  ----------------------------------------------------------------
203  VSR[63] | VR[31] |
204  ----------------------------------------------------------------
205 
206  VSX has 64 128bit registers. The first 32 registers overlap with
207  the FP registers (doubleword 0) and hence extend them with additional
208  64 bits (doubleword 1). The other 32 regs overlap with the VMX
209  registers. */
210 #define SIZEOF_VSXREGS 32*8
211 
213 
214 /* On PPC processors that support the Signal Processing Extension
215  (SPE) APU, the general-purpose registers are 64 bits long.
216  However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER
217  ptrace calls only access the lower half of each register, to allow
218  them to behave the same way they do on non-SPE systems. There's a
219  separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that
220  read and write the top halves of all the general-purpose registers
221  at once, along with some SPE-specific registers.
222 
223  GDB itself continues to claim the general-purpose registers are 32
224  bits long. It has unnamed raw registers that hold the upper halves
225  of the gprs, and the full 64-bit SIMD views of the registers,
226  'ev0' -- 'ev31', are pseudo-registers that splice the top and
227  bottom halves together.
228 
229  This is the structure filled in by PTRACE_GETEVRREGS and written to
230  the inferior's registers by PTRACE_SETEVRREGS. */
232 {
233  unsigned long evr[32];
234  unsigned long long acc;
235  unsigned long spefscr;
236 };
237 
238 /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and
239  PTRACE_SETVSXREGS requests, for reading and writing the VSX
240  POWER7 registers 0 through 31. Zero if we've tried one of them and
241  gotten an error. Note that VSX registers 32 through 63 overlap
242  with VR registers 0 through 31. */
244 
245 /* Non-zero if our kernel may support the PTRACE_GETVRREGS and
246  PTRACE_SETVRREGS requests, for reading and writing the Altivec
247  registers. Zero if we've tried one of them and gotten an
248  error. */
250 
251 /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and
252  PTRACE_SETEVRREGS requests, for reading and writing the SPE
253  registers. Zero if we've tried one of them and gotten an
254  error. */
256 
257 /* Non-zero if our kernel may support the PTRACE_GETREGS and
258  PTRACE_SETREGS requests, for reading and writing the
259  general-purpose registers. Zero if we've tried one of
260  them and gotten an error. */
262 
263 /* Non-zero if our kernel may support the PTRACE_GETFPREGS and
264  PTRACE_SETFPREGS requests, for reading and writing the
265  floating-pointers registers. Zero if we've tried one of
266  them and gotten an error. */
268 
269 /* *INDENT-OFF* */
270 /* registers layout, as presented by the ptrace interface:
271 PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
272 PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
273 PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
274 PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
275 PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6,
276 PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
277 PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22,
278 PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
279 PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38,
280 PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
281 PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54,
282 PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
283 PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */
284 /* *INDENT_ON * */
285 
286 static int
287 ppc_register_u_addr (struct gdbarch *gdbarch, int regno)
288 {
289  int u_addr = -1;
290  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
291  /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
292  interface, and not the wordsize of the program's ABI. */
293  int wordsize = sizeof (long);
294 
295  /* General purpose registers occupy 1 slot each in the buffer. */
296  if (regno >= tdep->ppc_gp0_regnum
297  && regno < tdep->ppc_gp0_regnum + ppc_num_gprs)
298  u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize);
299 
300  /* Floating point regs: eight bytes each in both 32- and 64-bit
301  ptrace interfaces. Thus, two slots each in 32-bit interface, one
302  slot each in 64-bit interface. */
303  if (tdep->ppc_fp0_regnum >= 0
304  && regno >= tdep->ppc_fp0_regnum
305  && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)
306  u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8);
307 
308  /* UISA special purpose registers: 1 slot each. */
309  if (regno == gdbarch_pc_regnum (gdbarch))
310  u_addr = PT_NIP * wordsize;
311  if (regno == tdep->ppc_lr_regnum)
312  u_addr = PT_LNK * wordsize;
313  if (regno == tdep->ppc_cr_regnum)
314  u_addr = PT_CCR * wordsize;
315  if (regno == tdep->ppc_xer_regnum)
316  u_addr = PT_XER * wordsize;
317  if (regno == tdep->ppc_ctr_regnum)
318  u_addr = PT_CTR * wordsize;
319 #ifdef PT_MQ
320  if (regno == tdep->ppc_mq_regnum)
321  u_addr = PT_MQ * wordsize;
322 #endif
323  if (regno == tdep->ppc_ps_regnum)
324  u_addr = PT_MSR * wordsize;
325  if (regno == PPC_ORIG_R3_REGNUM)
326  u_addr = PT_ORIG_R3 * wordsize;
327  if (regno == PPC_TRAP_REGNUM)
328  u_addr = PT_TRAP * wordsize;
329  if (tdep->ppc_fpscr_regnum >= 0
330  && regno == tdep->ppc_fpscr_regnum)
331  {
332  /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the
333  kernel headers incorrectly contained the 32-bit definition of
334  PT_FPSCR. For the 32-bit definition, floating-point
335  registers occupy two 32-bit "slots", and the FPSCR lives in
336  the second half of such a slot-pair (hence +1). For 64-bit,
337  the FPSCR instead occupies the full 64-bit 2-word-slot and
338  hence no adjustment is necessary. Hack around this. */
339  if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1))
340  u_addr = (48 + 32) * wordsize;
341  /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit
342  slot and not just its second word. The PT_FPSCR supplied when
343  GDB is compiled as a 32-bit app doesn't reflect this. */
344  else if (wordsize == 4 && register_size (gdbarch, regno) == 8
345  && PT_FPSCR == (48 + 2*32 + 1))
346  u_addr = (48 + 2*32) * wordsize;
347  else
348  u_addr = PT_FPSCR * wordsize;
349  }
350  return u_addr;
351 }
352 
353 /* The Linux kernel ptrace interface for POWER7 VSX registers uses the
354  registers set mechanism, as opposed to the interface for all the
355  other registers, that stores/fetches each register individually. */
356 static void
357 fetch_vsx_register (struct regcache *regcache, int tid, int regno)
358 {
359  int ret;
361  struct gdbarch *gdbarch = get_regcache_arch (regcache);
362  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
363  int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
364 
365  ret = ptrace (PTRACE_GETVSXREGS, tid, 0, &regs);
366  if (ret < 0)
367  {
368  if (errno == EIO)
369  {
371  return;
372  }
373  perror_with_name (_("Unable to fetch VSX register"));
374  }
375 
376  regcache_raw_supply (regcache, regno,
377  regs + (regno - tdep->ppc_vsr0_upper_regnum)
378  * vsxregsize);
379 }
380 
381 /* The Linux kernel ptrace interface for AltiVec registers uses the
382  registers set mechanism, as opposed to the interface for all the
383  other registers, that stores/fetches each register individually. */
384 static void
385 fetch_altivec_register (struct regcache *regcache, int tid, int regno)
386 {
387  int ret;
388  int offset = 0;
390  struct gdbarch *gdbarch = get_regcache_arch (regcache);
391  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
392  int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
393 
394  ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
395  if (ret < 0)
396  {
397  if (errno == EIO)
398  {
400  return;
401  }
402  perror_with_name (_("Unable to fetch AltiVec register"));
403  }
404 
405  /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
406  long on the hardware. We deal only with the lower 4 bytes of the
407  vector. VRSAVE is at the end of the array in a 4 bytes slot, so
408  there is no need to define an offset for it. */
409  if (regno == (tdep->ppc_vrsave_regnum - 1))
410  offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
411 
412  regcache_raw_supply (regcache, regno,
413  regs + (regno
414  - tdep->ppc_vr0_regnum) * vrregsize + offset);
415 }
416 
417 /* Fetch the top 32 bits of TID's general-purpose registers and the
418  SPE-specific registers, and place the results in EVRREGSET. If we
419  don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with
420  zeros.
421 
422  All the logic to deal with whether or not the PTRACE_GETEVRREGS and
423  PTRACE_SETEVRREGS requests are supported is isolated here, and in
424  set_spe_registers. */
425 static void
426 get_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
427 {
429  {
430  if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0)
431  return;
432  else
433  {
434  /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
435  we just return zeros. */
436  if (errno == EIO)
438  else
439  /* Anything else needs to be reported. */
440  perror_with_name (_("Unable to fetch SPE registers"));
441  }
442  }
443 
444  memset (evrregset, 0, sizeof (*evrregset));
445 }
446 
447 /* Supply values from TID for SPE-specific raw registers: the upper
448  halves of the GPRs, the accumulator, and the spefscr. REGNO must
449  be the number of an upper half register, acc, spefscr, or -1 to
450  supply the values of all registers. */
451 static void
452 fetch_spe_register (struct regcache *regcache, int tid, int regno)
453 {
454  struct gdbarch *gdbarch = get_regcache_arch (regcache);
455  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
456  struct gdb_evrregset_t evrregs;
457 
458  gdb_assert (sizeof (evrregs.evr[0])
459  == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
460  gdb_assert (sizeof (evrregs.acc)
461  == register_size (gdbarch, tdep->ppc_acc_regnum));
462  gdb_assert (sizeof (evrregs.spefscr)
463  == register_size (gdbarch, tdep->ppc_spefscr_regnum));
464 
465  get_spe_registers (tid, &evrregs);
466 
467  if (regno == -1)
468  {
469  int i;
470 
471  for (i = 0; i < ppc_num_gprs; i++)
472  regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i,
473  &evrregs.evr[i]);
474  }
475  else if (tdep->ppc_ev0_upper_regnum <= regno
476  && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
477  regcache_raw_supply (regcache, regno,
478  &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
479 
480  if (regno == -1
481  || regno == tdep->ppc_acc_regnum)
482  regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc);
483 
484  if (regno == -1
485  || regno == tdep->ppc_spefscr_regnum)
486  regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum,
487  &evrregs.spefscr);
488 }
489 
490 static void
491 fetch_register (struct regcache *regcache, int tid, int regno)
492 {
493  struct gdbarch *gdbarch = get_regcache_arch (regcache);
494  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
495  /* This isn't really an address. But ptrace thinks of it as one. */
496  CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);
497  int bytes_transferred;
498  unsigned int offset; /* Offset of registers within the u area. */
500 
501  if (altivec_register_p (gdbarch, regno))
502  {
503  /* If this is the first time through, or if it is not the first
504  time through, and we have comfirmed that there is kernel
505  support for such a ptrace request, then go and fetch the
506  register. */
508  {
509  fetch_altivec_register (regcache, tid, regno);
510  return;
511  }
512  /* If we have discovered that there is no ptrace support for
513  AltiVec registers, fall through and return zeroes, because
514  regaddr will be -1 in this case. */
515  }
516  if (vsx_register_p (gdbarch, regno))
517  {
519  {
520  fetch_vsx_register (regcache, tid, regno);
521  return;
522  }
523  }
524  else if (spe_register_p (gdbarch, regno))
525  {
526  fetch_spe_register (regcache, tid, regno);
527  return;
528  }
529 
530  if (regaddr == -1)
531  {
532  memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */
533  regcache_raw_supply (regcache, regno, buf);
534  return;
535  }
536 
537  /* Read the raw register using sizeof(long) sized chunks. On a
538  32-bit platform, 64-bit floating-point registers will require two
539  transfers. */
540  for (bytes_transferred = 0;
541  bytes_transferred < register_size (gdbarch, regno);
542  bytes_transferred += sizeof (long))
543  {
544  long l;
545 
546  errno = 0;
547  l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);
548  regaddr += sizeof (long);
549  if (errno != 0)
550  {
551  char message[128];
552  xsnprintf (message, sizeof (message), "reading register %s (#%d)",
553  gdbarch_register_name (gdbarch, regno), regno);
554  perror_with_name (message);
555  }
556  memcpy (&buf[bytes_transferred], &l, sizeof (l));
557  }
558 
559  /* Now supply the register. Keep in mind that the regcache's idea
560  of the register's size may not be a multiple of sizeof
561  (long). */
562  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
563  {
564  /* Little-endian values are always found at the left end of the
565  bytes transferred. */
566  regcache_raw_supply (regcache, regno, buf);
567  }
568  else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
569  {
570  /* Big-endian values are found at the right end of the bytes
571  transferred. */
572  size_t padding = (bytes_transferred - register_size (gdbarch, regno));
573  regcache_raw_supply (regcache, regno, buf + padding);
574  }
575  else
576  internal_error (__FILE__, __LINE__,
577  _("fetch_register: unexpected byte order: %d"),
578  gdbarch_byte_order (gdbarch));
579 }
580 
581 static void
583 {
584  int i;
585  struct gdbarch *gdbarch = get_regcache_arch (regcache);
586  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
587  int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
588 
589  for (i = 0; i < ppc_num_vshrs; i++)
590  {
591  regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i,
592  *vsxregsetp + i * vsxregsize);
593  }
594 }
595 
596 static void
598 {
599  int i;
600  struct gdbarch *gdbarch = get_regcache_arch (regcache);
601  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
602  int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
603  int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
604  int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
605 
606  for (i = 0; i < num_of_vrregs; i++)
607  {
608  /* The last 2 registers of this set are only 32 bit long, not
609  128. However an offset is necessary only for VSCR because it
610  occupies a whole vector, while VRSAVE occupies a full 4 bytes
611  slot. */
612  if (i == (num_of_vrregs - 2))
613  regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i,
614  *vrregsetp + i * vrregsize + offset);
615  else
616  regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i,
617  *vrregsetp + i * vrregsize);
618  }
619 }
620 
621 static void
623 {
624  int ret;
626 
627  ret = ptrace (PTRACE_GETVSXREGS, tid, 0, &regs);
628  if (ret < 0)
629  {
630  if (errno == EIO)
631  {
633  return;
634  }
635  perror_with_name (_("Unable to fetch VSX registers"));
636  }
637  supply_vsxregset (regcache, &regs);
638 }
639 
640 static void
642 {
643  int ret;
645 
646  ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
647  if (ret < 0)
648  {
649  if (errno == EIO)
650  {
652  return;
653  }
654  perror_with_name (_("Unable to fetch AltiVec registers"));
655  }
656  supply_vrregset (regcache, &regs);
657 }
658 
659 /* This function actually issues the request to ptrace, telling
660  it to get all general-purpose registers and put them into the
661  specified regset.
662 
663  If the ptrace request does not exist, this function returns 0
664  and properly sets the have_ptrace_* flag. If the request fails,
665  this function calls perror_with_name. Otherwise, if the request
666  succeeds, then the regcache gets filled and 1 is returned. */
667 static int
669 {
670  struct gdbarch *gdbarch = get_regcache_arch (regcache);
671  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
673 
674  if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
675  {
676  if (errno == EIO)
677  {
679  return 0;
680  }
681  perror_with_name (_("Couldn't get general-purpose registers."));
682  }
683 
684  supply_gregset (regcache, (const gdb_gregset_t *) &gregset);
685 
686  return 1;
687 }
688 
689 /* This is a wrapper for the fetch_all_gp_regs function. It is
690  responsible for verifying if this target has the ptrace request
691  that can be used to fetch all general-purpose registers at one
692  shot. If it doesn't, then we should fetch them using the
693  old-fashioned way, which is to iterate over the registers and
694  request them one by one. */
695 static void
696 fetch_gp_regs (struct regcache *regcache, int tid)
697 {
698  struct gdbarch *gdbarch = get_regcache_arch (regcache);
699  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
700  int i;
701 
703  if (fetch_all_gp_regs (regcache, tid))
704  return;
705 
706  /* If we've hit this point, it doesn't really matter which
707  architecture we are using. We just need to read the
708  registers in the "old-fashioned way". */
709  for (i = 0; i < ppc_num_gprs; i++)
710  fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i);
711 }
712 
713 /* This function actually issues the request to ptrace, telling
714  it to get all floating-point registers and put them into the
715  specified regset.
716 
717  If the ptrace request does not exist, this function returns 0
718  and properly sets the have_ptrace_* flag. If the request fails,
719  this function calls perror_with_name. Otherwise, if the request
720  succeeds, then the regcache gets filled and 1 is returned. */
721 static int
723 {
724  gdb_fpregset_t fpregs;
725 
726  if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0)
727  {
728  if (errno == EIO)
729  {
731  return 0;
732  }
733  perror_with_name (_("Couldn't get floating-point registers."));
734  }
735 
736  supply_fpregset (regcache, (const gdb_fpregset_t *) &fpregs);
737 
738  return 1;
739 }
740 
741 /* This is a wrapper for the fetch_all_fp_regs function. It is
742  responsible for verifying if this target has the ptrace request
743  that can be used to fetch all floating-point registers at one
744  shot. If it doesn't, then we should fetch them using the
745  old-fashioned way, which is to iterate over the registers and
746  request them one by one. */
747 static void
748 fetch_fp_regs (struct regcache *regcache, int tid)
749 {
750  struct gdbarch *gdbarch = get_regcache_arch (regcache);
751  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
752  int i;
753 
755  if (fetch_all_fp_regs (regcache, tid))
756  return;
757 
758  /* If we've hit this point, it doesn't really matter which
759  architecture we are using. We just need to read the
760  registers in the "old-fashioned way". */
761  for (i = 0; i < ppc_num_fprs; i++)
762  fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i);
763 }
764 
765 static void
767 {
768  int i;
769  struct gdbarch *gdbarch = get_regcache_arch (regcache);
770  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
771 
772  fetch_gp_regs (regcache, tid);
773  if (tdep->ppc_fp0_regnum >= 0)
774  fetch_fp_regs (regcache, tid);
775  fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch));
776  if (tdep->ppc_ps_regnum != -1)
777  fetch_register (regcache, tid, tdep->ppc_ps_regnum);
778  if (tdep->ppc_cr_regnum != -1)
779  fetch_register (regcache, tid, tdep->ppc_cr_regnum);
780  if (tdep->ppc_lr_regnum != -1)
781  fetch_register (regcache, tid, tdep->ppc_lr_regnum);
782  if (tdep->ppc_ctr_regnum != -1)
783  fetch_register (regcache, tid, tdep->ppc_ctr_regnum);
784  if (tdep->ppc_xer_regnum != -1)
785  fetch_register (regcache, tid, tdep->ppc_xer_regnum);
786  if (tdep->ppc_mq_regnum != -1)
787  fetch_register (regcache, tid, tdep->ppc_mq_regnum);
788  if (ppc_linux_trap_reg_p (gdbarch))
789  {
790  fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM);
791  fetch_register (regcache, tid, PPC_TRAP_REGNUM);
792  }
793  if (tdep->ppc_fpscr_regnum != -1)
794  fetch_register (regcache, tid, tdep->ppc_fpscr_regnum);
796  if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
797  fetch_altivec_registers (regcache, tid);
799  if (tdep->ppc_vsr0_upper_regnum != -1)
800  fetch_vsx_registers (regcache, tid);
801  if (tdep->ppc_ev0_upper_regnum >= 0)
802  fetch_spe_register (regcache, tid, -1);
803 }
804 
805 /* Fetch registers from the child process. Fetch all registers if
806  regno == -1, otherwise fetch all general registers or all floating
807  point registers depending upon the value of regno. */
808 static void
810  struct regcache *regcache, int regno)
811 {
812  /* Overload thread id onto process id. */
813  int tid = ptid_get_lwp (inferior_ptid);
814 
815  /* No thread id, just use process id. */
816  if (tid == 0)
817  tid = ptid_get_pid (inferior_ptid);
818 
819  if (regno == -1)
820  fetch_ppc_registers (regcache, tid);
821  else
822  fetch_register (regcache, tid, regno);
823 }
824 
825 /* Store one VSX register. */
826 static void
827 store_vsx_register (const struct regcache *regcache, int tid, int regno)
828 {
829  int ret;
831  struct gdbarch *gdbarch = get_regcache_arch (regcache);
832  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
833  int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
834 
835  ret = ptrace (PTRACE_GETVSXREGS, tid, 0, &regs);
836  if (ret < 0)
837  {
838  if (errno == EIO)
839  {
841  return;
842  }
843  perror_with_name (_("Unable to fetch VSX register"));
844  }
845 
846  regcache_raw_collect (regcache, regno, regs +
847  (regno - tdep->ppc_vsr0_upper_regnum) * vsxregsize);
848 
849  ret = ptrace (PTRACE_SETVSXREGS, tid, 0, &regs);
850  if (ret < 0)
851  perror_with_name (_("Unable to store VSX register"));
852 }
853 
854 /* Store one register. */
855 static void
856 store_altivec_register (const struct regcache *regcache, int tid, int regno)
857 {
858  int ret;
859  int offset = 0;
861  struct gdbarch *gdbarch = get_regcache_arch (regcache);
862  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
863  int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
864 
865  ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
866  if (ret < 0)
867  {
868  if (errno == EIO)
869  {
871  return;
872  }
873  perror_with_name (_("Unable to fetch AltiVec register"));
874  }
875 
876  /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
877  long on the hardware. */
878  if (regno == (tdep->ppc_vrsave_regnum - 1))
879  offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
880 
881  regcache_raw_collect (regcache, regno,
882  regs + (regno
883  - tdep->ppc_vr0_regnum) * vrregsize + offset);
884 
885  ret = ptrace (PTRACE_SETVRREGS, tid, 0, &regs);
886  if (ret < 0)
887  perror_with_name (_("Unable to store AltiVec register"));
888 }
889 
890 /* Assuming TID referrs to an SPE process, set the top halves of TID's
891  general-purpose registers and its SPE-specific registers to the
892  values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do
893  nothing.
894 
895  All the logic to deal with whether or not the PTRACE_GETEVRREGS and
896  PTRACE_SETEVRREGS requests are supported is isolated here, and in
897  get_spe_registers. */
898 static void
899 set_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
900 {
902  {
903  if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0)
904  return;
905  else
906  {
907  /* EIO means that the PTRACE_SETEVRREGS request isn't
908  supported; we fail silently, and don't try the call
909  again. */
910  if (errno == EIO)
912  else
913  /* Anything else needs to be reported. */
914  perror_with_name (_("Unable to set SPE registers"));
915  }
916  }
917 }
918 
919 /* Write GDB's value for the SPE-specific raw register REGNO to TID.
920  If REGNO is -1, write the values of all the SPE-specific
921  registers. */
922 static void
923 store_spe_register (const struct regcache *regcache, int tid, int regno)
924 {
925  struct gdbarch *gdbarch = get_regcache_arch (regcache);
926  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
927  struct gdb_evrregset_t evrregs;
928 
929  gdb_assert (sizeof (evrregs.evr[0])
930  == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
931  gdb_assert (sizeof (evrregs.acc)
932  == register_size (gdbarch, tdep->ppc_acc_regnum));
933  gdb_assert (sizeof (evrregs.spefscr)
934  == register_size (gdbarch, tdep->ppc_spefscr_regnum));
935 
936  if (regno == -1)
937  /* Since we're going to write out every register, the code below
938  should store to every field of evrregs; if that doesn't happen,
939  make it obvious by initializing it with suspicious values. */
940  memset (&evrregs, 42, sizeof (evrregs));
941  else
942  /* We can only read and write the entire EVR register set at a
943  time, so to write just a single register, we do a
944  read-modify-write maneuver. */
945  get_spe_registers (tid, &evrregs);
946 
947  if (regno == -1)
948  {
949  int i;
950 
951  for (i = 0; i < ppc_num_gprs; i++)
952  regcache_raw_collect (regcache,
953  tdep->ppc_ev0_upper_regnum + i,
954  &evrregs.evr[i]);
955  }
956  else if (tdep->ppc_ev0_upper_regnum <= regno
957  && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
958  regcache_raw_collect (regcache, regno,
959  &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
960 
961  if (regno == -1
962  || regno == tdep->ppc_acc_regnum)
963  regcache_raw_collect (regcache,
964  tdep->ppc_acc_regnum,
965  &evrregs.acc);
966 
967  if (regno == -1
968  || regno == tdep->ppc_spefscr_regnum)
969  regcache_raw_collect (regcache,
970  tdep->ppc_spefscr_regnum,
971  &evrregs.spefscr);
972 
973  /* Write back the modified register set. */
974  set_spe_registers (tid, &evrregs);
975 }
976 
977 static void
978 store_register (const struct regcache *regcache, int tid, int regno)
979 {
980  struct gdbarch *gdbarch = get_regcache_arch (regcache);
981  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
982  /* This isn't really an address. But ptrace thinks of it as one. */
983  CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);
984  int i;
985  size_t bytes_to_transfer;
987 
988  if (altivec_register_p (gdbarch, regno))
989  {
990  store_altivec_register (regcache, tid, regno);
991  return;
992  }
993  if (vsx_register_p (gdbarch, regno))
994  {
995  store_vsx_register (regcache, tid, regno);
996  return;
997  }
998  else if (spe_register_p (gdbarch, regno))
999  {
1000  store_spe_register (regcache, tid, regno);
1001  return;
1002  }
1003 
1004  if (regaddr == -1)
1005  return;
1006 
1007  /* First collect the register. Keep in mind that the regcache's
1008  idea of the register's size may not be a multiple of sizeof
1009  (long). */
1010  memset (buf, 0, sizeof buf);
1011  bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long));
1012  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1013  {
1014  /* Little-endian values always sit at the left end of the buffer. */
1015  regcache_raw_collect (regcache, regno, buf);
1016  }
1017  else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1018  {
1019  /* Big-endian values sit at the right end of the buffer. */
1020  size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
1021  regcache_raw_collect (regcache, regno, buf + padding);
1022  }
1023 
1024  for (i = 0; i < bytes_to_transfer; i += sizeof (long))
1025  {
1026  long l;
1027 
1028  memcpy (&l, &buf[i], sizeof (l));
1029  errno = 0;
1030  ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l);
1031  regaddr += sizeof (long);
1032 
1033  if (errno == EIO
1034  && (regno == tdep->ppc_fpscr_regnum
1035  || regno == PPC_ORIG_R3_REGNUM
1036  || regno == PPC_TRAP_REGNUM))
1037  {
1038  /* Some older kernel versions don't allow fpscr, orig_r3
1039  or trap to be written. */
1040  continue;
1041  }
1042 
1043  if (errno != 0)
1044  {
1045  char message[128];
1046  xsnprintf (message, sizeof (message), "writing register %s (#%d)",
1047  gdbarch_register_name (gdbarch, regno), regno);
1048  perror_with_name (message);
1049  }
1050  }
1051 }
1052 
1053 static void
1054 fill_vsxregset (const struct regcache *regcache, gdb_vsxregset_t *vsxregsetp)
1055 {
1056  int i;
1057  struct gdbarch *gdbarch = get_regcache_arch (regcache);
1058  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1059  int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
1060 
1061  for (i = 0; i < ppc_num_vshrs; i++)
1062  regcache_raw_collect (regcache, tdep->ppc_vsr0_upper_regnum + i,
1063  *vsxregsetp + i * vsxregsize);
1064 }
1065 
1066 static void
1067 fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp)
1068 {
1069  int i;
1070  struct gdbarch *gdbarch = get_regcache_arch (regcache);
1071  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1072  int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
1073  int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
1074  int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
1075 
1076  for (i = 0; i < num_of_vrregs; i++)
1077  {
1078  /* The last 2 registers of this set are only 32 bit long, not
1079  128, but only VSCR is fetched as a 16 bytes quantity. */
1080  if (i == (num_of_vrregs - 2))
1081  regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i,
1082  *vrregsetp + i * vrregsize + offset);
1083  else
1084  regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i,
1085  *vrregsetp + i * vrregsize);
1086  }
1087 }
1088 
1089 static void
1090 store_vsx_registers (const struct regcache *regcache, int tid)
1091 {
1092  int ret;
1094 
1095  ret = ptrace (PTRACE_GETVSXREGS, tid, 0, &regs);
1096  if (ret < 0)
1097  {
1098  if (errno == EIO)
1099  {
1101  return;
1102  }
1103  perror_with_name (_("Couldn't get VSX registers"));
1104  }
1105 
1106  fill_vsxregset (regcache, &regs);
1107 
1108  if (ptrace (PTRACE_SETVSXREGS, tid, 0, &regs) < 0)
1109  perror_with_name (_("Couldn't write VSX registers"));
1110 }
1111 
1112 static void
1114 {
1115  int ret;
1117 
1118  ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
1119  if (ret < 0)
1120  {
1121  if (errno == EIO)
1122  {
1124  return;
1125  }
1126  perror_with_name (_("Couldn't get AltiVec registers"));
1127  }
1128 
1129  fill_vrregset (regcache, &regs);
1130 
1131  if (ptrace (PTRACE_SETVRREGS, tid, 0, &regs) < 0)
1132  perror_with_name (_("Couldn't write AltiVec registers"));
1133 }
1134 
1135 /* This function actually issues the request to ptrace, telling
1136  it to store all general-purpose registers present in the specified
1137  regset.
1138 
1139  If the ptrace request does not exist, this function returns 0
1140  and properly sets the have_ptrace_* flag. If the request fails,
1141  this function calls perror_with_name. Otherwise, if the request
1142  succeeds, then the regcache is stored and 1 is returned. */
1143 static int
1144 store_all_gp_regs (const struct regcache *regcache, int tid, int regno)
1145 {
1146  struct gdbarch *gdbarch = get_regcache_arch (regcache);
1147  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1149 
1150  if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
1151  {
1152  if (errno == EIO)
1153  {
1155  return 0;
1156  }
1157  perror_with_name (_("Couldn't get general-purpose registers."));
1158  }
1159 
1160  fill_gregset (regcache, &gregset, regno);
1161 
1162  if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0)
1163  {
1164  if (errno == EIO)
1165  {
1167  return 0;
1168  }
1169  perror_with_name (_("Couldn't set general-purpose registers."));
1170  }
1171 
1172  return 1;
1173 }
1174 
1175 /* This is a wrapper for the store_all_gp_regs function. It is
1176  responsible for verifying if this target has the ptrace request
1177  that can be used to store all general-purpose registers at one
1178  shot. If it doesn't, then we should store them using the
1179  old-fashioned way, which is to iterate over the registers and
1180  store them one by one. */
1181 static void
1182 store_gp_regs (const struct regcache *regcache, int tid, int regno)
1183 {
1184  struct gdbarch *gdbarch = get_regcache_arch (regcache);
1185  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1186  int i;
1187 
1189  if (store_all_gp_regs (regcache, tid, regno))
1190  return;
1191 
1192  /* If we hit this point, it doesn't really matter which
1193  architecture we are using. We just need to store the
1194  registers in the "old-fashioned way". */
1195  for (i = 0; i < ppc_num_gprs; i++)
1196  store_register (regcache, tid, tdep->ppc_gp0_regnum + i);
1197 }
1198 
1199 /* This function actually issues the request to ptrace, telling
1200  it to store all floating-point registers present in the specified
1201  regset.
1202 
1203  If the ptrace request does not exist, this function returns 0
1204  and properly sets the have_ptrace_* flag. If the request fails,
1205  this function calls perror_with_name. Otherwise, if the request
1206  succeeds, then the regcache is stored and 1 is returned. */
1207 static int
1208 store_all_fp_regs (const struct regcache *regcache, int tid, int regno)
1209 {
1210  gdb_fpregset_t fpregs;
1211 
1212  if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0)
1213  {
1214  if (errno == EIO)
1215  {
1217  return 0;
1218  }
1219  perror_with_name (_("Couldn't get floating-point registers."));
1220  }
1221 
1222  fill_fpregset (regcache, &fpregs, regno);
1223 
1224  if (ptrace (PTRACE_SETFPREGS, tid, 0, (void *) &fpregs) < 0)
1225  {
1226  if (errno == EIO)
1227  {
1229  return 0;
1230  }
1231  perror_with_name (_("Couldn't set floating-point registers."));
1232  }
1233 
1234  return 1;
1235 }
1236 
1237 /* This is a wrapper for the store_all_fp_regs function. It is
1238  responsible for verifying if this target has the ptrace request
1239  that can be used to store all floating-point registers at one
1240  shot. If it doesn't, then we should store them using the
1241  old-fashioned way, which is to iterate over the registers and
1242  store them one by one. */
1243 static void
1244 store_fp_regs (const struct regcache *regcache, int tid, int regno)
1245 {
1246  struct gdbarch *gdbarch = get_regcache_arch (regcache);
1247  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1248  int i;
1249 
1251  if (store_all_fp_regs (regcache, tid, regno))
1252  return;
1253 
1254  /* If we hit this point, it doesn't really matter which
1255  architecture we are using. We just need to store the
1256  registers in the "old-fashioned way". */
1257  for (i = 0; i < ppc_num_fprs; i++)
1258  store_register (regcache, tid, tdep->ppc_fp0_regnum + i);
1259 }
1260 
1261 static void
1262 store_ppc_registers (const struct regcache *regcache, int tid)
1263 {
1264  int i;
1265  struct gdbarch *gdbarch = get_regcache_arch (regcache);
1266  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1267 
1268  store_gp_regs (regcache, tid, -1);
1269  if (tdep->ppc_fp0_regnum >= 0)
1270  store_fp_regs (regcache, tid, -1);
1271  store_register (regcache, tid, gdbarch_pc_regnum (gdbarch));
1272  if (tdep->ppc_ps_regnum != -1)
1273  store_register (regcache, tid, tdep->ppc_ps_regnum);
1274  if (tdep->ppc_cr_regnum != -1)
1275  store_register (regcache, tid, tdep->ppc_cr_regnum);
1276  if (tdep->ppc_lr_regnum != -1)
1277  store_register (regcache, tid, tdep->ppc_lr_regnum);
1278  if (tdep->ppc_ctr_regnum != -1)
1279  store_register (regcache, tid, tdep->ppc_ctr_regnum);
1280  if (tdep->ppc_xer_regnum != -1)
1281  store_register (regcache, tid, tdep->ppc_xer_regnum);
1282  if (tdep->ppc_mq_regnum != -1)
1283  store_register (regcache, tid, tdep->ppc_mq_regnum);
1284  if (tdep->ppc_fpscr_regnum != -1)
1285  store_register (regcache, tid, tdep->ppc_fpscr_regnum);
1286  if (ppc_linux_trap_reg_p (gdbarch))
1287  {
1288  store_register (regcache, tid, PPC_ORIG_R3_REGNUM);
1289  store_register (regcache, tid, PPC_TRAP_REGNUM);
1290  }
1292  if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
1293  store_altivec_registers (regcache, tid);
1295  if (tdep->ppc_vsr0_upper_regnum != -1)
1296  store_vsx_registers (regcache, tid);
1297  if (tdep->ppc_ev0_upper_regnum >= 0)
1298  store_spe_register (regcache, tid, -1);
1299 }
1300 
1301 /* Fetch the AT_HWCAP entry from the aux vector. */
1302 static unsigned long
1304 {
1305  CORE_ADDR field;
1306 
1307  if (target_auxv_search (&current_target, AT_HWCAP, &field))
1308  return (unsigned long) field;
1309 
1310  return 0;
1311 }
1312 
1313 /* The cached DABR value, to install in new threads.
1314  This variable is used when the PowerPC HWDEBUG ptrace
1315  interface is not available. */
1316 static long saved_dabr_value;
1317 
1318 /* Global structure that will store information about the available
1319  features provided by the PowerPC HWDEBUG ptrace interface. */
1321 
1322 /* Global variable that holds the maximum number of slots that the
1323  kernel will use. This is only used when PowerPC HWDEBUG ptrace interface
1324  is available. */
1325 static size_t max_slots_number = 0;
1326 
1328 {
1329  long slot;
1331 };
1332 
1333 /* This is an internal VEC created to store information about *points inserted
1334  for each thread. This is used when PowerPC HWDEBUG ptrace interface is
1335  available. */
1336 typedef struct thread_points
1337  {
1338  /* The TID to which this *point relates. */
1339  int tid;
1340  /* Information about the *point, such as its address, type, etc.
1341 
1342  Each element inside this vector corresponds to a hardware
1343  breakpoint or watchpoint in the thread represented by TID. The maximum
1344  size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of
1345  the tuple is NULL, then the position in the vector is free. */
1347  } *thread_points_p;
1349 
1350 VEC(thread_points_p) *ppc_threads = NULL;
1351 
1352 /* The version of the PowerPC HWDEBUG kernel interface that we will use, if
1353  available. */
1354 #define PPC_DEBUG_CURRENT_VERSION 1
1355 
1356 /* Returns non-zero if we support the PowerPC HWDEBUG ptrace interface. */
1357 static int
1358 have_ptrace_hwdebug_interface (void)
1359 {
1360  static int have_ptrace_hwdebug_interface = -1;
1361 
1362  if (have_ptrace_hwdebug_interface == -1)
1363  {
1364  int tid;
1365 
1366  tid = ptid_get_lwp (inferior_ptid);
1367  if (tid == 0)
1368  tid = ptid_get_pid (inferior_ptid);
1369 
1370  /* Check for kernel support for PowerPC HWDEBUG ptrace interface. */
1371  if (ptrace (PPC_PTRACE_GETHWDBGINFO, tid, 0, &hwdebug_info) >= 0)
1372  {
1373  /* Check whether PowerPC HWDEBUG ptrace interface is functional and
1374  provides any supported feature. */
1375  if (hwdebug_info.features != 0)
1376  {
1377  have_ptrace_hwdebug_interface = 1;
1381  return have_ptrace_hwdebug_interface;
1382  }
1383  }
1384  /* Old school interface and no PowerPC HWDEBUG ptrace support. */
1385  have_ptrace_hwdebug_interface = 0;
1386  memset (&hwdebug_info, 0, sizeof (struct ppc_debug_info));
1387  }
1388 
1389  return have_ptrace_hwdebug_interface;
1390 }
1391 
1392 static int
1394  int type, int cnt, int ot)
1395 {
1396  int total_hw_wp, total_hw_bp;
1397 
1398  if (have_ptrace_hwdebug_interface ())
1399  {
1400  /* When PowerPC HWDEBUG ptrace interface is available, the number of
1401  available hardware watchpoints and breakpoints is stored at the
1402  hwdebug_info struct. */
1403  total_hw_bp = hwdebug_info.num_instruction_bps;
1404  total_hw_wp = hwdebug_info.num_data_bps;
1405  }
1406  else
1407  {
1408  /* When we do not have PowerPC HWDEBUG ptrace interface, we should
1409  consider having 1 hardware watchpoint and no hardware breakpoints. */
1410  total_hw_bp = 0;
1411  total_hw_wp = 1;
1412  }
1413 
1414  if (type == bp_hardware_watchpoint || type == bp_read_watchpoint
1415  || type == bp_access_watchpoint || type == bp_watchpoint)
1416  {
1417  if (cnt + ot > total_hw_wp)
1418  return -1;
1419  }
1420  else if (type == bp_hardware_breakpoint)
1421  {
1422  if (total_hw_bp == 0)
1423  {
1424  /* No hardware breakpoint support. */
1425  return 0;
1426  }
1427  if (cnt > total_hw_bp)
1428  return -1;
1429  }
1430 
1431  if (!have_ptrace_hwdebug_interface ())
1432  {
1433  int tid;
1435 
1436  /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG
1437  and whether the target has DABR. If either answer is no, the
1438  ptrace call will return -1. Fail in that case. */
1439  tid = ptid_get_lwp (ptid);
1440  if (tid == 0)
1441  tid = ptid_get_pid (ptid);
1442 
1443  if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1)
1444  return 0;
1445  }
1446 
1447  return 1;
1448 }
1449 
1450 static int
1452  CORE_ADDR addr, int len)
1453 {
1454  /* Handle sub-8-byte quantities. */
1455  if (len <= 0)
1456  return 0;
1457 
1458  /* The PowerPC HWDEBUG ptrace interface tells if there are alignment
1459  restrictions for watchpoints in the processors. In that case, we use that
1460  information to determine the hardcoded watchable region for
1461  watchpoints. */
1462  if (have_ptrace_hwdebug_interface ())
1463  {
1464  int region_size;
1465  /* Embedded DAC-based processors, like the PowerPC 440 have ranged
1466  watchpoints and can watch any access within an arbitrary memory
1467  region. This is useful to watch arrays and structs, for instance. It
1468  takes two hardware watchpoints though. */
1469  if (len > 1
1472  return 2;
1473  /* Check if the processor provides DAWR interface. */
1475  /* DAWR interface allows to watch up to 512 byte wide ranges which
1476  can't cross a 512 byte boundary. */
1477  region_size = 512;
1478  else
1479  region_size = hwdebug_info.data_bp_alignment;
1480  /* Server processors provide one hardware watchpoint and addr+len should
1481  fall in the watchable region provided by the ptrace interface. */
1482  if (region_size
1483  && (addr + len > (addr & ~(region_size - 1)) + region_size))
1484  return 0;
1485  }
1486  /* addr+len must fall in the 8 byte watchable region for DABR-based
1487  processors (i.e., server processors). Without the new PowerPC HWDEBUG
1488  ptrace interface, DAC-based processors (i.e., embedded processors) will
1489  use addresses aligned to 4-bytes due to the way the read/write flags are
1490  passed in the old ptrace interface. */
1491  else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
1492  && (addr + len) > (addr & ~3) + 4)
1493  || (addr + len) > (addr & ~7) + 8)
1494  return 0;
1495 
1496  return 1;
1497 }
1498 
1499 /* This function compares two ppc_hw_breakpoint structs field-by-field. */
1500 static int
1502 {
1503  return (a->trigger_type == b->trigger_type
1504  && a->addr_mode == b->addr_mode
1505  && a->condition_mode == b->condition_mode
1506  && a->addr == b->addr
1507  && a->addr2 == b->addr2
1508  && a->condition_value == b->condition_value);
1509 }
1510 
1511 /* This function can be used to retrieve a thread_points by the TID of the
1512  related process/thread. If nothing has been found, and ALLOC_NEW is 0,
1513  it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the
1514  provided TID will be created and returned. */
1515 static struct thread_points *
1517 {
1518  int i;
1519  struct thread_points *t;
1520 
1521  for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, t); i++)
1522  if (t->tid == tid)
1523  return t;
1524 
1525  t = NULL;
1526 
1527  /* Do we need to allocate a new point_item
1528  if the wanted one does not exist? */
1529  if (alloc_new)
1530  {
1531  t = xmalloc (sizeof (struct thread_points));
1532  t->hw_breaks
1533  = xzalloc (max_slots_number * sizeof (struct hw_break_tuple));
1534  t->tid = tid;
1535  VEC_safe_push (thread_points_p, ppc_threads, t);
1536  }
1537 
1538  return t;
1539 }
1540 
1541 /* This function is a generic wrapper that is responsible for inserting a
1542  *point (i.e., calling `ptrace' in order to issue the request to the
1543  kernel) and registering it internally in GDB. */
1544 static void
1546 {
1547  int i;
1548  long slot;
1549  struct ppc_hw_breakpoint *p = xmalloc (sizeof (struct ppc_hw_breakpoint));
1550  struct hw_break_tuple *hw_breaks;
1551  struct cleanup *c = make_cleanup (xfree, p);
1552  struct thread_points *t;
1553  struct hw_break_tuple *tuple;
1554 
1555  memcpy (p, b, sizeof (struct ppc_hw_breakpoint));
1556 
1557  errno = 0;
1558  slot = ptrace (PPC_PTRACE_SETHWDEBUG, tid, 0, p);
1559  if (slot < 0)
1560  perror_with_name (_("Unexpected error setting breakpoint or watchpoint"));
1561 
1562  /* Everything went fine, so we have to register this *point. */
1563  t = hwdebug_find_thread_points_by_tid (tid, 1);
1564  gdb_assert (t != NULL);
1565  hw_breaks = t->hw_breaks;
1566 
1567  /* Find a free element in the hw_breaks vector. */
1568  for (i = 0; i < max_slots_number; i++)
1569  if (hw_breaks[i].hw_break == NULL)
1570  {
1571  hw_breaks[i].slot = slot;
1572  hw_breaks[i].hw_break = p;
1573  break;
1574  }
1575 
1576  gdb_assert (i != max_slots_number);
1577 
1578  discard_cleanups (c);
1579 }
1580 
1581 /* This function is a generic wrapper that is responsible for removing a
1582  *point (i.e., calling `ptrace' in order to issue the request to the
1583  kernel), and unregistering it internally at GDB. */
1584 static void
1586 {
1587  int i;
1588  struct hw_break_tuple *hw_breaks;
1589  struct thread_points *t;
1590 
1591  t = hwdebug_find_thread_points_by_tid (tid, 0);
1592  gdb_assert (t != NULL);
1593  hw_breaks = t->hw_breaks;
1594 
1595  for (i = 0; i < max_slots_number; i++)
1596  if (hw_breaks[i].hw_break && hwdebug_point_cmp (hw_breaks[i].hw_break, b))
1597  break;
1598 
1599  gdb_assert (i != max_slots_number);
1600 
1601  /* We have to ignore ENOENT errors because the kernel implements hardware
1602  breakpoints/watchpoints as "one-shot", that is, they are automatically
1603  deleted when hit. */
1604  errno = 0;
1605  if (ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot) < 0)
1606  if (errno != ENOENT)
1607  perror_with_name (_("Unexpected error deleting "
1608  "breakpoint or watchpoint"));
1609 
1610  xfree (hw_breaks[i].hw_break);
1611  hw_breaks[i].hw_break = NULL;
1612 }
1613 
1614 /* Return the number of registers needed for a ranged breakpoint. */
1615 
1616 static int
1618 {
1619  return ((have_ptrace_hwdebug_interface ()
1621  2 : -1);
1622 }
1623 
1624 /* Insert the hardware breakpoint described by BP_TGT. Returns 0 for
1625  success, 1 if hardware breakpoints are not supported or -1 for failure. */
1626 
1627 static int
1629  struct gdbarch *gdbarch,
1630  struct bp_target_info *bp_tgt)
1631 {
1632  struct lwp_info *lp;
1633  struct ppc_hw_breakpoint p;
1634 
1635  if (!have_ptrace_hwdebug_interface ())
1636  return -1;
1637 
1641  p.addr = (uint64_t) (bp_tgt->placed_address = bp_tgt->reqstd_address);
1642  p.condition_value = 0;
1643 
1644  if (bp_tgt->length)
1645  {
1647 
1648  /* The breakpoint will trigger if the address of the instruction is
1649  within the defined range, as follows: p.addr <= address < p.addr2. */
1650  p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length;
1651  }
1652  else
1653  {
1655  p.addr2 = 0;
1656  }
1657 
1658  ALL_LWPS (lp)
1660 
1661  return 0;
1662 }
1663 
1664 static int
1666  struct gdbarch *gdbarch,
1667  struct bp_target_info *bp_tgt)
1668 {
1669  struct lwp_info *lp;
1670  struct ppc_hw_breakpoint p;
1671 
1672  if (!have_ptrace_hwdebug_interface ())
1673  return -1;
1674 
1678  p.addr = (uint64_t) bp_tgt->placed_address;
1679  p.condition_value = 0;
1680 
1681  if (bp_tgt->length)
1682  {
1684 
1685  /* The breakpoint will trigger if the address of the instruction is within
1686  the defined range, as follows: p.addr <= address < p.addr2. */
1687  p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length;
1688  }
1689  else
1690  {
1692  p.addr2 = 0;
1693  }
1694 
1695  ALL_LWPS (lp)
1697 
1698  return 0;
1699 }
1700 
1701 static int
1703 {
1704  int t;
1705 
1706  if (rw == hw_read)
1708  else if (rw == hw_write)
1710  else
1712 
1713  return t;
1714 }
1715 
1716 /* Insert a new masked watchpoint at ADDR using the mask MASK.
1717  RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1718  or hw_access for an access watchpoint. Returns 0 on success and throws
1719  an error on failure. */
1720 
1721 static int
1723  CORE_ADDR mask, int rw)
1724 {
1725  struct lwp_info *lp;
1726  struct ppc_hw_breakpoint p;
1727 
1728  gdb_assert (have_ptrace_hwdebug_interface ());
1729 
1731  p.trigger_type = get_trigger_type (rw);
1734  p.addr = addr;
1735  p.addr2 = mask;
1736  p.condition_value = 0;
1737 
1738  ALL_LWPS (lp)
1740 
1741  return 0;
1742 }
1743 
1744 /* Remove a masked watchpoint at ADDR with the mask MASK.
1745  RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1746  or hw_access for an access watchpoint. Returns 0 on success and throws
1747  an error on failure. */
1748 
1749 static int
1751  CORE_ADDR mask, int rw)
1752 {
1753  struct lwp_info *lp;
1754  struct ppc_hw_breakpoint p;
1755 
1756  gdb_assert (have_ptrace_hwdebug_interface ());
1757 
1759  p.trigger_type = get_trigger_type (rw);
1762  p.addr = addr;
1763  p.addr2 = mask;
1764  p.condition_value = 0;
1765 
1766  ALL_LWPS (lp)
1768 
1769  return 0;
1770 }
1771 
1772 /* Check whether we have at least one free DVC register. */
1773 static int
1775 {
1776  struct thread_points *p;
1777  int tid = ptid_get_lwp (inferior_ptid);
1778  int cnt = hwdebug_info.num_condition_regs, i;
1779  CORE_ADDR tmp_value;
1780 
1781  if (!have_ptrace_hwdebug_interface () || cnt == 0)
1782  return 0;
1783 
1784  p = hwdebug_find_thread_points_by_tid (tid, 0);
1785 
1786  if (p)
1787  {
1788  for (i = 0; i < max_slots_number; i++)
1789  if (p->hw_breaks[i].hw_break != NULL
1790  && (p->hw_breaks[i].hw_break->condition_mode
1792  cnt--;
1793 
1794  /* There are no available slots now. */
1795  if (cnt <= 0)
1796  return 0;
1797  }
1798 
1799  return 1;
1800 }
1801 
1802 /* Calculate the enable bits and the contents of the Data Value Compare
1803  debug register present in BookE processors.
1804 
1805  ADDR is the address to be watched, LEN is the length of watched data
1806  and DATA_VALUE is the value which will trigger the watchpoint.
1807  On exit, CONDITION_MODE will hold the enable bits for the DVC, and
1808  CONDITION_VALUE will hold the value which should be put in the
1809  DVC register. */
1810 static void
1811 calculate_dvc (CORE_ADDR addr, int len, CORE_ADDR data_value,
1812  uint32_t *condition_mode, uint64_t *condition_value)
1813 {
1814  int i, num_byte_enable, align_offset, num_bytes_off_dvc,
1815  rightmost_enabled_byte;
1816  CORE_ADDR addr_end_data, addr_end_dvc;
1817 
1818  /* The DVC register compares bytes within fixed-length windows which
1819  are word-aligned, with length equal to that of the DVC register.
1820  We need to calculate where our watch region is relative to that
1821  window and enable comparison of the bytes which fall within it. */
1822 
1823  align_offset = addr % hwdebug_info.sizeof_condition;
1824  addr_end_data = addr + len;
1825  addr_end_dvc = (addr - align_offset
1827  num_bytes_off_dvc = (addr_end_data > addr_end_dvc)?
1828  addr_end_data - addr_end_dvc : 0;
1829  num_byte_enable = len - num_bytes_off_dvc;
1830  /* Here, bytes are numbered from right to left. */
1831  rightmost_enabled_byte = (addr_end_data < addr_end_dvc)?
1832  addr_end_dvc - addr_end_data : 0;
1833 
1834  *condition_mode = PPC_BREAKPOINT_CONDITION_AND;
1835  for (i = 0; i < num_byte_enable; i++)
1836  *condition_mode
1837  |= PPC_BREAKPOINT_CONDITION_BE (i + rightmost_enabled_byte);
1838 
1839  /* Now we need to match the position within the DVC of the comparison
1840  value with where the watch region is relative to the window
1841  (i.e., the ALIGN_OFFSET). */
1842 
1843  *condition_value = ((uint64_t) data_value >> num_bytes_off_dvc * 8
1844  << rightmost_enabled_byte * 8);
1845 }
1846 
1847 /* Return the number of memory locations that need to be accessed to
1848  evaluate the expression which generated the given value chain.
1849  Returns -1 if there's any register access involved, or if there are
1850  other kinds of values which are not acceptable in a condition
1851  expression (e.g., lval_computed or lval_internalvar). */
1852 static int
1854 {
1855  int found_memory_cnt = 0;
1856  struct value *head = v;
1857 
1858  /* The idea here is that evaluating an expression generates a series
1859  of values, one holding the value of every subexpression. (The
1860  expression a*b+c has five subexpressions: a, b, a*b, c, and
1861  a*b+c.) GDB's values hold almost enough information to establish
1862  the criteria given above --- they identify memory lvalues,
1863  register lvalues, computed values, etcetera. So we can evaluate
1864  the expression, and then scan the chain of values that leaves
1865  behind to determine the memory locations involved in the evaluation
1866  of an expression.
1867 
1868  However, I don't think that the values returned by inferior
1869  function calls are special in any way. So this function may not
1870  notice that an expression contains an inferior function call.
1871  FIXME. */
1872 
1873  for (; v; v = value_next (v))
1874  {
1875  /* Constants and values from the history are fine. */
1876  if (VALUE_LVAL (v) == not_lval || deprecated_value_modifiable (v) == 0)
1877  continue;
1878  else if (VALUE_LVAL (v) == lval_memory)
1879  {
1880  /* A lazy memory lvalue is one that GDB never needed to fetch;
1881  we either just used its address (e.g., `a' in `a.b') or
1882  we never needed it at all (e.g., `a' in `a,b'). */
1883  if (!value_lazy (v))
1884  found_memory_cnt++;
1885  }
1886  /* Other kinds of values are not fine. */
1887  else
1888  return -1;
1889  }
1890 
1891  return found_memory_cnt;
1892 }
1893 
1894 /* Verifies whether the expression COND can be implemented using the
1895  DVC (Data Value Compare) register in BookE processors. The expression
1896  must test the watch value for equality with a constant expression.
1897  If the function returns 1, DATA_VALUE will contain the constant against
1898  which the watch value should be compared and LEN will contain the size
1899  of the constant. */
1900 static int
1901 check_condition (CORE_ADDR watch_addr, struct expression *cond,
1902  CORE_ADDR *data_value, int *len)
1903 {
1904  int pc = 1, num_accesses_left, num_accesses_right;
1905  struct value *left_val, *right_val, *left_chain, *right_chain;
1906 
1907  if (cond->elts[0].opcode != BINOP_EQUAL)
1908  return 0;
1909 
1910  fetch_subexp_value (cond, &pc, &left_val, NULL, &left_chain, 0);
1911  num_accesses_left = num_memory_accesses (left_chain);
1912 
1913  if (left_val == NULL || num_accesses_left < 0)
1914  {
1915  free_value_chain (left_chain);
1916 
1917  return 0;
1918  }
1919 
1920  fetch_subexp_value (cond, &pc, &right_val, NULL, &right_chain, 0);
1921  num_accesses_right = num_memory_accesses (right_chain);
1922 
1923  if (right_val == NULL || num_accesses_right < 0)
1924  {
1925  free_value_chain (left_chain);
1926  free_value_chain (right_chain);
1927 
1928  return 0;
1929  }
1930 
1931  if (num_accesses_left == 1 && num_accesses_right == 0
1932  && VALUE_LVAL (left_val) == lval_memory
1933  && value_address (left_val) == watch_addr)
1934  {
1935  *data_value = value_as_long (right_val);
1936 
1937  /* DATA_VALUE is the constant in RIGHT_VAL, but actually has
1938  the same type as the memory region referenced by LEFT_VAL. */
1939  *len = TYPE_LENGTH (check_typedef (value_type (left_val)));
1940  }
1941  else if (num_accesses_left == 0 && num_accesses_right == 1
1942  && VALUE_LVAL (right_val) == lval_memory
1943  && value_address (right_val) == watch_addr)
1944  {
1945  *data_value = value_as_long (left_val);
1946 
1947  /* DATA_VALUE is the constant in LEFT_VAL, but actually has
1948  the same type as the memory region referenced by RIGHT_VAL. */
1949  *len = TYPE_LENGTH (check_typedef (value_type (right_val)));
1950  }
1951  else
1952  {
1953  free_value_chain (left_chain);
1954  free_value_chain (right_chain);
1955 
1956  return 0;
1957  }
1958 
1959  free_value_chain (left_chain);
1960  free_value_chain (right_chain);
1961 
1962  return 1;
1963 }
1964 
1965 /* Return non-zero if the target is capable of using hardware to evaluate
1966  the condition expression, thus only triggering the watchpoint when it is
1967  true. */
1968 static int
1970  CORE_ADDR addr, int len, int rw,
1971  struct expression *cond)
1972 {
1973  CORE_ADDR data_value;
1974 
1975  return (have_ptrace_hwdebug_interface ()
1977  && check_condition (addr, cond, &data_value, &len));
1978 }
1979 
1980 /* Set up P with the parameters necessary to request a watchpoint covering
1981  LEN bytes starting at ADDR and if possible with condition expression COND
1982  evaluated by hardware. INSERT tells if we are creating a request for
1983  inserting or removing the watchpoint. */
1984 
1985 static void
1987  int len, int rw, struct expression *cond,
1988  int insert)
1989 {
1990  if (len == 1
1992  {
1993  int use_condition;
1994  CORE_ADDR data_value;
1995 
1996  use_condition = (insert? can_use_watchpoint_cond_accel ()
1998  if (cond && use_condition && check_condition (addr, cond,
1999  &data_value, &len))
2000  calculate_dvc (addr, len, data_value, &p->condition_mode,
2001  &p->condition_value);
2002  else
2003  {
2005  p->condition_value = 0;
2006  }
2007 
2009  p->addr2 = 0;
2010  }
2011  else
2012  {
2015  p->condition_value = 0;
2016 
2017  /* The watchpoint will trigger if the address of the memory access is
2018  within the defined range, as follows: p->addr <= address < p->addr2.
2019 
2020  Note that the above sentence just documents how ptrace interprets
2021  its arguments; the watchpoint is set to watch the range defined by
2022  the user _inclusively_, as specified by the user interface. */
2023  p->addr2 = (uint64_t) addr + len;
2024  }
2025 
2027  p->trigger_type = get_trigger_type (rw);
2028  p->addr = (uint64_t) addr;
2029 }
2030 
2031 static int
2033  CORE_ADDR addr, int len, int rw,
2034  struct expression *cond)
2035 {
2036  struct lwp_info *lp;
2037  int ret = -1;
2038 
2039  if (have_ptrace_hwdebug_interface ())
2040  {
2041  struct ppc_hw_breakpoint p;
2042 
2043  create_watchpoint_request (&p, addr, len, rw, cond, 1);
2044 
2045  ALL_LWPS (lp)
2047 
2048  ret = 0;
2049  }
2050  else
2051  {
2052  long dabr_value;
2053  long read_mode, write_mode;
2054 
2056  {
2057  /* PowerPC 440 requires only the read/write flags to be passed
2058  to the kernel. */
2059  read_mode = 1;
2060  write_mode = 2;
2061  }
2062  else
2063  {
2064  /* PowerPC 970 and other DABR-based processors are required to pass
2065  the Breakpoint Translation bit together with the flags. */
2066  read_mode = 5;
2067  write_mode = 6;
2068  }
2069 
2070  dabr_value = addr & ~(read_mode | write_mode);
2071  switch (rw)
2072  {
2073  case hw_read:
2074  /* Set read and translate bits. */
2075  dabr_value |= read_mode;
2076  break;
2077  case hw_write:
2078  /* Set write and translate bits. */
2079  dabr_value |= write_mode;
2080  break;
2081  case hw_access:
2082  /* Set read, write and translate bits. */
2083  dabr_value |= read_mode | write_mode;
2084  break;
2085  }
2086 
2087  saved_dabr_value = dabr_value;
2088 
2089  ALL_LWPS (lp)
2091  saved_dabr_value) < 0)
2092  return -1;
2093 
2094  ret = 0;
2095  }
2096 
2097  return ret;
2098 }
2099 
2100 static int
2102  CORE_ADDR addr, int len, int rw,
2103  struct expression *cond)
2104 {
2105  struct lwp_info *lp;
2106  int ret = -1;
2107 
2108  if (have_ptrace_hwdebug_interface ())
2109  {
2110  struct ppc_hw_breakpoint p;
2111 
2112  create_watchpoint_request (&p, addr, len, rw, cond, 0);
2113 
2114  ALL_LWPS (lp)
2116 
2117  ret = 0;
2118  }
2119  else
2120  {
2121  saved_dabr_value = 0;
2122  ALL_LWPS (lp)
2124  saved_dabr_value) < 0)
2125  return -1;
2126 
2127  ret = 0;
2128  }
2129 
2130  return ret;
2131 }
2132 
2133 static void
2135 {
2136  int tid = ptid_get_lwp (lp->ptid);
2137 
2138  if (have_ptrace_hwdebug_interface ())
2139  {
2140  int i;
2141  struct thread_points *p;
2142  struct hw_break_tuple *hw_breaks;
2143 
2144  if (VEC_empty (thread_points_p, ppc_threads))
2145  return;
2146 
2147  /* Get a list of breakpoints from any thread. */
2148  p = VEC_last (thread_points_p, ppc_threads);
2149  hw_breaks = p->hw_breaks;
2150 
2151  /* Copy that thread's breakpoints and watchpoints to the new thread. */
2152  for (i = 0; i < max_slots_number; i++)
2153  if (hw_breaks[i].hw_break)
2154  {
2155  /* Older kernels did not make new threads inherit their parent
2156  thread's debug state, so we always clear the slot and replicate
2157  the debug state ourselves, ensuring compatibility with all
2158  kernels. */
2159 
2160  /* The ppc debug resource accounting is done through "slots".
2161  Ask the kernel the deallocate this specific *point's slot. */
2162  ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot);
2163 
2164  hwdebug_insert_point (hw_breaks[i].hw_break, tid);
2165  }
2166  }
2167  else
2169 }
2170 
2171 static void
2172 ppc_linux_thread_exit (struct thread_info *tp, int silent)
2173 {
2174  int i;
2175  int tid = ptid_get_lwp (tp->ptid);
2176  struct hw_break_tuple *hw_breaks;
2177  struct thread_points *t = NULL, *p;
2178 
2179  if (!have_ptrace_hwdebug_interface ())
2180  return;
2181 
2182  for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, p); i++)
2183  if (p->tid == tid)
2184  {
2185  t = p;
2186  break;
2187  }
2188 
2189  if (t == NULL)
2190  return;
2191 
2192  VEC_unordered_remove (thread_points_p, ppc_threads, i);
2193 
2194  hw_breaks = t->hw_breaks;
2195 
2196  for (i = 0; i < max_slots_number; i++)
2197  if (hw_breaks[i].hw_break)
2198  xfree (hw_breaks[i].hw_break);
2199 
2200  xfree (t->hw_breaks);
2201  xfree (t);
2202 }
2203 
2204 static int
2206 {
2207  siginfo_t siginfo;
2208 
2209  if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
2210  return 0;
2211 
2212  if (siginfo.si_signo != SIGTRAP
2213  || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
2214  return 0;
2215 
2216  if (have_ptrace_hwdebug_interface ())
2217  {
2218  int i;
2219  struct thread_points *t;
2220  struct hw_break_tuple *hw_breaks;
2221  /* The index (or slot) of the *point is passed in the si_errno field. */
2222  int slot = siginfo.si_errno;
2223 
2225 
2226  /* Find out if this *point is a hardware breakpoint.
2227  If so, we should return 0. */
2228  if (t)
2229  {
2230  hw_breaks = t->hw_breaks;
2231  for (i = 0; i < max_slots_number; i++)
2232  if (hw_breaks[i].hw_break && hw_breaks[i].slot == slot
2233  && hw_breaks[i].hw_break->trigger_type
2235  return 0;
2236  }
2237  }
2238 
2239  *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr;
2240  return 1;
2241 }
2242 
2243 static int
2245 {
2246  CORE_ADDR addr;
2247  return ppc_linux_stopped_data_address (ops, &addr);
2248 }
2249 
2250 static int
2252  CORE_ADDR addr,
2253  CORE_ADDR start, int length)
2254 {
2255  int mask;
2256 
2257  if (have_ptrace_hwdebug_interface ()
2259  return start <= addr && start + length >= addr;
2260  else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
2261  mask = 3;
2262  else
2263  mask = 7;
2264 
2265  addr &= ~mask;
2266 
2267  /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */
2268  return start <= addr + mask && start + length - 1 >= addr;
2269 }
2270 
2271 /* Return the number of registers needed for a masked hardware watchpoint. */
2272 
2273 static int
2275  CORE_ADDR addr, CORE_ADDR mask)
2276 {
2277  if (!have_ptrace_hwdebug_interface ()
2279  return -1;
2280  else if ((mask & 0xC0000000) != 0xC0000000)
2281  {
2282  warning (_("The given mask covers kernel address space "
2283  "and cannot be used.\n"));
2284 
2285  return -2;
2286  }
2287  else
2288  return 2;
2289 }
2290 
2291 static void
2293  struct regcache *regcache, int regno)
2294 {
2295  /* Overload thread id onto process id. */
2296  int tid = ptid_get_lwp (inferior_ptid);
2297 
2298  /* No thread id, just use process id. */
2299  if (tid == 0)
2300  tid = ptid_get_pid (inferior_ptid);
2301 
2302  if (regno >= 0)
2303  store_register (regcache, tid, regno);
2304  else
2305  store_ppc_registers (regcache, tid);
2306 }
2307 
2308 /* Functions for transferring registers between a gregset_t or fpregset_t
2309  (see sys/ucontext.h) and gdb's regcache. The word size is that used
2310  by the ptrace interface, not the current program's ABI. Eg. if a
2311  powerpc64-linux gdb is being used to debug a powerpc32-linux app, we
2312  read or write 64-bit gregsets. This is to suit the host libthread_db. */
2313 
2314 void
2315 supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
2316 {
2317  const struct regset *regset = ppc_linux_gregset (sizeof (long));
2318 
2319  ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp));
2320 }
2321 
2322 void
2324  gdb_gregset_t *gregsetp, int regno)
2325 {
2326  const struct regset *regset = ppc_linux_gregset (sizeof (long));
2327 
2328  if (regno == -1)
2329  memset (gregsetp, 0, sizeof (*gregsetp));
2330  ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp));
2331 }
2332 
2333 void
2334 supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp)
2335 {
2336  const struct regset *regset = ppc_linux_fpregset ();
2337 
2338  ppc_supply_fpregset (regset, regcache, -1,
2339  fpregsetp, sizeof (*fpregsetp));
2340 }
2341 
2342 void
2344  gdb_fpregset_t *fpregsetp, int regno)
2345 {
2346  const struct regset *regset = ppc_linux_fpregset ();
2347 
2348  ppc_collect_fpregset (regset, regcache, regno,
2349  fpregsetp, sizeof (*fpregsetp));
2350 }
2351 
2352 static int
2354 {
2355  int wordsize = 4;
2356 
2357  /* Check for 64-bit inferior process. This is the case when the host is
2358  64-bit, and in addition the top bit of the MSR register is set. */
2359 #ifdef __powerpc64__
2360  long msr;
2361 
2362  int tid = ptid_get_lwp (inferior_ptid);
2363  if (tid == 0)
2364  tid = ptid_get_pid (inferior_ptid);
2365 
2366  errno = 0;
2367  msr = (long) ptrace (PTRACE_PEEKUSER, tid, PT_MSR * 8, 0);
2368  if (errno == 0 && ppc64_64bit_inferior_p (msr))
2369  wordsize = 8;
2370 #endif
2371 
2372  return wordsize;
2373 }
2374 
2375 static int
2376 ppc_linux_auxv_parse (struct target_ops *ops, gdb_byte **readptr,
2377  gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp)
2378 {
2379  int sizeof_auxv_field = ppc_linux_target_wordsize ();
2380  enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
2381  gdb_byte *ptr = *readptr;
2382 
2383  if (endptr == ptr)
2384  return 0;
2385 
2386  if (endptr - ptr < sizeof_auxv_field * 2)
2387  return -1;
2388 
2389  *typep = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order);
2390  ptr += sizeof_auxv_field;
2391  *valp = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order);
2392  ptr += sizeof_auxv_field;
2393 
2394  *readptr = ptr;
2395  return 1;
2396 }
2397 
2398 static const struct target_desc *
2400 {
2401  int altivec = 0;
2402  int vsx = 0;
2403  int isa205 = 0;
2404  int cell = 0;
2405 
2406  int tid = ptid_get_lwp (inferior_ptid);
2407  if (tid == 0)
2408  tid = ptid_get_pid (inferior_ptid);
2409 
2411  {
2412  struct gdb_evrregset_t evrregset;
2413 
2414  if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0)
2415  return tdesc_powerpc_e500l;
2416 
2417  /* EIO means that the PTRACE_GETEVRREGS request isn't supported.
2418  Anything else needs to be reported. */
2419  else if (errno != EIO)
2420  perror_with_name (_("Unable to fetch SPE registers"));
2421  }
2422 
2424  {
2425  gdb_vsxregset_t vsxregset;
2426 
2427  if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0)
2428  vsx = 1;
2429 
2430  /* EIO means that the PTRACE_GETVSXREGS request isn't supported.
2431  Anything else needs to be reported. */
2432  else if (errno != EIO)
2433  perror_with_name (_("Unable to fetch VSX registers"));
2434  }
2435 
2437  {
2438  gdb_vrregset_t vrregset;
2439 
2440  if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0)
2441  altivec = 1;
2442 
2443  /* EIO means that the PTRACE_GETVRREGS request isn't supported.
2444  Anything else needs to be reported. */
2445  else if (errno != EIO)
2446  perror_with_name (_("Unable to fetch AltiVec registers"));
2447  }
2448 
2449  /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases
2450  the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this
2451  ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only
2452  PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher
2453  half of the register are for Decimal Floating Point, we check if that
2454  feature is available to decide the size of the FPSCR. */
2456  isa205 = 1;
2457 
2459  cell = 1;
2460 
2461  if (ppc_linux_target_wordsize () == 8)
2462  {
2463  if (cell)
2464  return tdesc_powerpc_cell64l;
2465  else if (vsx)
2467  else if (altivec)
2468  return isa205
2470 
2472  }
2473 
2474  if (cell)
2475  return tdesc_powerpc_cell32l;
2476  else if (vsx)
2478  else if (altivec)
2480 
2482 }
2483 
2484 void _initialize_ppc_linux_nat (void);
2485 
2486 void
2488 {
2489  struct target_ops *t;
2490 
2491  /* Fill in the generic GNU/Linux methods. */
2492  t = linux_target ();
2493 
2494  /* Add our register access methods. */
2497 
2498  /* Add our breakpoint/watchpoint methods. */
2514 
2517 
2519 
2520  /* Register the target. */
2523 }
struct gdbarch * target_gdbarch(void)
Definition: gdbarch.c:5143
CORE_ADDR reqstd_address
Definition: breakpoint.h:235
union exp_element elts[1]
Definition: expression.h:85
ULONGEST extract_unsigned_integer(const gdb_byte *, int, enum bfd_endian)
Definition: findvar.c:84
uint32_t num_condition_regs
Definition: ppc-linux-nat.c:79
static int ppc_linux_can_accel_watchpoint_condition(struct target_ops *self, CORE_ADDR addr, int len, int rw, struct expression *cond)
#define PTRACE_SET_DEBUGREG
Definition: ppc-linux-nat.c:55
#define PPC_PTRACE_GETHWDBGINFO
Definition: ppc-linux-nat.c:70
struct ppc_hw_breakpoint * hw_break
static void hwdebug_remove_point(struct ppc_hw_breakpoint *b, int tid)
static int ppc_linux_insert_watchpoint(struct target_ops *self, CORE_ADDR addr, int len, int rw, struct expression *cond)
static void ppc_linux_new_thread(struct lwp_info *lp)
struct observer * observer_attach_thread_exit(observer_thread_exit_ftype *f)
const struct target_desc *(* to_read_description)(struct target_ops *ops) TARGET_DEFAULT_RETURN(NULL)
Definition: target.h:769
static void supply_vsxregset(struct regcache *regcache, gdb_vsxregset_t *vsxregsetp)
int have_ptrace_getsetevrregs
static int hwdebug_point_cmp(struct ppc_hw_breakpoint *a, struct ppc_hw_breakpoint *b)
static int fetch_all_gp_regs(struct regcache *regcache, int tid)
uint64_t features
Definition: ppc-linux-nat.c:82
uint32_t sizeof_condition
Definition: ppc-linux-nat.c:81
enum exp_opcode opcode
Definition: expression.h:65
#define PT_ORIG_R3
Definition: ppc-linux.h:26
bfd_vma CORE_ADDR
Definition: common-types.h:41
struct thread_points * thread_points_p
static int ppc_linux_auxv_parse(struct target_ops *ops, gdb_byte **readptr, gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp)
static int can_use_watchpoint_cond_accel(void)
static void fill_vrregset(const struct regcache *regcache, gdb_vrregset_t *vrregsetp)
void xfree(void *)
Definition: common-utils.c:97
static void store_vsx_registers(const struct regcache *regcache, int tid)
struct target_desc * tdesc_powerpc_isa205_vsx32l
static int ppc_linux_can_use_hw_breakpoint(struct target_ops *self, int type, int cnt, int ot)
#define ALL_LWPS(LP)
Definition: linux-nat.h:123
int ppc_lr_regnum
Definition: ppc-tdep.h:218
struct gdbarch * get_regcache_arch(const struct regcache *regcache)
Definition: regcache.c:297
LONGEST value_as_long(struct value *val)
Definition: value.c:2654
if(!(yy_init))
Definition: ada-lex.c:1072
void linux_nat_set_new_thread(struct target_ops *t, void(*new_thread)(struct lwp_info *))
Definition: linux-nat.c:5040
void ppc_supply_fpregset(const struct regset *regset, struct regcache *regcache, int regnum, const void *fpregs, size_t len)
Definition: rs6000-tdep.c:550
void warning(const char *fmt,...)
Definition: errors.c:26
const struct regset * gregset
Definition: sparc-tdep.h:61
ptid_t ptid
Definition: linux-nat.h:34
static void fetch_gp_regs(struct regcache *regcache, int tid)
struct target_desc * tdesc_powerpc_e500l
Definition: powerpc-e500l.c:8
static void store_altivec_registers(const struct regcache *regcache, int tid)
int ppc_fpscr_regnum
Definition: ppc-tdep.h:228
void internal_error(const char *file, int line, const char *fmt,...)
Definition: errors.c:50
static int store_all_fp_regs(const struct regcache *regcache, int tid, int regno)
static struct ppc_debug_info hwdebug_info
int have_ptrace_getsetvsxregs
#define VEC_unordered_remove(T, V, I)
Definition: vec.h:351
static int ppc_register_u_addr(struct gdbarch *gdbarch, int regno)
static void supply_vrregset(struct regcache *regcache, gdb_vrregset_t *vrregsetp)
int ppc_spefscr_regnum
Definition: ppc-tdep.h:246
static int ppc_linux_insert_mask_watchpoint(struct target_ops *ops, CORE_ADDR addr, CORE_ADDR mask, int rw)
struct target_desc * tdesc_powerpc_32l
Definition: powerpc-32l.c:8
struct target_desc * tdesc_powerpc_isa205_64l
#define VEC_safe_push(T, V, O)
Definition: vec.h:260
#define PTRACE_GETEVRREGS
Definition: ppc-linux.h:81
static void ppc_linux_store_inferior_registers(struct target_ops *ops, struct regcache *regcache, int regno)
const struct regset * ppc_linux_gregset(int wordsize)
int(* to_region_ok_for_hw_watchpoint)(struct target_ops *, CORE_ADDR, int) TARGET_DEFAULT_FUNC(default_region_ok_for_hw_watchpoint)
Definition: target.h:554
static int ppc_linux_stopped_data_address(struct target_ops *target, CORE_ADDR *addr_p)
void _initialize_ppc_linux_nat(void)
#define PTRACE_SETFPREGS
#define _(String)
Definition: gdb_locale.h:40
static int ppc_linux_masked_watch_num_registers(struct target_ops *target, CORE_ADDR addr, CORE_ADDR mask)
int vsx_register_p(struct gdbarch *gdbarch, int regno)
Definition: rs6000-tdep.c:156
int linux_nat_get_siginfo(ptid_t ptid, siginfo_t *siginfo)
Definition: linux-nat.c:5104
int ppc_cr_regnum
Definition: ppc-tdep.h:217
struct gdbarch_tdep * gdbarch_tdep(struct gdbarch *gdbarch)
Definition: gdbarch.c:1402
void supply_gregset(struct regcache *regcache, const gdb_gregset_t *gregsetp)
#define PPC_BREAKPOINT_MODE_MASK
struct target_desc * tdesc_powerpc_cell32l
static void fetch_spe_register(struct regcache *regcache, int tid, int regno)
#define VALUE_LVAL(val)
Definition: value.h:411
#define PPC_DEBUG_FEATURE_DATA_BP_DAWR
static int ppc_linux_ranged_break_num_registers(struct target_ops *target)
PTRACE_TYPE_RET ptrace()
Definition: ptid.h:35
static const struct target_desc * ppc_linux_read_description(struct target_ops *ops)
unsigned long evr[32]
static int check_condition(CORE_ADDR watch_addr, struct expression *cond, CORE_ADDR *data_value, int *len)
static int get_trigger_type(int rw)
struct target_desc * tdesc_powerpc_64l
Definition: powerpc-64l.c:8
Definition: regset.h:34
static int ppc_linux_remove_mask_watchpoint(struct target_ops *ops, CORE_ADDR addr, CORE_ADDR mask, int rw)
#define PPC_FEATURE_HAS_DFP
Definition: ppc-linux.h:43
static int num_memory_accesses(struct value *v)
void free_value_chain(struct value *v)
Definition: value.c:1588
int(* to_insert_watchpoint)(struct target_ops *, CORE_ADDR, int, int, struct expression *) TARGET_DEFAULT_RETURN(-1)
Definition: target.h:532
#define VEC_iterate(T, V, I, P)
Definition: vec.h:165
static size_t max_slots_number
struct type * check_typedef(struct type *type)
Definition: gdbtypes.c:2217
void ppc_collect_gregset(const struct regset *regset, const struct regcache *regcache, int regnum, void *gregs, size_t len)
Definition: rs6000-tdep.c:663
int ppc_vsr0_upper_regnum
Definition: ppc-tdep.h:235
struct target_desc * tdesc_powerpc_cell64l
#define PPC_DEBUG_FEATURE_DATA_BP_RANGE
Definition: ppc-linux-nat.c:88
#define PTRACE_SETEVRREGS
Definition: ppc-linux.h:82
#define PTRACE_GETFPREGS
uint32_t trigger_type
Definition: ppc-linux-nat.c:94
static void store_fp_regs(const struct regcache *regcache, int tid, int regno)
struct target_ops current_target
static void fetch_altivec_registers(struct regcache *regcache, int tid)
int value_lazy(struct value *value)
Definition: value.c:1305
#define PPC_PTRACE_SETHWDEBUG
Definition: ppc-linux-nat.c:71
int ppc_vrsave_regnum
Definition: ppc-tdep.h:240
struct target_desc * tdesc_powerpc_altivec32l
#define PPC_BREAKPOINT_CONDITION_AND
#define PPC_BREAKPOINT_TRIGGER_READ
int(* to_watchpoint_addr_within_range)(struct target_ops *, CORE_ADDR, CORE_ADDR, int) TARGET_DEFAULT_FUNC(default_watchpoint_addr_within_range)
Definition: target.h:548
uint32_t data_bp_alignment
Definition: ppc-linux-nat.c:80
#define PPC_FEATURE_CELL
Definition: ppc-linux.h:37
void * xzalloc(size_t size)
Definition: common-utils.c:91
#define PPC_BREAKPOINT_MODE_EXACT
GDB_GREGSET_T gdb_gregset_t
Definition: gregset.h:34
static struct thread_points * hwdebug_find_thread_points_by_tid(int tid, int alloc_new)
int(* to_remove_watchpoint)(struct target_ops *, CORE_ADDR, int, int, struct expression *) TARGET_DEFAULT_RETURN(-1)
Definition: target.h:529
#define PT_TRAP
Definition: ppc-linux.h:29
#define PPC_FEATURE_BOOKE
Definition: ppc-linux.h:40
int ppc_gp0_regnum
Definition: ppc-tdep.h:214
int target_auxv_search(struct target_ops *ops, CORE_ADDR match, CORE_ADDR *valp)
Definition: auxv.c:375
int ppc_linux_trap_reg_p(struct gdbarch *gdbarch)
static void fetch_register(struct regcache *regcache, int tid, int regno)
int ppc_acc_regnum
Definition: ppc-tdep.h:245
static void calculate_dvc(CORE_ADDR addr, int len, CORE_ADDR data_value, uint32_t *condition_mode, uint64_t *condition_value)
int have_ptrace_getvrregs
GDB_FPREGSET_T gdb_fpregset_t
Definition: gregset.h:35
static void set_spe_registers(int tid, struct gdb_evrregset_t *evrregset)
enum bfd_endian gdbarch_byte_order(struct gdbarch *gdbarch)
Definition: gdbarch.c:1420
static int fetch_all_fp_regs(struct regcache *regcache, int tid)
void fill_fpregset(const struct regcache *regcache, gdb_fpregset_t *fpregsetp, int regno)
struct cleanup * make_cleanup(make_cleanup_ftype *function, void *arg)
Definition: cleanups.c:117
#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
int(* to_masked_watch_num_registers)(struct target_ops *, CORE_ADDR, CORE_ADDR) TARGET_DEFAULT_RETURN(-1)
Definition: target.h:562
Definition: gdbtypes.h:749
#define PPC_BREAKPOINT_TRIGGER_WRITE
static int store_all_gp_regs(const struct regcache *regcache, int tid, int regno)
#define PPC_PTRACE_DELHWDEBUG
Definition: ppc-linux-nat.c:72
static void get_spe_registers(int tid, struct gdb_evrregset_t *evrregset)
static int ppc_linux_watchpoint_addr_within_range(struct target_ops *target, CORE_ADDR addr, CORE_ADDR start, int length)
static long saved_dabr_value
char gdb_vrregset_t[SIZEOF_VRREGS]
struct target_desc * tdesc_powerpc_isa205_altivec64l
#define gdb_assert(expr)
Definition: gdb_assert.h:33
void ppc_collect_fpregset(const struct regset *regset, const struct regcache *regcache, int regnum, void *fpregs, size_t len)
Definition: rs6000-tdep.c:710
const char * gdbarch_register_name(struct gdbarch *gdbarch, int regnr)
Definition: gdbarch.c:2117
void linux_nat_add_target(struct target_ops *t)
Definition: linux-nat.c:4972
static void fetch_ppc_registers(struct regcache *regcache, int tid)
static int ppc_linux_stopped_by_watchpoint(struct target_ops *ops)
static void fetch_altivec_register(struct regcache *regcache, int tid, int regno)
struct value * value_next(struct value *value)
Definition: value.c:1015
int deprecated_value_modifiable(struct value *value)
Definition: value.c:1490
static int ppc_linux_remove_watchpoint(struct target_ops *self, CORE_ADDR addr, int len, int rw, struct expression *cond)
CORE_ADDR placed_address
Definition: breakpoint.h:232
struct target_ops * linux_target(void)
Definition: linux-nat.c:4544
void * xmalloc(YYSIZE_T)
int(* to_insert_hw_breakpoint)(struct target_ops *, struct gdbarch *, struct bp_target_info *) TARGET_DEFAULT_RETURN(-1)
Definition: target.h:520
int(* to_remove_mask_watchpoint)(struct target_ops *, CORE_ADDR, CORE_ADDR, int) TARGET_DEFAULT_RETURN(1)
Definition: target.h:539
#define VEC_last(T, V)
Definition: vec.h:142
static void ppc_linux_thread_exit(struct thread_info *tp, int silent)
#define PPC_DEBUG_FEATURE_DATA_BP_MASK
Definition: ppc-linux-nat.c:89
int have_ptrace_getsetfpregs
#define VEC_empty(T, V)
Definition: vec.h:132
Definition: value.c:172
int ptid_get_pid(ptid_t ptid)
Definition: ptid.c:52
const struct regset * ppc_linux_fpregset(void)
static void ppc_linux_fetch_inferior_registers(struct target_ops *ops, struct regcache *regcache, int regno)
int(* to_auxv_parse)(struct target_ops *ops, gdb_byte **readptr, gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp) TARGET_DEFAULT_FUNC(default_auxv_parse)
Definition: target.h:784
uint64_t condition_value
Definition: ppc-linux-nat.c:99
#define PTRACE_SETVRREGS
Definition: ppc-linux.h:68
int(* to_remove_hw_breakpoint)(struct target_ops *, struct gdbarch *, struct bp_target_info *) TARGET_DEFAULT_RETURN(-1)
Definition: target.h:523
bfd_byte gdb_byte
Definition: common-types.h:38
int ppc_ctr_regnum
Definition: ppc-tdep.h:219
void fetch_subexp_value(struct expression *exp, int *pc, struct value **valp, struct value **resultp, struct value **val_chain, int preserve_errors)
Definition: eval.c:210
VEC(thread_points_p)
int ppc_vr0_regnum
Definition: ppc-tdep.h:239
int have_ptrace_getsetregs
void discard_cleanups(struct cleanup *old_chain)
Definition: cleanups.c:213
ULONGEST align_up(ULONGEST v, int n)
Definition: utils.c:2963
static unsigned long ppc_linux_get_hwcap(void)
void(* to_fetch_registers)(struct target_ops *, struct regcache *, int) TARGET_DEFAULT_IGNORE()
Definition: target.h:472
static int ppc_linux_target_wordsize(void)
void void void void void void void void void perror_with_name(const char *string) ATTRIBUTE_NORETURN
Definition: utils.c:979
static void fetch_fp_regs(struct regcache *regcache, int tid)
int(* to_can_use_hw_breakpoint)(struct target_ops *, int, int, int) TARGET_DEFAULT_RETURN(0)
Definition: target.h:516
#define SIZEOF_VRREGS
ptid_t ptid
Definition: gdbthread.h:169
int xsnprintf(char *str, size_t size, const char *format,...)
Definition: common-utils.c:134
struct hw_break_tuple * hw_breaks
static void fill_vsxregset(const struct regcache *regcache, gdb_vsxregset_t *vsxregsetp)
ptid_t inferior_ptid
Definition: infcmd.c:124
int(* to_can_accel_watchpoint_condition)(struct target_ops *, CORE_ADDR, int, int, struct expression *) TARGET_DEFAULT_RETURN(0)
Definition: target.h:558
static void store_spe_register(const struct regcache *regcache, int tid, int regno)
int ppc_ev0_upper_regnum
Definition: ppc-tdep.h:243
#define PTRACE_GETVRREGS
Definition: ppc-linux.h:67
static void store_gp_regs(const struct regcache *regcache, int tid, int regno)
static void create_watchpoint_request(struct ppc_hw_breakpoint *p, CORE_ADDR addr, int len, int rw, struct expression *cond, int insert)
int ppc_ps_regnum
Definition: ppc-tdep.h:216
#define PPC_DEBUG_FEATURE_INSN_BP_RANGE
Definition: ppc-linux-nat.c:86
int offset
Definition: agent.c:65
#define PTRACE_GETVSXREGS
Definition: ppc-linux.h:73
int(* to_ranged_break_num_registers)(struct target_ops *) TARGET_DEFAULT_RETURN(-1)
Definition: target.h:518
int ppc_xer_regnum
Definition: ppc-tdep.h:220
#define SIZEOF_VSXREGS
#define PTRACE_SETREGS
int ppc_mq_regnum
Definition: ppc-tdep.h:231
uint32_t condition_mode
Definition: ppc-linux-nat.c:96
int(* to_stopped_by_watchpoint)(struct target_ops *) TARGET_DEFAULT_RETURN(0)
Definition: target.h:542
struct m32c_reg regs[M32C_MAX_NUM_REGS]
Definition: m32c-tdep.c:105
struct target_desc * tdesc_powerpc_isa205_32l
unsigned long long acc
void supply_fpregset(struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
#define PPC_DEBUG_CURRENT_VERSION
void regcache_raw_supply(struct regcache *regcache, int regnum, const void *buf)
Definition: regcache.c:1041
struct target_desc * tdesc_powerpc_vsx64l
Definition: powerpc-vsx64l.c:8
static int ppc_linux_insert_hw_breakpoint(struct target_ops *self, struct gdbarch *gdbarch, struct bp_target_info *bp_tgt)
int register_size(struct gdbarch *gdbarch, int regnum)
Definition: regcache.c:169
long ptid_get_lwp(ptid_t ptid)
Definition: ptid.c:60
struct type * value_type(const struct value *value)
Definition: value.c:1021
struct target_desc * tdesc_powerpc_vsx32l
Definition: powerpc-vsx32l.c:8
void regcache_raw_collect(const struct regcache *regcache, int regnum, void *buf)
Definition: regcache.c:1071
uint32_t version
Definition: ppc-linux-nat.c:76
int gdbarch_pc_regnum(struct gdbarch *gdbarch)
Definition: gdbarch.c:1998
#define PTRACE_TYPE_ARG3
Definition: config.h:658
struct target_desc * tdesc_powerpc_isa205_vsx64l
static void store_ppc_registers(const struct regcache *regcache, int tid)
uint32_t num_data_bps
Definition: ppc-linux-nat.c:78
#define PTRACE_SETVSXREGS
Definition: ppc-linux.h:74
#define TYPE_LENGTH(thistype)
Definition: gdbtypes.h:1237
int altivec_register_p(struct gdbarch *gdbarch, int regno)
Definition: rs6000-tdep.c:168
unsigned long spefscr
static void store_register(const struct regcache *regcache, int tid, int regno)
static void fetch_vsx_registers(struct regcache *regcache, int tid)
int spe_register_p(struct gdbarch *gdbarch, int regno)
Definition: rs6000-tdep.c:180
int(* to_stopped_data_address)(struct target_ops *, CORE_ADDR *) TARGET_DEFAULT_RETURN(0)
Definition: target.h:546
static void store_vsx_register(const struct regcache *regcache, int tid, int regno)
CORE_ADDR value_address(const struct value *value)
Definition: value.c:1440
struct target_desc * tdesc_powerpc_altivec64l
static void hwdebug_insert_point(struct ppc_hw_breakpoint *b, int tid)
void(* to_store_registers)(struct target_ops *, struct regcache *, int) TARGET_DEFAULT_NORETURN(noprocess())
Definition: target.h:474
Definition: defs.h:353
#define PPC_BREAKPOINT_TRIGGER_EXECUTE
static int ppc_linux_remove_hw_breakpoint(struct target_ops *self, struct gdbarch *gdbarch, struct bp_target_info *bp_tgt)
static int ppc_linux_region_ok_for_hw_watchpoint(struct target_ops *self, CORE_ADDR addr, int len)
uint32_t num_instruction_bps
Definition: ppc-linux-nat.c:77
int(* to_insert_mask_watchpoint)(struct target_ops *, CORE_ADDR, CORE_ADDR, int) TARGET_DEFAULT_RETURN(1)
Definition: target.h:536
int ppc_fp0_regnum
Definition: ppc-tdep.h:227
static void store_altivec_register(const struct regcache *regcache, int tid, int regno)
void ppc_supply_gregset(const struct regset *regset, struct regcache *regcache, int regnum, const void *gregs, size_t len)
Definition: rs6000-tdep.c:505
#define PPC_BREAKPOINT_CONDITION_BE(n)
#define wordsize
struct target_desc * tdesc_powerpc_isa205_altivec32l
DEF_VEC_P(thread_points_p)
#define PTRACE_GETREGS
static void fetch_vsx_register(struct regcache *regcache, int tid, int regno)
const ULONGEST const LONGEST len
Definition: target.h:309
char gdb_vsxregset_t[SIZEOF_VSXREGS]
#define PPC_BREAKPOINT_CONDITION_NONE
void fill_gregset(const struct regcache *regcache, gdb_gregset_t *gregsetp, int regno)